JP2008016615A - Bipolar transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a rapidly-operating bipolar transistor with a p-type base comprising a two-dimensional hole gas layer and comprising nitride semiconductor. <P>SOLUTION: The bipolar transistor comprises an emitter layer including a first semiconductor layer 14 comprising the nitride semiconductor; a base layer comprising the nitride semiconductor with a band gap narrower than that of the first semiconductor layer 14 and including a second semiconductor layer 15 formed in contact with the first semiconductor layer 14; and a collector layer including a third semiconductor layer 16 comprising the nitride semiconductor formed in contact with the surface of the second semiconductor layer 15 on the opposite side of the first semiconductor layer 14. The two dimensional hole gas layer is generated in an interfacial region between the first semiconductor layer 14 and the second semiconductor layer 15 of the second semiconductor layer 15, and a base electrode 19 selectively formed so as to contact with a part of the base layer is in ohmic contact with the two dimensional hole gas layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a bipolar transistor, and more particularly to a bipolar transistor capable of high-speed operation.

  One type of vertical device in which electrons run in a direction perpendicular to a semiconductor substrate is a heterojunction bipolar transistor (HBT) using a heterojunction of a compound semiconductor. Since the HBT has a band offset between the base layer and the emitter, holes are confined in the base layer. Therefore, even if the hole concentration in the base layer is increased, electrons are injected from the emitter to the collector. Efficiency does not decrease. As a result, a low base layer resistance is obtained, and a high maximum oscillation frequency (fmax) can be realized.

  However, in order to increase the current cutoff frequency (ft), which is another index when the transistor operates at high speed, electrons injected from the emitter are reduced by reducing the impurity concentration of the base layer and reducing the thickness. It is desirable to have a structure in which is not scattered in the base layer. In view of this point, an inversion base layer bipolar transistor using an undoped aluminum arsenide (AlAs) as an emitter and a p-type inversion layer formed at the interface with an n-type gallium arsenide (n-GaAs) collector (Inversion base transistor: IBT) has been proposed in the mid 1980s (see, for example, Non-Patent Document 1).

  This IBT can be expected to have a very high ft because the thickness of the base layer is extremely thin and the scattering of electrons and p-type impurities generated in the conventional HBT is eliminated.

  However, while HBT has been successfully put into practical use as a high-power transistor for mobile phone terminals, IBT has reached the present day without going out of research. One reason for this is presumed that an electron trap was generated at the heterojunction interface between GaAs and AlAs due to a crystallinity problem, and a good inversion layer could not be obtained. As a result, a sufficient current gain could not be obtained.

On the other hand, in recent years, crystal growth technology for nitride semiconductors represented by gallium nitride (GaN) as a wide band gap material has greatly advanced. GaN has a band gap of 3.4 eV, which is larger than 1.4 eV of GaAs, and has a dielectric breakdown electric field that is one digit higher, making it suitable for high voltage devices. Furthermore, since the saturation rate of electrons is higher than that of GaAs, high speed is greatly expected. Using this GaN, FETs that allow electrons to run parallel to the semiconductor substrate are being actively developed. As a specific structure, an HFET (Hetero-structure field effect transistor) in which aluminum gallium nitride (AlGaN) and GaN are heterojunction is common. In this case, by having spontaneous polarization and piezo polarization caused by lattice distortion, a two-dimensional electron gas of about 1 × 10 ¹³ cm ⁻² is generated and large even if no impurity is doped at the heterojunction interface. It is possible to pass an electric current. As a result, GaN-based HFETs are being put to practical use in transmission devices for mobile phone base stations.

An HBT that is representative of a vertical device has also been disclosed in which a nitride semiconductor is used and electrons are caused to travel through the base layer at high speed using an electric field in the base layer generated by polarization (for example, patents). See reference 1.) However, in GaN-based devices, development of vertical HBT has not progressed much compared to horizontal HFETs. The main reason is that the activation rate of the p-type dopant is low in the nitride-based semiconductor, and it is difficult to obtain a high-concentration p-type layer. For example, the carrier concentration obtained by doping Mg with 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ as a p-type impurity in GaN is about 5 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁸ cm ^−3. Only. For this reason, it is difficult to reduce the base layer resistance as compared with GaAs-based and InP-based HBTs that can easily obtain a carrier concentration of 1 × 10 ¹⁹ cm ⁻³ or more. Therefore, an IBT using an inversion layer instead of a p-type impurity is considered as a vertical device convenient for a nitride semiconductor.
JP 2005-79417 A K. Matsumoto et al., “GaAs Inversion-Base Bipolar Transistor (GaAs IBT)”, IEEE Electron Device Letters, 1986, Vol. EDL-7, no. 11, p. 627-628

  However, an IBT having a structure in which a collector layer made of i-GaN, a base layer made of i-GaN, and an emitter layer made of i-AlGaN are sequentially stacked on a substrate does not operate normally.

When a nitride semiconductor layer is epitaxially grown on a substrate by metal organic chemical vapor deposition (MOCVD), the base layer is in contact with the nitrogen (N) surface of the emitter layer because it normally grows with the Ga surface facing upward. Therefore, as shown in the band diagram of FIG. 9, positive fixed charges are generated at the interface between the emitter layer made of i-AlGaN and the base layer made of i-GaN due to spontaneous polarization and piezo polarization, and compensate for it. Two-dimensional electron gas is generated. Even if a negative voltage V _EB is applied between the emitter layer and the base layer in this state, only the concentration of the two-dimensional electron gas is lowered and no holes are generated. That is, it does not operate as a bipolar transistor.

  Even if a p-type impurity is introduced into the interface between the emitter layer and the base layer, it is difficult to realize a high p-type concentration because of positive fixed charges. Therefore, in the case of using a nitride-based semiconductor, even if a transistor having a structure in which a collector layer, a base layer, and an emitter layer are sequentially stacked is formed, an inversion in which an undoped layer or an n-type layer is inverted There is a problem that the layer cannot be operated as an IBT having a p-type base.

  The present invention solves the above-mentioned conventional problems, and realizes a bipolar transistor which is made of a nitride semiconductor and operates at high speed based on a two-dimensional hole gas layer formed in an undoped layer or a low-concentration n-type layer. The purpose is to be able to.

  In order to achieve the above object, the present invention has a bipolar transistor including a two-dimensional hole gas layer and a base electrode ohmically connected to the two-dimensional hole gas layer.

  Specifically, the bipolar transistor according to the present invention is formed with an emitter layer including a first nitride semiconductor layer and a band gap smaller than that of the first nitride semiconductor layer and in contact with the first nitride semiconductor layer. A base layer including the second nitride semiconductor layer formed, and a third nitride semiconductor layer formed in contact with a surface of the second nitride semiconductor layer opposite to the first nitride semiconductor layer. A collector layer including the two-dimensional hole gas layer generated in an interface region between the first nitride semiconductor layer and the second nitride semiconductor layer in the second nitride semiconductor layer, and a part of the base layer And a base electrode that is selectively formed and is in ohmic contact with the two-dimensional hole gas layer.

  According to the bipolar transistor of the present invention, since the two-dimensional hole gas layer and the base electrode ohmically connected to the two-dimensional hole gas layer are provided, the two-dimensional hole gas layer in the base layer is generated. It is possible to control the amount of electrons injected into the base region, which is a region in accordance with the value of the voltage applied between the base emitters. Further, the electrons injected into the base region due to the internal electric field generated on the collector layer side reach the collector layer, and can be operated as a bipolar transistor.

  In the bipolar transistor of the present invention, it is preferable that the first nitride semiconductor layer contains gallium as a group III element, and the second nitride semiconductor layer is in contact with the gallium surface of the first nitride semiconductor layer. With such a configuration, a two-dimensional hole gas layer can be reliably generated in the interface region between the first nitride semiconductor layer and the second nitride semiconductor layer.

  In the bipolar transistor of the present invention, the base layer is formed between the second nitride semiconductor layer and the base electrode, and the fourth nitride semiconductor layer having a larger band gap than the second nitride semiconductor layer is formed. It is preferable to include. With such a configuration, a potential barrier can be formed between the base electrode and the base layer. Accordingly, since the base current injected directly from the emitter into the base electrode can be reduced, a bipolar transistor having a high current amplification factor and operating at high speed can be realized.

  In this case, the fourth nitride semiconductor layer is preferably made of a semiconductor material doped with p-type impurities. With such a configuration, the contact resistance of the base electrode can be reliably reduced.

  In the bipolar transistor of the present invention, the emitter layer is formed on the surface of the first nitride semiconductor layer opposite to the second nitride semiconductor layer in the first nitride semiconductor layer, and the first nitride semiconductor layer A fifth nitride semiconductor layer having a band gap smaller than that of the semiconductor layer, and a fifth nitride semiconductor layer formed on a surface of the fifth nitride semiconductor layer opposite to the first nitride semiconductor layer; It is preferable to have a resonant tunneling diode structure in which a sixth nitride semiconductor layer having a larger band gap is stacked. With such a configuration, electrons are injected from the emitter layer to the base region by the resonant tunneling effect. Therefore, the emitter dynamic resistance is reduced, so that the emitter charging time can be shortened. As a result, a bipolar transistor having a high cutoff frequency ft can be realized.

  The bipolar transistor of the present invention preferably further includes a substrate, and the emitter layer, the base layer, and the collector layer are sequentially formed on the substrate from the emitter layer. With such a configuration, electrons injected from the emitter layer into the base region reach the collector layer without being scattered by impurities. Accordingly, it is possible to realize a hot electron transistor having a higher speed than a normal bipolar transistor.

  In this case, the substrate is preferably made of sapphire or silicon carbide.

  According to the bipolar transistor of the present invention, a bipolar transistor having a two-dimensional hole gas layer as a p-type base and made of a nitride semiconductor and operating at high speed can be realized.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional configuration of a bipolar transistor according to the first embodiment.

  As shown in FIG. 1, the transistor of the present embodiment is an inverted base layer bipolar transistor (IBT) formed on a sapphire substrate 11 having a (0001) plane of the plane orientation as a main surface.

  A buffer layer 12 made of aluminum nitride (AlN) is formed on the main surface of the sapphire substrate 11. On the buffer layer 12, a heavily doped layer 13 and a first semiconductor layer 14 as an emitter layer are formed. The second semiconductor layer 15 as the base layer, the third semiconductor layer 16 as the collector layer, and the heavily doped layer 17 are sequentially formed by epitaxial growth.

The heavily doped layer 13 includes, for example, n ⁺ -GaN having a thickness of 500 nm, including an n-type impurity of 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ . The first semiconductor layer 14 is made of undoped i-Al ₀ . ₂ Ga ₀ . ₈ N. The second semiconductor layer 15 is made of i-GaN having an undoped thickness of 30 nm. The third semiconductor layer 16 is made of n-GaN having an n-type impurity of 1 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ¹⁷ cm ⁻³ and a thickness of 300 nm. The heavily doped layer 17 includes n ⁺ -GaN having a thickness of 20 nm, including an n-type impurity of 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ .

  A collector electrode 18 is formed on the heavily doped layer 17, a base electrode 19 is formed on the second semiconductor layer 15, and an emitter electrode 20 is formed on the heavily doped layer 13. Yes.

FIG. 2 shows a band structure when a voltage V _EB is applied between the first semiconductor layer 14 and the second semiconductor layer 15 in the bipolar transistor of this embodiment. In general, when GaN is crystal-grown by metal organic chemical vapor deposition (MOCVD), a gallium (Ga) surface grows. Therefore, in the bipolar transistor of this embodiment, the upper surface of the first semiconductor layer 14 that is an emitter is a Ga surface, and the second semiconductor layer 15 that is a base is in contact with the Ga surface of the first semiconductor layer 14. Yes. For this reason, a two-dimensional hole gas layer is generated at the interface between the first semiconductor layer 14 and the second semiconductor layer 15 having a band gap smaller than that of the first semiconductor layer 14. In the case of this embodiment, the concentration of the two-dimensional hole gas is about 1 × 10 ¹³ cm ⁻² .

Therefore, the base electrode 19 formed on the second semiconductor layer 15 and the base region where the two-dimensional hole gas exists in the second semiconductor layer 15 are equipotential. That is, the two-dimensional hole gas and the base electrode 19 are electrically ohmically connected, and the amount of electrons injected into the base region where the two-dimensional hole gas layer is generated in the base layer is , V _EB is controlled according to the value. Furthermore, a bipolar transistor operation in which electrons injected into the base region reach the third semiconductor layer 16 is realized by an internal electric field generated on the third semiconductor layer 16 side.

  In the present invention, since the base region is a region where the two-dimensional hole gas is generated, the thickness of the base region is substantially determined by the thickness of the two-dimensional hole gas layer. Since the thickness of the two-dimensional hole gas layer is as thin as 10 nm or less, the operation speed of the bipolar transistor can be increased. The thickness of the two-dimensional hole gas layer is preferably 3 nm to 10 nm because the base layer resistance increases if it is too thin.

(Second Embodiment)
The second embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows a cross-sectional configuration of a bipolar transistor according to the second embodiment. In FIG. 3, the same components as those in FIG.

As shown in FIG. 3, the bipolar transistor of this embodiment includes a second semiconductor layer 15 whose base is made of i-GaN, p-Al ₀ . ₂ Ga ₀ . _The base electrode 19 is formed on the fourth semiconductor layer 21. The fourth semiconductor layer 21 is made of 8N.

In the present embodiment, electrons injected from the first semiconductor layer 14 that is the emitter layer into the external base region that is the region below the base electrode 19 in the second semiconductor layer 15 reach the base electrode 19. The probability is set so that the second semiconductor layer 15 made of i-GaN and p-Al ₀ . ₂ Ga ₀ . _This can be reduced by the effect of the band offset with the fourth semiconductor layer 21 made of 8N.

FIG. 4 shows a band structure in the external base region and the first semiconductor layer 14 of the present embodiment. As shown in FIG. 4, p-Al ₀ . ₂ Ga ₀ . _A potential barrier is formed by the fourth semiconductor layer 21 made of 8N. This potential barrier reduces the probability that electrons injected from the first semiconductor layer 14 to the external base region will reach the base electrode 19. Thereby, since the base current is reduced, a bipolar transistor having a high current amplification factor and operating at high speed can be realized.

  Below, the manufacturing method of the bipolar transistor which concerns on this embodiment is demonstrated with reference to drawings. 5 and 6 show a method of manufacturing the bipolar transistor according to this embodiment in the order of steps.

First, as shown in FIG. 5A, a buffer layer 12 made of AlN is formed on a sapphire substrate 11 whose main surface is the (0001) plane of the plane orientation. Subsequently, on the buffer layer 12, the heavily doped layer 13 made of n ⁺ -GaN having a thickness of 500 nm, i-Al ₀ . ₂ Ga ₀ . First semiconductor layer 14 made of ₈ N, second semiconductor layer 15 made of undoped i-GaN having a thickness of 30 nm, and fourth semiconductor made of p-AlGaN doped in p-type and having a thickness of 30 nm Layer 21 is epitaxially grown sequentially by MOCVD.

Next, as shown in FIG. 5B, a silicon oxide (SiO ₂ ) film 30 having a thickness of 100 nm is deposited on the fourth semiconductor layer 21, and then subjected to normal photolithography and wet etching processes. An opening 30a that exposes the fourth semiconductor layer 21 is formed.

Next, as shown in FIG. 5C, dry etching using chlorine gas is performed using the SiO ₂ film 30 as a mask to etch the fourth semiconductor layer 21 to expose the second semiconductor layer 15. .

Next, as shown in FIG. 5D, a third layer of n-GaN having a thickness of 300 nm doped n-type is formed on the portion exposed from the opening of the second semiconductor layer 15 by MOCVD. The semiconductor layer 16 and the heavily doped layer 17 made of n ⁺ -GaN having an n-type doped thickness of 20 nm are sequentially epitaxially regrown. Since the nitride semiconductor is not grown on the SiO ₂ film 30, the third semiconductor layer 16 and the highly doped layer 17 are grown only in the portion exposed from the opening in the second semiconductor layer 15. Selective regrowth.

Next, as shown in FIG. 6A, the SiO ₂ film 30 is removed by wet etching with hydrofluoric acid. Further, as shown in FIG. 6B, the fourth semiconductor layer 21, the second semiconductor layer 15, and a part of the first semiconductor layer 14 are selected by ordinary photolithography and dry etching using chlorine gas. The heavily doped layer 13 is exposed by etching.

  Next, after forming a resist pattern (not shown) by ordinary photolithography as shown in FIG. 6C, Ti having a thickness of 20 nm and Al having a thickness of 300 nm are vapor-deposited to form a resist pattern. The emitter film 20 and the collector electrode 18 are formed on the heavily doped layer 13 and the heavily doped layer 17, respectively, by lifting off the metal film deposited thereon. Subsequently, the emitter electrode 20 and the collector electrode 18 are brought into ohmic contact by performing heat treatment at 650 ° C.

  Next, as shown in FIG. 6D, the base electrode 19 in which Pd having a thickness of 100 nm and Au having a thickness of 300 nm are stacked is formed as a fourth semiconductor layer by using normal photolithography and lift-off. 21 is formed. Subsequently, the base electrode 19 is brought into ohmic contact by performing heat treatment at 450 ° C.

  In this embodiment, a sapphire substrate is used as the substrate, but a silicon carbide (SiC) substrate may be used. Although the SiC substrate is expensive, a semiconductor layer having a lattice constant close to that of GaN and good epitaxial film quality can be obtained.

Further, an n-type impurity such as silicon is introduced into the high concentration doped layer 13 and the high concentration doped layer 17 so as to be 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ^−3, and the third semiconductor layer 16 may be introduced with an n-type impurity so as to be 1 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ¹⁷ cm ⁻³ . The thickness of the first semiconductor layer 14 is preferably 10 nm to 30 nm, the thickness of the second semiconductor layer 15 is preferably 10 nm to 50 nm, and the thickness of the third semiconductor layer 16 is The film thickness is preferably 200 nm to 500 nm.

(Third embodiment)
The third embodiment of the present invention will be described below with reference to the drawings. FIG. 7 shows a cross-sectional structure of a bipolar transistor according to the third embodiment. In FIG. 7, the same components as those of FIG.

  As shown in FIG. 7, the bipolar transistor of this embodiment is characterized in that the emitter layer is formed by a resonant tunnel diode structure 24. Specifically, the emitter layer includes a sixth semiconductor layer 23, a fifth semiconductor layer 22, and a first semiconductor layer 14 that are sequentially stacked from the bottom.

The first semiconductor layer 14 and the sixth semiconductor layer 23 are undoped i-Al ₀ . ₂ Ga ₀ . Consist ₈ N, the fifth semiconductor layer 22 has a thickness of an undoped consists 4nm of i-GaN. FIG. 8 shows the band structure of the bipolar transistor of this embodiment. As shown in FIG. 8, a resonant tunnel diode structure 24 is formed in which the first semiconductor layer 14 and the sixth semiconductor layer 23 serve as barrier layers and the fifth semiconductor layer 22 serves as a well layer. With such a configuration, electrons are injected from the emitter layer to the base region by the resonant tunneling effect. For this reason, the emitter dynamic resistance is reduced, so that the emitter charging time is shortened. As a result, a bipolar transistor having a high cutoff frequency ft can be realized.

In each embodiment, i-Al ₀ . ₂ Ga ₀ . An example is shown in which ₈ N is used and i-GaN is used for the second semiconductor layer. In addition, two types of compounds selected from nitride semiconductors represented by the general formula InxAlyGa (1-xy) N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1), The one with the larger band gap may be the first semiconductor layer 14, and the one with the smaller band gap may be the second semiconductor layer 15. Note that the first semiconductor layer is preferably undoped, but may be n-type with an n-type impurity concentration of 10 ¹⁷ cm ⁻³ or less, and p when the p-type impurity concentration is 10 ¹⁶ cm ⁻³ or less. It may be a mold. The third semiconductor layer 16 is the same as the second semiconductor layer 15 in order to reduce the thickness of the two-dimensional hole gas layer and to prevent scattering of electrons injected into the base at the base collector interface. Nitride semiconductors having a composition ratio are preferable, but nitride semiconductors having different composition ratios may be used. The n-type impurity concentration of the third semiconductor layer 16 is preferably in the range of 1 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ¹⁷ cm ⁻³ , but may be undoped, and the p-type impurity concentration is 10 ^16. If it is cm ⁻³ or less, it may be p-type.

In order to reduce the scattering of electrons in the base region and operate the bipolar transistor at high speed, the second semiconductor layer 15 serving as the base is preferably undoped. However, if it is 10 ¹⁶ cm ⁻³ or less, there is no problem even if n-type or p-type impurities are contained.

  In each embodiment, the case where the Ga surface is grown on the substrate using the MOCVD method has been described. However, it is also possible to grow the N plane by using molecular beam epitaxy (MBE) method or the like. In this case, the semiconductor layer is formed so that the second semiconductor layer is in contact with the Ga plane of the first semiconductor layer 14. The order of stacking may be changed.

  The bipolar transistor according to the present invention can be realized as a bipolar transistor which has a two-dimensional hole gas layer as a p-type base and is made of a nitride semiconductor and operates at high speed, and is useful as a bipolar transistor capable of high-speed operation.

1 is a cross-sectional view showing a bipolar transistor according to a first embodiment of the present invention. It is a band figure showing the band structure of the bipolar transistor concerning a 1st embodiment of the present invention. It is sectional drawing which shows the bipolar transistor which concerns on the 2nd Embodiment of this invention. It is a band figure which shows the band structure in the external base area | region of the bipolar transistor which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the bipolar transistor which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the bipolar transistor which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the bipolar transistor which concerns on the 3rd Embodiment of this invention. It is a band diagram which shows the band structure of the bipolar transistor which concerns on the 3rd Embodiment of this invention. It is a band figure which shows the band structure for demonstrating the subject in the conventional transistor.

Explanation of symbols

11 Substrate 12 Buffer layer 13 Highly doped layer 14 First semiconductor layer 15 Second semiconductor layer 16 Third semiconductor layer 17 Highly doped layer 18 Collector electrode 19 Base electrode 20 Emitter electrode 21 Fourth semiconductor layer 22 5 semiconductor layer 23 sixth semiconductor layer 24 resonant tunnel diode structure 30 silicon oxide film

Claims (9)

An emitter layer including a first nitride semiconductor layer;
A base layer including a second nitride semiconductor layer having a smaller band gap than the first nitride semiconductor layer and formed in contact with the first nitride semiconductor layer;
A collector layer including a third nitride semiconductor layer formed in contact with a surface of the second nitride semiconductor layer opposite to the first nitride semiconductor layer;
A two-dimensional hole gas layer generated in an interface region between the first nitride semiconductor layer and the second nitride semiconductor layer in the second nitride semiconductor layer;
A bipolar transistor, comprising: a base electrode selectively formed so as to be in contact with a part of the base layer and in ohmic contact with the two-dimensional hole gas layer. The first nitride semiconductor layer includes gallium as a group III element;
2. The bipolar transistor according to claim 1, wherein the second nitride semiconductor layer is in contact with a gallium surface of the first nitride semiconductor layer.   The base layer includes a fourth nitride semiconductor layer formed between the second nitride semiconductor layer and the base electrode and having a band gap larger than that of the second nitride semiconductor layer. The bipolar transistor according to claim 1.   4. The bipolar transistor according to claim 3, wherein the fourth nitride semiconductor layer is made of a semiconductor material doped with p-type impurities.   The emitter layer is formed on the surface of the first nitride semiconductor layer opposite to the second nitride semiconductor layer in the first nitride semiconductor layer, and the first nitride semiconductor layer A fifth nitride semiconductor layer having a smaller band gap than the fifth nitride semiconductor layer, and a surface of the fifth nitride semiconductor layer opposite to the first nitride semiconductor layer; 5. The bipolar transistor according to claim 1, wherein the bipolar transistor has a resonant tunnel diode structure in which a sixth nitride semiconductor layer having a larger band gap is stacked.   6. The bipolar transistor according to claim 1, wherein the second nitride semiconductor layer is made of a semiconductor material not doped with impurities.   The bipolar transistor according to any one of claims 1 to 6, wherein the second nitride semiconductor layer and the third nitride semiconductor layer are made of the same semiconductor material. Further comprising a substrate,
The bipolar transistor according to claim 1, wherein the emitter layer, the base layer, and the collector layer are sequentially formed on the substrate from the emitter layer.   The bipolar transistor according to claim 8, wherein the substrate is made of sapphire or silicon carbide.

Images