CN111081543A - Bipolar triode based on two-dimensional material/gallium nitride and preparation method thereof - Google Patents
Bipolar triode based on two-dimensional material/gallium nitride and preparation method thereof Download PDFInfo
- Publication number
- CN111081543A CN111081543A CN201911365414.3A CN201911365414A CN111081543A CN 111081543 A CN111081543 A CN 111081543A CN 201911365414 A CN201911365414 A CN 201911365414A CN 111081543 A CN111081543 A CN 111081543A
- Authority
- CN
- China
- Prior art keywords
- type doped
- iii
- dimensional material
- layer
- nitride layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 50
- 239000000463 material Substances 0.000 title claims abstract description 50
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 35
- 238000002360 preparation method Methods 0.000 title claims abstract description 6
- 150000004767 nitrides Chemical class 0.000 claims abstract description 49
- 238000000151 deposition Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 31
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910015844 BCl3 Inorganic materials 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 3
- ROUIDRHELGULJS-UHFFFAOYSA-N bis(selanylidene)tungsten Chemical compound [Se]=[W]=[Se] ROUIDRHELGULJS-UHFFFAOYSA-N 0.000 claims description 3
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- HITXEXPSQXNMAN-UHFFFAOYSA-N bis(tellanylidene)molybdenum Chemical compound [Te]=[Mo]=[Te] HITXEXPSQXNMAN-UHFFFAOYSA-N 0.000 claims description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 2
- 238000001465 metallisation Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 description 8
- 229910002704 AlGaN Inorganic materials 0.000 description 7
- 229910003090 WSe2 Inorganic materials 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910016021 MoTe2 Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 229910052982 molybdenum disulfide Inorganic materials 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical group S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052961 molybdenite Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
- H01L29/66318—Heterojunction transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
The invention provides a bipolar triode based on two-dimensional material/gallium nitride and a preparation method thereof.A first N-type doped III-group nitride layer 2 is extended on a GaN-based substrate 1 as a collector region; depositing a P-type doped two-dimensional material layer 3 with a P-type doping concentration of 10 on the first N-type doped group III nitride layer18cm‑3‑1020cm‑3The P-type doped two-dimensional material layer 3 is a base region; depositing a second N-type doped III-group nitride layer 4 on the P-type doped two-dimensional material layer 3, etching the end part of the second N-type III-group nitride layer 4 to expose the P-type doped two-dimensional material layer and define an emitting region; the valence band of the two-dimensional material and the valence band of the gallium nitride have larger energy difference, so that the heterojunction has higher electron emission efficiency, and the gain of the transistor is favorably improved. Due to the ultra-thin characteristic of the two-dimensional material, the base area can be greatly reduced over time, and the frequency of the transistor is improved.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a bipolar triode based on a two-dimensional material/gallium nitride and a preparation method thereof.
Background
Bipolar Junction Transistors (BJTs) are switching semiconductor devices that utilize both electron and hole carriers. By injecting a small amount of carriers into the base region, a large amount of minority carriers are promoted to be emitted from the emitter region, so that the current amplification effect is generated. Bipolar transistors use a vertical device structure, and current can flow in a direction perpendicular to the entire device plane, rather than conducting current only at the very surface as in a metal-oxide-semiconductor field effect transistor (MOSFET). Therefore, the characteristic is that large current and larger current gain characteristic can be conducted. Bipolar transistors can be widely used in high-power, large-capacity electronic systems (e.g., power regulators for solar power generation, electric vehicles, and radio frequency amplification) as compared to unipolar transistors. And a Heterojunction Bipolar Transistor (HBT) has higher current gain and cut-off frequency and can be widely applied to various radio frequency circuits.
The traditional heterojunction bipolar transistor is based on a silicon/germanium-silicon heterojunction, realizes high gain by utilizing the valence band energy band difference of silicon/germanium-silicon, and achieves the effect of high cut-off frequency by using an ultrathin germanium epitaxial layer. However, the silicon/silicon germanium heterojunction bipolar transistor has a small forbidden band width and a low breakdown voltage, and is difficult to apply to high-power radio frequency devices. Group III nitrides, such as gallium nitride and aluminum gallium nitride, are representative materials for third generation semiconductors, have characteristics of large forbidden bandwidth, high electron mobility, and the like, and are suitable for use in power devices withstanding high voltages. Gallium nitride based field effect transistors have been studied extensively. However, the development of bipolar transistors based on gallium nitride has been in a standstill, due to the difficulty in obtaining P-type doping in gallium nitride.
Disclosure of Invention
In order to solve the problems, the invention provides a preparation method of a bipolar triode based on a two-dimensional material/nitride, which comprises the following steps: comprises the following steps
Providing a gallium nitride substrate 1;
extending a first N-type doped III-group nitride layer 2 on the gallium nitride substrate 1 in an epitaxial manner, and defining the first N-type doped III-group nitride layer 2 as a collector region;
depositing a P-type doped two-dimensional material layer 3 on the first N-type doped group III nitride layer, wherein the P-type doping concentration is 1018cm-3-1020cm-3Defining the P-type doped two-dimensional material layer 3 as a base region;
depositing a second N-type doped III-group nitride layer 4 on the P-type doped two-dimensional material layer 3, etching the end part of the second N-type doped III-group nitride layer 4 to expose the P-type doped two-dimensional material layer, and defining the exposed P-type doped two-dimensional material layer as an emitting region; the doping concentration of the first N-type doped group III nitride layer 2 is less than the doping concentration of the second N-type doped group III nitride layer 4;
and depositing metal on the second N-type group III nitride layer 4 to form an emitter 7, depositing a base 6 on the exposed P-type doped two-dimensional material layer 3, and depositing a collector 5 at the bottom of the first N-type group III nitride layer 2.
Preferably, the gallium nitride-based substrate 1 is a gallium nitride substrate or a gallium nitride epitaxial wafer of a uniform material.
Preferably, the gallium nitride-based substrate 1 is doped in an N type with a doping concentration of 1019cm-3-1021cm-3。
Preferably, the first N-type doped group III nitride layer 2 is weakly N-type doped with a doping concentration of 1015cm-3-1017cm-3。
Preferably, the mode of depositing the P-type doped two-dimensional material layer 3 is a thin film transfer process or chemical vapor deposition.
Preferably, the second N-type doped group III nitride layer 4 is heavily N-type doped with a doping concentration of 1018cm-3-1021cm-3。
Preferably, the mode for depositing the second N-type doped group III nitride layer 4 is chemical vapor deposition or physical vapor deposition; the second N-type doped III-nitride layer 4 is etched by dry etching with etching gasIs Cl2Or BCl3。
Preferably, the depositing the metal includes an annealing process with an annealing time of 300 ℃ to 900 ℃.
Preferably, the first N-type doped group III nitride layer 2 and/or the second N-type doped group III nitride layer 4 is made of a material selected from gallium nitride, aluminum gallium nitride, indium gallium nitride, and aluminum nitride.
Preferably, the P-type doped two-dimensional material layer 3 is selected from tungsten diselenide, molybdenum ditelluride and black phosphorus.
Based on the same inventive concept, the invention also provides a bipolar triode transistor based on the method, the triode structure comprises a gallium nitride substrate 1, a first N-type doped III-group nitride layer 2, a P-type doped two-dimensional material layer 3 and a second N-type doped III-group nitride layer 4 from bottom to top in sequence; the first N-type doped III-nitride layer 2 is a collector region; the P-type doped two-dimensional material layer 3 is a base region; the second N-type doped group III nitride layer 3 is an emitter region.
Preferably, the thickness of the first N-type doped group III nitride layer 2 and/or the second N-type doped group III nitride layer 4 is 100nm to 10 um.
Preferably, the thickness of the P-type two-dimensional material layer 3 is 1nm to 100 nm. Two-dimensional materials are new semiconductor materials emerging in recent years, and have the advantages of doping, flexible and adjustable forbidden band width and thickness. The two-dimensional material can be doped with N-type doping or P-type doping by controlling the growth and doping of the material. The invention combines a P-type doped two-dimensional material and an N-type doped III-group nitride, takes the two-dimensional material as a base region, and takes the nitride as an emitter region and a collector region. Because the combination of the P-type doped two-dimensional material and the N-type doped III-group nitride has huge valence band energy difference, the emission efficiency of electrons emitted from the emitter region combined with the N-type doped III-group nitride into the base region of the P-type doped two-dimensional material can be greatly improved, and the current gain of the transistor can be improved. In addition, the thickness of the film of the two-dimensional material is flexible and controllable, and the film can be as thin as a monoatomic layer. The ultrathin two-dimensional material is used as the base region, so that the carrier transit time of the base region can be greatly reduced, and the cut-off frequency of the transistor is improved. The semiconductor device can be widely applied to the fields of radio frequency power amplification, signal amplification or frequency mixing and the like. The device can be used independently as a discrete device and can also be integrated in a single chip integrated system.
Drawings
Fig. 1 is a schematic structural diagram of a bipolar transistor in embodiment 1 of the present invention.
Fig. 2 is a schematic view of a process for manufacturing a bipolar transistor according to embodiment 1 of the present invention.
GaN-based substrate 1, weakly N-doped GaN layer 2, P-doped WSe2Layer 3, heavily N-doped GaN layer 4, collector 5, base 6, emitter 7
Detailed Description
The following detailed description of the preferred embodiments of the present invention will be given in conjunction with the accompanying drawings so that the features and functions of the present invention can be more easily understood by those skilled in the art, but the present invention is not limited to the following embodiments.
Example 1: the embodiment provides a WSe-based method2Bipolar transistor and method for manufacturing the same
As shown in FIG. 1, the transistor structure is a schematic diagram, the triode structure comprises a GaN-based substrate 1, a first N-type doped III-nitride layer 2 with the thickness of 50nm and a P-type doped WSe with the thickness of 10nm from bottom to top in sequence2Layer 3, a second N-type doped group III nitride layer 4 of thickness 1 um; the first N-type doped III-nitride layer 2 is a collector region; the P-type doped WSe2The layer 3 is a base region, and the second N-type doped III-nitride layer 4 is an emitter region; a collector 5 is deposited at the bottom of the first N-type doped III-nitride layer 4, an emitter 7 is deposited on the second N-type doped III-nitride layer 4, and the P-type doped WSe2 A base 6 is deposited on the layer 3.
As shown in fig. 2, the method for manufacturing the transistor comprises the following steps:
as shown in FIG. 2(a), an initial GaN-based substrate 1 is provided, which is heavily N-doped with a doping concentration of 1020cm-3The substrate may be GaN of uniform material.
As shown in FIG. 2(b), a weak N-type dopant is formed on a heavily N-type doped GaN-based substrate 1 using an epitaxial processThe GaN layer 2 is used as a voltage-withstanding region of the collector region and has a doping concentration of 1015cm-3；
As shown in FIG. 2(c), a layer of P-type doped WSe is deposited on the weakly N-doped GaN2Layer 3 with a doping concentration of 1018cm-3The deposition of the molybdenum disulfide adopts a transfer method;
as shown in FIG. 2(d), in the P-type WSe2Depositing a heavily N-doped GaN layer with a doping concentration of 1020cm-3The deposition is carried out by Chemical Vapor Deposition (CVD). After deposition, photoetching and etching are carried out to define a gallium nitride emission region at the top layer and expose the lower P-type WSe2And (3) a layer. The etching adopts dry etching, and the etching gas is generally Cl2Or BCl3And the like.
As shown in fig. 2(e), metallic nickel is deposited and annealed at 400 c to form the base, collector and emitter.
Compared with molybdenum disulfide or nitride, tungsten diselenide is easier to form P-type doping, and the energy difference between the valence band and the gallium nitride valence band is larger, so that the current gain of the transistor is further improved.
Example 2: the embodiment provides a method based on MoTe2Method for preparing bipolar transistor
Providing an initial GaN-based substrate 1 doped with heavy N-type dopant at a concentration of 1020cm-3The substrate is a gallium nitride layer formed by silicon epitaxy;
a layer of weak N-type doped gallium nitride layer is formed on a heavily N-type doped gallium nitride substrate 1 by using an epitaxial process as a voltage-tolerant region of a collector region, and the doping concentration is 1016cm-3；
Depositing a layer of P-type doped MoTe on weakly N-doped gallium nitride2Layer of doping concentration of 1019cm-3，MoTe2The deposition of the layer adopts a chemical vapor deposition method;
in MoTe2A layer of heavily N-doped GaN is deposited on the substrate, the doping concentration is 1020cm-3The deposition adopts a physical vapor deposition method, and the top layer is defined by photoetching and etching after the depositionGallium nitride emitter region and exposing underlying MoTe2And (3) a layer. The etching adopts dry etching, and the etching gas is Cl2。
Titanium metal is deposited and annealed at 600 c to form the base, collector and emitter.
Example 3: the present embodiment provides another WSe-based solution2Method for preparing bipolar transistor
Providing an initial AlGaN substrate 1, which is heavily doped N-type and has a doping concentration of 1020cm-3；
A layer of weak N-type doped AlGaN layer is formed on a heavily N-type doped gallium nitride substrate 1 by using an epitaxial process as a withstand voltage region of a collector region, and the doping concentration is 1015cm-3；
Depositing a layer of P-doped WSe on the weakly N-doped AlGaN layer2Layer of doping concentration of 1020cm-3，MoS2The deposition of the layer adopts a chemical vapor deposition method;
in WSe2Depositing a heavily N-doped AlGaN layer on the layer with the doping concentration of 1019cm-3The physical vapor deposition method is adopted for deposition. Photoetching and etching are carried out after deposition so as to define an AlGaN layer emission region at the top layer and expose the WSe below2And (3) a layer. The etching adopts dry etching, and the etching gas is BCl3。
A titanium/aluminum/nickel/gold composite metal layer is deposited and annealed at 800 c to form the base, collector and emitter.
Compared with gallium nitride, the AlGaN has larger forbidden band width, so that the AlGaN can bear higher working voltage and is beneficial to forming high-power devices.
The above-mentioned embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, and it should be understood that the above-mentioned embodiments are only examples of the present invention and are not intended to limit the present invention. It is within the spirit and scope of the present invention to change the location and name of the lateral structure by changing the thickness or doping concentration of a region.
Claims (13)
1. A preparation method of a bipolar triode based on a two-dimensional material/gallium nitride is characterized by comprising the following steps:
providing a gallium nitride substrate (1);
extending a first N-type doped III-group nitride layer (2) on the gallium nitride substrate (1) in an epitaxial manner, and defining the first N-type doped III-group nitride layer (2) as a collector region;
depositing a P-doped two-dimensional material layer (3) on the first N-doped group III nitride layer, wherein the P-doping concentration is 1018cm-3-1020cm-3Defining the P-type doped two-dimensional material layer (3) as a base region;
depositing a second N-type doped III-group nitride layer (4) on the P-type doped two-dimensional material layer (3), etching the end part of the second N-type doped III-group nitride layer (4) to expose the P-type doped two-dimensional material layer, and defining the exposed P-type doped two-dimensional material layer as an emitting region; the doping concentration of the first N-type doped group III nitride layer (2) is less than the doping concentration of the second N-type doped group III nitride layer (4);
depositing metal on the second N-type III-nitride layer (4) to form an emitter (7), depositing a base (6) on the exposed P-type doped two-dimensional material layer (3), and depositing a collector (5) at the bottom of the first N-type III-nitride layer (2).
2. The method for manufacturing a bipolar transistor according to claim 1, wherein: the gallium nitride substrate (1) is a gallium nitride substrate or a gallium nitride epitaxial wafer made of uniform materials.
3. The method for manufacturing a bipolar transistor according to claim 1, wherein: the gallium nitride substrate (1) is doped in an N type with a doping concentration of 1019cm-3-1021cm-3。
4. The method for manufacturing a bipolar transistor according to claim 1, wherein: the first N-type doped group IIIThe nitride layer (2) is weakly N-doped with a doping concentration of 1015cm-3-1017cm-3。
5. The method for manufacturing a bipolar transistor according to claim 1, wherein: the mode of depositing the P-type doped two-dimensional material layer (3) is a film transfer process or chemical vapor deposition.
6. The method for manufacturing a bipolar transistor according to claim 1, wherein: the second N-type doped III-nitride layer (4) is heavily N-doped with a doping concentration of 1018cm-3-1021cm-3。
7. The method for manufacturing a bipolar transistor according to claim 1, wherein: the method for depositing the second N-type doped III-group nitride layer (4) is chemical vapor deposition or physical vapor deposition; the second N-type doped III-group nitride layer (4) is etched by a dry etching method with Cl as etching gas2Or BCl3。
8. The method for manufacturing a bipolar transistor according to claim 1, wherein: the metal deposition comprises an annealing process, and the annealing time is 300-900 ℃.
9. The method for manufacturing a bipolar transistor according to claim 1, wherein: the first N-type doped III-group nitride layer (2) and/or the second N-type doped III-group nitride layer (4) are made of materials selected from gallium nitride, aluminum gallium nitride, indium gallium nitride and aluminum nitride.
10. The method for manufacturing a bipolar transistor according to claim 1, wherein: the P-type doped two-dimensional material layer (3) is selected from tungsten diselenide, molybdenum ditelluride and black phosphorus.
11. A transistor prepared by the method of claims 1-10, wherein: the triode structure comprises a gallium nitride-based substrate (1), a first N-type doped III-group nitride layer (2), a P-type doped two-dimensional material layer (3) and a second N-type doped III-group nitride layer (4) from bottom to top in sequence; the first N-type doped III-group nitride layer (2) is a collector region; the P-type doped two-dimensional material layer (3) is a base region; the second N-type doped group III nitride layer (4) is an emitter region.
12. The transistor of claim 11, wherein: the thickness of the first N-type doped III-group nitride layer (2) and/or the second N-type doped III-group nitride layer (4) is 100nm-10 um.
13. The transistor of claim 11, wherein: the thickness of the P-type doped two-dimensional material layer (3) is 1nm-100 nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911365414.3A CN111081543A (en) | 2019-12-26 | 2019-12-26 | Bipolar triode based on two-dimensional material/gallium nitride and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911365414.3A CN111081543A (en) | 2019-12-26 | 2019-12-26 | Bipolar triode based on two-dimensional material/gallium nitride and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111081543A true CN111081543A (en) | 2020-04-28 |
Family
ID=70317969
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911365414.3A Pending CN111081543A (en) | 2019-12-26 | 2019-12-26 | Bipolar triode based on two-dimensional material/gallium nitride and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111081543A (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6313488B1 (en) * | 1999-04-21 | 2001-11-06 | Abb Research Limited | Bipolar transistor having a low doped drift layer of crystalline SiC |
| US20040124435A1 (en) * | 2002-12-27 | 2004-07-01 | General Electric Company | Homoepitaxial gallium-nitride-based electronic devices and method for producing same |
| US20070114518A1 (en) * | 2005-11-22 | 2007-05-24 | Yue-Ming Hsin | GaN HETEROJUNCTION BIPOLAR TRANSISTOR WITH A P-TYPE STRAINED InGaN BASE LAYER AND FABRICATING METHOD THEREOF |
| JP2008016615A (en) * | 2006-07-05 | 2008-01-24 | Matsushita Electric Ind Co Ltd | Bipolar transistor |
| US20080128745A1 (en) * | 2006-12-04 | 2008-06-05 | Mastro Michael A | Group iii-nitride growth on silicon or silicon germanium substrates and method and devices therefor |
| US20080296617A1 (en) * | 2007-05-01 | 2008-12-04 | The Regents Of The University Of California | METHOD USING LOW TEMPERATURE WAFER BONDING TO FABRICATE TRANSISTORS WITH HETEROJUNCTIONS OF Si(Ge) TO III-N MATERIALS |
| US20150357446A1 (en) * | 2014-06-04 | 2015-12-10 | Infineon Technologies Dresden Gmbh | Bipolar transistor structure and a method of manufacturing a bipolar transistor structure |
| CN106298513A (en) * | 2016-08-31 | 2017-01-04 | 厦门市三安光电科技有限公司 | A kind of HBT manufacture method |
| JP2017076715A (en) * | 2015-10-15 | 2017-04-20 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| CN107123581A (en) * | 2017-04-07 | 2017-09-01 | 中山大学 | A kind of device and preparation method based on two-dimensional layer material |
| CN108305834A (en) * | 2018-01-11 | 2018-07-20 | 北京华碳科技有限责任公司 | A kind of preparation method of enhancement type gallium nitride fieldtron |
| CN108365008A (en) * | 2018-01-11 | 2018-08-03 | 北京华碳科技有限责任公司 | Has the preparation method of p-type two-dimensional material grid enhancement type gallium nitride fieldtron |
-
2019
- 2019-12-26 CN CN201911365414.3A patent/CN111081543A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6313488B1 (en) * | 1999-04-21 | 2001-11-06 | Abb Research Limited | Bipolar transistor having a low doped drift layer of crystalline SiC |
| US20040124435A1 (en) * | 2002-12-27 | 2004-07-01 | General Electric Company | Homoepitaxial gallium-nitride-based electronic devices and method for producing same |
| US20070114518A1 (en) * | 2005-11-22 | 2007-05-24 | Yue-Ming Hsin | GaN HETEROJUNCTION BIPOLAR TRANSISTOR WITH A P-TYPE STRAINED InGaN BASE LAYER AND FABRICATING METHOD THEREOF |
| JP2008016615A (en) * | 2006-07-05 | 2008-01-24 | Matsushita Electric Ind Co Ltd | Bipolar transistor |
| US20080128745A1 (en) * | 2006-12-04 | 2008-06-05 | Mastro Michael A | Group iii-nitride growth on silicon or silicon germanium substrates and method and devices therefor |
| US20080296617A1 (en) * | 2007-05-01 | 2008-12-04 | The Regents Of The University Of California | METHOD USING LOW TEMPERATURE WAFER BONDING TO FABRICATE TRANSISTORS WITH HETEROJUNCTIONS OF Si(Ge) TO III-N MATERIALS |
| US20150357446A1 (en) * | 2014-06-04 | 2015-12-10 | Infineon Technologies Dresden Gmbh | Bipolar transistor structure and a method of manufacturing a bipolar transistor structure |
| JP2017076715A (en) * | 2015-10-15 | 2017-04-20 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| CN106298513A (en) * | 2016-08-31 | 2017-01-04 | 厦门市三安光电科技有限公司 | A kind of HBT manufacture method |
| CN107123581A (en) * | 2017-04-07 | 2017-09-01 | 中山大学 | A kind of device and preparation method based on two-dimensional layer material |
| CN108305834A (en) * | 2018-01-11 | 2018-07-20 | 北京华碳科技有限责任公司 | A kind of preparation method of enhancement type gallium nitride fieldtron |
| CN108365008A (en) * | 2018-01-11 | 2018-08-03 | 北京华碳科技有限责任公司 | Has the preparation method of p-type two-dimensional material grid enhancement type gallium nitride fieldtron |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10158009B2 (en) | Method of making a graphene base transistor with reduced collector area | |
| US20010026986A1 (en) | Process for forming a silicon-germanium base of a heterojunction bipolar transistor | |
| JPH0677245A (en) | Bipolar transistor and its manufacture | |
| US20190067460A1 (en) | Semiconductor device | |
| CN109873034B (en) | Normally-off HEMT power device for depositing polycrystalline AlN and preparation method thereof | |
| KR20160100918A (en) | HEMT Made from a Heterojunction | |
| KR20210065843A (en) | Si-MOSFET With Wide Bandgap III-V Compound Semiconductor Drain And Method Of Manufacturing The Same | |
| JP2008016615A (en) | Bipolar transistor | |
| US6410396B1 (en) | Silicon carbide: germanium (SiC:Ge) heterojunction bipolar transistor; a new semiconductor transistor for high-speed, high-power applications | |
| CN111682064B (en) | High-performance MIS gate enhanced GaN-based high electron mobility transistor and preparation method thereof | |
| JP3515944B2 (en) | Hetero bipolar transistor | |
| US6573539B2 (en) | Heterojunction bipolar transistor with silicon-germanium base | |
| CN115775730B (en) | GaN Schottky diode with quasi-vertical structure and preparation method thereof | |
| CN108831932B (en) | Transverse MIS-Schottky mixed anode diode of gallium nitride | |
| US20060284282A1 (en) | Heterjunction bipolar transistor with tunnelling mis emitter junction | |
| CN111081543A (en) | Bipolar triode based on two-dimensional material/gallium nitride and preparation method thereof | |
| KR102074320B1 (en) | Hetero junction bipolar transistor | |
| US11195940B2 (en) | High-voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor and preparation method thereof | |
| JP2007042936A (en) | Group iii-v compound semiconductor epitaxial wafer | |
| CN210110780U (en) | PNP type Schottky collector region AlGaN/GaN HBT device | |
| KR100347520B1 (en) | A Heterojunction Bipolar Transistor and, A Method Manufacturing the HBT | |
| JP4158683B2 (en) | Epitaxial wafer for heterojunction bipolar transistor | |
| JP2017195217A (en) | Heterojunction bipolar transistor and manufacturing method thereof | |
| KR100839786B1 (en) | SiGe semiconductor device structure and its manufacture method | |
| Chu-Kung et al. | Process and performance improvements to type-II GaAsSb/InP DHBTs |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20230329 Address after: No. 1088, Xueyuan Avenue, Taoyuan Street, Nanshan District, Shenzhen City, Guangdong Province Applicant after: Southern University of Science and Technology Address before: Taizhou building, No. 1088, Xueyuan Avenue, Xili University Town, Nanshan District, Shenzhen City, Guangdong Province Applicant before: SHENZHEN THIRD GENERATION SEMICONDUCTOR Research Institute |
|
| AD01 | Patent right deemed abandoned | ||
| AD01 | Patent right deemed abandoned |
Effective date of abandoning: 20240319 |