JP2007026185A - Function-processing electronic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce mounted hardware by mounting only the number of DMAs, corresponding to the transmission speed of a bus or memory, and realizing necessary function-processing with hardware. <P>SOLUTION: A plurality of DMACs are connected to a plurality of function-processing blocks through a switching circuit, and the connection between each DMAC and each function-processing block can be changed with a switch. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electronic circuit having a DMA controller (hereinafter referred to as DMAC), and more particularly to an electronic circuit realized using a plurality of function processing hardware and a DMAC.

  In an embedded system, a hardware function processing block that implements specific functions in addition to the CPU, memory control circuit, and interface circuit is installed inside the system, thereby reducing software processing and hardware processing. It is possible to speed up. In addition, by installing hardware functional processing blocks, it becomes possible to perform processing resource load distribution by parallelizing processing and pipelining.

  The function processing block of hardware generally implements a function by performing specific signal processing provided for data stored in a memory and holding the result data in the memory again. In other words, the original data in the memory is taken in by the DMAC, the data is processed by the circuit in the function processing block, and the result data after processing is written back to the memory by the DMAC. It is realized with. For example, the functional processing block (101) for performing JEPG decoding shown in FIG. 1 is composed of two sets of DMAC (102, 103) and JEPG decoding block (104). The read DMAC (102) that reads data from one memory reads the encoded JPEG data stored in the memory (105), and inputs the read data to the JPEG decoding circuit (104). The JPEG decoding circuit (104) decodes the input JPEG data and outputs the resulting decoded data. The decoded data output by the JPEG decoding circuit (104) is input to the Write DMAC (103) for writing the data to the other memory, and the decoded data that is the result data is transferred to the memory (105) by the DMAC. The JPEG decoding function is realized by writing back to the memory.

  In many systems, in order to realize a plurality of functions, a plurality of types of function processing blocks are mounted by hardware to realize high-speed processing of functions and parallel processing. Figure 2 shows an example of the system. The system includes a CPU (201) that controls the entire system, a memory device control circuit (202) that controls a memory device such as a main memory, an interface circuit (203) that controls an external interface such as a network, and a plurality of It has function processing blocks (204 to 209), each function processing block has a DMAC for reading and writing data from the memory device and a function processing circuit for realizing a predetermined function, and JPEG encoding Functional processing such as decryption and encryption processing is realized as a block. For example, when the system realizes the function A processing, the function processing block reads the original data from the memory by activating the DMAC of the function processing block A (204) and the function processing circuit A from the CPU (201), and the function processing This is realized by processing in the circuit A and writing the result data in the memory by the DMAC. By performing this setting for each function processing block from the CPU (201), the system can execute each function process in parallel. By implementing the processing realized by the system in hardware as a function processing block in this way, it is possible to realize high-speed processing by hardware. When a plurality of JPEG encoding processes are executed in parallel in the system, a plurality of function processing blocks for implementing the same function processing are configured by mounting JPEG encoding processing circuits on the function processing circuits A and B, respectively. Also, a functional processing block that performs processing to decode JPEG data encoded for each rectangle as a continuous image and a functional processing block that performs processing to decode JPEG data encoded as one continuous image as an image for each rectangle. In the system that requires the same JPEG decoding processing circuit for each of the function processing circuits C and D, the reading DMAC of one function processing block is fetched for each rectangle, and the writing DMAC is continuously imaged The two functional processing systems are realized by adopting a configuration in which the data is written in the memory, the reading DMAC of the other functional processing block is taken in as a continuous image, and the writing DMAC is written in the memory as a rectangular image.

  As described above, functional processing that requires high-speed processing in the system is implemented by hardware as functional processing blocks necessary for the system, and the performance required by the system is realized.

Moreover, as a prior art example, patent document 1 and patent document 2 can be mention | raise | lifted, for example.
JP 05-274249 A JP 09-223103 A

  However, while each function processing block transfers data from memory, the maximum transfer speed of the connected bus and memory is finite, so even if multiple function processing blocks are installed and DMAC is built in, Since the maximum processing speed is limited by the bus transfer speed and the memory transfer speed, an excessive DMAC that cannot operate simultaneously as the entire system is built in. Also, a functional processing block that performs processing to decode JPEG data encoded for each rectangle as a continuous image and a functional processing that performs processing to decode JPEG data encoded as one continuous image as an image for each rectangle. In a system that has one block at a time, for example, if you want to operate in parallel two processes for decoding JPEG data encoded for each rectangle as a continuous image, it is necessary to implement two such equal processing blocks If only one is implemented, functional processing is performed even if the JPEG decoding circuit of the functional processing block that performs processing to decode JPEG data encoded as a continuous image as an image for each block is unused. Since the function is limited as a block, it cannot be used as a resource, and the former two function processing blocks are implemented. If the hardware scale is increased and only one process is performed, hardware resources cannot be used effectively.

  The present invention has been made in view of the above problems, and the first object of the present invention is to implement only the number of DMAs corresponding to the transfer speed of the bus or memory, and realize necessary function processing by hardware. By doing so, the hardware to be mounted is reduced. In addition, the second object of the present invention is to make it possible to dynamically switch the combination of the DMA mechanism and the function processing block so that the resource of the function processing block can be used as much as possible. The hardware to be realized and implemented will be reduced.

At least one CPU,
Multiple function processing blocks;
Multiple DMA controllers and memory device control circuits,
It is composed of the functional processing block and a switch circuit which can be arbitrarily combined with the DMA controller,
One of the DMA controllers is connected to a memory control circuit, and the other is connected to an arbitrary function processing block via the switch circuit.

  The switch circuit has a switch switching designation input signal or a switch switching designation register, and has means for switching a combination of the function processing block and the DMA controller according to the designation.

  From the above, it is not necessary to have a DMAC for each function processing block by sharing and switching multiple DMACs in multiple function processing blocks, and the bandwidth of the connected bus and the access bandwidth to the memory device By implementing a considerable DMAC and realizing a configuration that is not excessive or deficient in the system, it is possible to reduce hardware resources without system performance degradation.

  Conversely, by sharing multiple functional processing blocks with multiple DMACs and using them by switching, multiple processing systems can be realized with the configuration of functional processing blocks and DMACs. The number of implementations can be reduced according to the possibility of parallel processing, and hardware resources can be reduced without deterioration in performance for the same reason as described above.

  As an embodiment of the present invention, a system shown in FIG. 4 will be described as an example. This system includes a CPU (303), a memory control circuit (302), a memory device (301) connected thereto, two sets of ReadDMAC (401,402), two sets of WriteDMAC (403,404), and a system to which these devices are connected The bus (306) includes six function processing blocks (312 to 317) and a data transfer switch (405) for connecting each DMAC and the function processing block.

  The function processing circuit included in the function processing block (312 to 317) is a circuit that performs arbitrary data signal processing such as JPEG encoding and decoding, performs signal processing provided for input data, and outputs result data. Output. Data subjected to signal processing in the function processing circuit is input from the data transfer connection switch (405) via the data input IF, and signal processing result data is output to the data transfer connection switch (405) via the data output IF. Is done.

  ReadDMAC (401, 402) has a DMAC setting register that sets the DMAC operation, a register that specifies the memory address of the data to be read, a register that specifies the data transfer amount, a rectangular transfer width register, a rectangular transfer address offset register, and a DMAC transfer It consists of setting registers that perform DMAC transfer, such as registers to be activated. The contents of the setting register are arbitrary. The ReadDMA control circuit issues a data read transfer request to the memory via the system bus (306) when instructed to start DMAC transfer according to the settings of the address, transfer amount, etc. specified in the setting register group. Read data on device (301). The read data is output to the data transfer switch (405) via the data output IF. In addition, by specifying the rectangular transfer width register and the rectangular transfer address offset register, the rectangular transfer in the memory space is performed, the rectangular transfer width is set arbitrarily, and the rectangular transfer address offset register value is set to 0, continuous transfer is possible It is.

  On the other hand, WriteDMAC (403, 404) has a DMAC setting register that sets the DMAC operation, such as a register that specifies the memory address of the data to be written, a rectangular transfer width register, a rectangular transfer address offset register, a register that starts DMAC transfer, etc. It consists of a set register group that performs transfer. The contents of the setting register are arbitrary. WriteDMAC (403, 404) receives data from the data transfer switch (405) via the data input IF. The WriteDMA control circuit is instructed to start DMAC transfer according to the setting of the address specified in the setting register group, and when data is input via the data input IF, it is sent to the memory via the system bus (306). A data write transfer request is issued and data is written on the memory device (301). In addition, by specifying the rectangular transfer width register and the rectangular transfer address offset register, the rectangular transfer in the memory space is performed, the rectangular transfer width is set arbitrarily, and the rectangular transfer address offset register value is set to 0, continuous transfer is possible It is.

  Data from the data output IF of ReadDMAC (401, 402) is connected to one data input IF of the function processing blocks (312 to 317) by the data read switch in the data transfer connection switch (405), and the function processing block The data output from the data output IF (312 to 317) is connected to the data input IF of WriteDMAC (403, 404) by the data write switch in the data transfer connection switch (405). The data transfer protocol for connecting ReadDMAC (401, 402) and the function processing blocks (312 to 317) and the data transfer protocol for connecting the function processing block (312 to 317) and WriteDMAC (403, 404) are arbitrary. FIG. 5 shows a signal waveform example of this data transfer protocol. In this embodiment, the data input IF issues a READY signal in the cycle immediately before the receivable cycle, and the data output IF issues a DATA_VALID signal and a DATA signal in the next cycle after the READY signal is issued. The DATA_END signal is issued simultaneously when the final data is transferred. The signal waveform example in FIG. 5 is an example of 8-beat data transfer (8 data transfers). When a READY signal is issued from the data input interface in cycle 1, the data output IF outputs a DATA_VALID signal and valid DATA from cycle 2. In cycle 3, the data input IF cancels the READY signal because it cannot take in the data of the next cycle. On the other hand, since the READY signal of cycle 2 is issued, the data output IF transfers valid data. In cycle 4, the valid data transfer is not performed in response to the release of the READY signal in cycle 3, and the valid transfer of the third beat is performed in cycle 5 because the READY signal is issued again in cycle 4. In this data transfer protocol, the signal to the next data input IF after the READY signal is issued is Don't Care. This is the last data transfer cycle of the eighth beat in cycle 12, and the DATA_END signal is transferred in the same cycle as the last data transfer, and the data transfer is completed.

  As shown in FIG. 6, the data transfer connection switch (405) includes a data read switch (601) and a data write switch (602), and a read data transfer destination designation signal for designating the data transfer destination of each ReadDMAC (401, 402). (603) and a read data transfer source specifying signal (604) for specifying the data transfer source of each function processing block (312 to 317), and a write data transfer source specifying signal for specifying the data transfer source of each WriteDMAC (403, 404) ( 606) and a write data transfer destination designation signal (605) for designating the result data transfer destination of each function processing block (312 to 317). Each transfer designation signal (603 to 606) is set by a register (not shown) in the data transfer connection switch.

  FIG. 7 shows a configuration diagram of the data read switch (601). Corresponding to each ReadDMAC (401, 402), the data transfer destination changeover switch (701) for the ReadDMAC output signal, the input changeover MUX (702) for the ReadDMAC input signal, and the connected function processing blocks (312 to 317) A transfer source switching MUX (703) for the output signal and an input switching switch (704) for the input signal from the function processing block are configured. Each switch and MUX switching signal includes a read data transfer destination designation signal (603) and a read data transfer source designation signal (604). A read data transfer destination designation signal (603) is a signal for selecting a function processing block (312 to 317) that is a data transfer destination of ReadDMAC. In the present embodiment, it is realized by a 3-bit signal as a signal for selecting six function processing blocks. The read data transfer source selection signal (604) is a signal for designating ReadDMAC (401, 402) as a transfer source on the function processing block (312 to 317) side. In this embodiment, it is realized by a 1-bit signal as a signal for selecting two ReadDMACs.

  Data transfer destination changeover switch (701), input changeover MUX (702), and read data transfer destination designation signal (603) are implemented as many as the number of connected ReadDMACs. In this example, it corresponds to ReadDMAC-1 / 2 (401, 402) Two sets are included. Transfer source change MUX (703), input changeover switch (704), and read data transfer source selection signal (604) are implemented by the number of function processing blocks to be connected. In this embodiment, function processing block-A / B / C Six sets are included corresponding to / D / E / F (312 to 317).

  The operation of the read data switch (601) is described below. The data transfer destination changeover switch (701) receives the output signal from the connected ReadDMAC and the read data transfer destination designation signal (603) as inputs, and has outputs for the number of function processing blocks connected as output. It has 6 output signal sets. The data transfer changeover switch (701) connects the output signal and the input signal to the designated function processing block according to the signal value of the read data transfer destination designation signal (603). The output signal to the function processing block that is not specified by the read data transfer destination specifying signal (603) is output as an invalid signal. Specifically, a signal obtained by canceling the DATA_VALID signal of the data transfer signal is output. By the above mechanism, the output signal to the function processing block selected by the read data transfer destination designation signal (603) is output as it is from the data output IF of ReadDMAC by the switch operation, and the function processing block that is out of selection The output signal to becomes invalid data, that is, a non-transfer state. Data output for each function processing block of the data transfer destination changeover switch (701) is connected to the transfer source changeover MUX (703). The transfer source switching MUX (703) is the input of the output signal (two sets in this embodiment) and the read data transfer source selection signal (604) of the data transfer switch (701) corresponding to each ReadDMAC, and the data of the function processing block Has a data output connected to the input IF. The data output transfer source change-over MUX (703) determines the ReadDMAC of the transfer source based on the signal value of the read data transfer source designation signal (604) and outputs the input signal from the corresponding ReadDMAC as an output signal to the function processing block . By the above mechanism, the output data of the data transfer changeover switch (701) corresponding to each ReadDMAC becomes the input of the transfer source changeover MUX (703), and the ReadDMAC designated as the transfer source by the read data transfer source selection signal (604) Is input as an input signal of the function processing block. In contrast, the input changeover switch (704) and input changeover MUX (702) are switch mechanisms for the READY signal transmitted from the function processing block to the ReadDMAC, and the READY signal from the function processing block is transmitted from the input changeover switch (704). ReadDMAC is selected by the value of the read data transfer source selection signal (604), the READY signal for the selected ReadDMAC is transmitted as it is from the function processing block, and the READY signal for ReadDMAC that has been selected is released Transferred in state. The input switch MUX (702) receives the output of the input switch (704) of each function processing block as input, selects the READY signal issue source based on the signal value of the read data transfer destination designation signal (603), and sends it to ReadDMAC READY signal is transmitted.

  FIG. 3 shows a configuration diagram of the data write switch (602). Corresponding to each WriteDMAC (403, 404), the data transfer source changeover switch (802) for the input signal of WriteDMAC, the output changeover MUX (801) for the output signal of WriteDMAC, and each function processing block (312 to 317) connected A transfer destination switching MUX (804) for the output signal and an output switching switch (803) for the input signal from the function processing block are configured. A write data transfer destination designation signal (606) and a write data transfer source designation signal (605) are provided as switching signals for each switch and MUX. The write data transfer source designation signal (605) is a signal for selecting a function processing block (312 to 317) that is a data transfer source of WriteDMAC. In the present embodiment, it is realized by a 3-bit signal as a signal for selecting six function processing blocks. The write data transfer destination selection signal (606) is a signal that designates WriteDMAC (403, 404) as a transfer source on the function processing block (312 to 317) side. In this embodiment, it is realized by a 1-bit signal as a signal for selecting two Write DMACs.

  Data transfer source changeover switch (802), output changeover MUX (801), and write data transfer source designation signal (605) are implemented for the number of connected WriteDMACs, and this example supports WriteDMAC-1 / 2 (403, 404) Two sets are included. The transfer destination switching MUX (804), output changeover switch (803), and write data transfer destination selection signal (606) are implemented by the number of function processing blocks to be connected. In this embodiment, the function processing block-A / B / C 6 sets are included corresponding to / D / E / F (312 to 317).

  The operation of the write data switch (602) is described below. The data transfer destination changeover switch (803) receives the output signal from the function processing block to be connected and the write data transfer destination designation signal (606) as inputs, and has outputs for the number of WriteDMACs connected as outputs. It has two output signal sets. The data transfer destination changeover switch (803) connects the output signal and the input signal to the designated WriteDMAC according to the signal value of the write data transfer destination designation signal (606). An output signal to WriteDMAC that is not designated by the write data transfer destination designation signal (606) is output as an invalid signal. Specifically, a signal obtained by canceling the DATA_VALID signal of the data transfer signal is output. With the above mechanism, the output signal for WriteDMAC selected by the write data transfer destination designation signal (606) is output as it is from the data output IF of the function processing block by the switch operation, and is sent to the WriteDMAC that is out of selection. The output signal becomes invalid data, that is, a non-transfer state. The data output for each write of the data transfer destination changeover switch (803) is connected to the transfer source changeover MUX (801). The transfer source switching MUX (801) is an input of the output signals (six sets in this embodiment) of the data transfer source changeover switch (803) corresponding to each function processing block, the input of the write data transfer source selection signal (605), and the WriteDMAC It has a data output connected to the data input IF. The data output transfer source switching MUX (801) discriminates the function processing block of the transfer source from the signal value of the write data transfer source designation signal (605) and outputs the input signal from the corresponding function processing block as an output signal to WriteDMAC To do. With the above mechanism, the output data of the data transfer changeover switch (803) corresponding to each function processing block becomes the input of the transfer source changeover MUX (801) and is designated as the transfer source by the write data transfer source selection signal (605). An input signal from the function processing block is output as an input signal of WriteDMAC. On the other hand, the output changeover switch (803) and the output changeover MUX (801) are switch mechanisms for the READY signal transmitted from the WriteDMAC to the function processing block, and the function for transmitting the READY signal from the WriteDMAC from the output changeover switch (802). The processing block is selected by the value of the write data transfer source selection signal (605), the READY signal for the selected function processing block is transmitted as it is from the WriteDMAC, and the READY signal for the selected function processing block is released. It is transferred in the state. The output switch MUX (804) receives the output of the output switch (802) of each WriteDMAC, selects the issuer of the READY signal according to the signal value of the write data transfer source designation signal (605), and sends it to the function processing block READY signal is transmitted.

  With the above switch configuration, the connection between the ReadDMAC (401, 402), WriteDMAC (403, 404) and the data of each function processing block (312 to 317) is established by the switch switching designation signal (603 to 606), and the data in each combination Transfer is possible.

  The operation and control of the DMAC (401 to 404) and the function processing block (312 to 317) will be described below. In this embodiment, the functional processing circuit of the functional processing block is the functional processing block-A / B (312,313) is a JPEG encoding circuit, the functional processing block-C / D (314,315) is a JPEG decoding circuit, and the functional processing block-E. Is a resolution conversion circuit, and function processing block-F is a color space conversion circuit. When JPEG encoding processing of continuous images is performed, the hardware resource usage status of each DMAC (401 to 404) and function processing block (312 to 317) is confirmed by software, and ReadDMAC, WriteDMAC, and JPEG encoding block Reserve resources. Here, explanation is made assuming that resources of ReadDMAC-1, WriteDMAC-1, and function processing block-A have been secured. When the software secures the resource, it issues access to the ReadDMAC-1 register, sets the start address and data transfer size of the original data to be encoded, and sets the offset register because it is a continuous data DMA transfer. Set to 0, then issue access to the WriteDMAC-1 register, and set the start address on the memory of the encoded data and the rectangle related registers. At the same time, as a setting of the JPEG encoding circuit, a parameter related to JPEG encoding included in the function processing block-A is set, and an operation permission of the function processing block is issued.

  The software then establishes a switch between the DMAC and the function processing block. To establish the connection between ReadDMAC-1 and function processing block-A, the register of the data transfer connection switch (405) is accessed and the read data transfer destination designation signal (603) and the read data transfer source designation signal (604) Setting is performed, and a write data transfer source designation signal (605) and a write data transfer destination designation signal (606) are set in order to establish a connection between WriteDMAC-1 and function processing block-A.

  After all the above settings are made, it is possible to perform JPEG encoding processing using DMA transfer by accessing the DMAC activation registers of ReadDMAC-1 and WriteDMAC-1.

  At the same time, if it is necessary to perform the same processing on different data, ReadDMAC-2, WriteDMAC-2, and function processing block-B are assigned and set, so that the same processing can be performed in parallel on two dedicated processing hardware. Can be done. In addition, when performing resolution conversion in parallel with the previous JPEG encoding process, assigning Read-DMAC-2, WriteDMAC-2, and function processing block-E and setting the JPEG encoding process and resolution conversion process Processing can be performed in parallel.

  In addition, when performing color space conversion on continuous images in memory and when performing color space conversion on images held in memory in rectangular units, any DMAC and function processing block-F are used as resources. By securing and changing the operation mode of ReadDMAC between continuous image and rectangular image, the same hardware can be used and desired color space conversion can be performed in each mode.

It is a simple block diagram of a general JPEG decoding processing block This is a system configuration example with multi-function processing hardware It is a circuit simplified block diagram of a write data transfer connection switch. It is a block block diagram of the system in a present Example. It is a signal waveform diagram which describes a data transfer protocol. It is a circuit simplified block diagram of a data transfer connection switch. It is a circuit simplified block diagram of a read data transfer connection switch.

Explanation of symbols

101 JPEG decoding block
102, 401, 402 ReadDMAC
103, 403, 404 WriteDMAC
104 JPEG decoding circuit
105,301 memory devices
201,303 CPU
202,302 Memory control circuit
203 Interface circuit
204 to 209: DMAC-included function processing block
306 System bus
405 Data transfer connection switch
312 to 317 Function processing block
601 Read data transfer connection switch
602 Write data transfer connection switch
603 Read data transfer destination selection signal
604 Read data transfer source selection signal
605 Write data transfer source selection signal
606 Write data transfer destination selection signal
701 Transfer destination selector switch
702 Input switching MUX
703 Transfer source switching MUX
704 Input selector switch
801 Output switching MUX
802 Transfer source selector switch
803 Output selector switch
804 Transfer destination switching MUX

Claims (11)

At least one CPU,
Multiple function processing blocks;
Multiple DMA controllers and memory device control circuits,
It is composed of the functional processing block and a switch circuit which can be arbitrarily combined with the DMA controller,
One of the DMA controllers is connected to a memory control circuit, and the other is connected to an arbitrary functional processing block via the switch circuit.   2. The electronic circuit according to claim 1, wherein the number of function processing blocks is larger than the number of the DMA controllers.   3. The electronic circuit according to claim 1, wherein the DMA controller has continuous address space DMA transfer means, rectangular address space DMA transfer means, continuous address space DMA, and rectangular address space DMA switching means.   3. The switch circuit according to claim 1, wherein the switch circuit has a switch switching designation input signal, and has means for switching a combination of the function processing block and the DMA controller in accordance with the switch switching designation input signal. Electronic circuit. 3. The switch circuit according to claim 1, wherein the switch circuit has a switch switching designation register, and has means for switching a combination of the function processing block and the DMA controller in accordance with the switch switching designation register setting. Electronic circuit.
At least one CPU,
Multiple function processing blocks;
Multiple write-only DMA controllers, multiple read-only DMA controllers, memory device control circuits,
The function processing block and the write-only DMA controller can be arbitrarily combined with a write switch circuit, and the function process block and the read-only DMA controller can be arbitrarily combined with a read switch circuit,
One of the write DMA controllers is connected to a memory control circuit, and the other can be connected to an arbitrary function processing block via the write switch circuit.
One of the read DMA controllers is connected to a memory control circuit, and the other can be connected to an arbitrary functional processing block via the read switch circuit.   The electronic circuit according to claim 6, wherein the number of the functional processing blocks is larger than either or both of the number of the write DMA controllers and the number of the read DMA controllers.   8. The electronic device according to claim 6, wherein the write DMA controller comprises continuous address space write DMA transfer means, rectangular address space write DMA transfer means, continuous address space DMA, and rectangular address space DMA switching means. circuit.   8. The electronic device according to claim 6, wherein the read DMA controller comprises continuous address space read DMA transfer means, rectangular address space read DMA transfer means, continuous address space DMA, and rectangular address space DMA switching means. circuit. The write switch circuit has a write switch switching designation input signal, and has means for switching the combination of the functional processing block and the write DMA controller according to the write switch switching designation input signal,
The read switch circuit has a read switch switching designation input signal, and has means for switching a combination of the functional processing block and the read DMA controller in accordance with the read switch switching designation input signal. The electronic circuit described in 6 or 7. The write switch circuit has a write switch switching designation register, and has means for switching a combination of the functional processing block and the write DMA controller according to the write switch switching designation register setting,
7. The read switch circuit has a read switch switching designation register, and has means for switching a combination of the functional processing block and the read DMA controller in accordance with the setting of the read switch switching designation register. Alternatively, the electronic circuit described in 7.

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