JP2009193282A - Data processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processing apparatus capable of preventing reduction of speed, with a simple circuit configuration. <P>SOLUTION: Before functional modules start transferring of data to an internal bus 101, a functional module on a writing side directly sends a process information representing a process content to a functional module on a succeeding stage. The internal bus 101 determines a transfer destination path by a direct command issued by WDMA of module before starting of data transfer, to automatically trigger RDMA (Read DMA) for direct data transfer. A first module 102 on the writing side can transmit data as if the data is transferred to a large capacity memory, and a sixth module 107 which is a transfer destination can receive data as if the data is read out of the large capacity memory. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data processing apparatus that performs data transfer between functional modules.

  The image processing module has a plurality of image processing units, compression units, decompression units, and external large-capacity memory controllers, and temporarily stores part or all of the image processing results by the image processing unit in the large-capacity memory. However, post-processing following the image processing unit is performed. However, when accesses from a plurality of master modules to a large-capacity memory are concentrated, the bandwidth to the external memory is compressed and the speed is reduced.

  Therefore, there is a technology to transfer data directly to each module. However, a master and a target are prepared for each module, and it is necessary to have two types of controllers for data transfer in one module. However, there is a problem that the circuit becomes complicated.

  Patent Document 1 discloses a technique for transferring data between a functional module and a large-capacity memory using DMA.

JP 2002-328881 A

  An object of the present invention is to provide a data processing apparatus that can suppress a decrease in speed with a simple circuit configuration.

  The present invention has a plurality of functional modules, and before each functional module starts to transfer data to the internal bus, the functional module on the writing side directly displays processing information for the subsequent functional module. It is a data processing device characterized by sending.

  In the invention, it is preferable that the internal bus determines a transfer destination path by a direct command issued by each functional module before starting the transfer.

  According to the present invention, the transfer destination path determined by the internal bus is formed by a bus matrix, and each switch of the bus matrix is switched by rewriting the port address to determine the transfer destination path.

  Further, the present invention is characterized in that after the internal bus determines the transfer destination path, data is transferred from the writing function module to the subsequent function module in a minimum unit.

  In the invention, it is preferable that each functional module has a unique address.

The present invention also includes a large-capacity memory having a storage capacity greater than a predetermined capacity,
When transferring data from the writing-side functional module to the subsequent-stage functional module via the large-capacity memory, the command sent by the writing-side functional module sent to the large-capacity memory is sent before starting the data transfer. It is characterized in that a subsequent functional module is determined by analysis.

  According to the present invention, before starting to transfer data to the internal bus, the functional module on the writing side directly sends processing information indicating the processing contents to the subsequent functional module. It is not necessary to connect many wires, and it is possible to suppress the speed reduction with a simple circuit configuration.

  According to the present invention, the internal bus determines a transfer destination path by a direct command issued by each functional module before starting the transfer.

  As a result, a transfer destination path can be secured for the internal bus before direct transfer.

  According to the present invention, the transfer destination path determined by the internal bus is formed by a bus matrix, and each switch of the bus matrix is switched by rewriting the port address to determine the transfer destination path. Data can be transferred when the functional module on the writing side issues a command to the port address of the internal bus.

  Hereinafter, the operation of the internal bus of the data processing apparatus according to the embodiment of the present invention will be described with reference to FIGS. The data processing apparatus according to the present invention targets image data, and reads and writes image data read by a scanner to a storage device, transfers the image data to an image processing module, and processes the processed image data. It is suitably used for transfer to a processing module.

  The data processing apparatus of the present invention has a plurality of functional modules, and each functional module reads and writes data by an DMA (Direct Memory Access) system via an internal bus without using a control unit such as a CPU. (Write).

  FIG. 1 is a block diagram showing the configuration of the data processing apparatus of the present invention. The data processing apparatus includes a first module 102 to a seventh module 108 which are a plurality of functional modules, and these modules are connected by an internal bus 101 so that data can be transmitted and received. The local bus controller 109 is a controller for performing data communication with an external data processing device or the like. The data processing apparatus reads / writes data from / to the external large capacity memory 113 via the SDRAM controller 110.

  In the data processing apparatus of the present invention, before each functional module starts to transfer data to the internal bus 101, the functional module on the writing side directly sends processing information indicating the processing content to the subsequent functional module. .

  Here, the data flow will be described with the functional module on the writing side as the first module 102 and the transfer destination functional module at the subsequent stage as the sixth module 107.

FIG. 2 is a diagram showing a bus data flow in the data processing apparatus.
In the present invention, the WDMA (Write DMA) of the first module 102 is a direct command including the processing size and processing contents of data to be transferred in advance to the sixth module 107 as the transfer destination before starting the data transfer. Is issued.

  The sixth module 107 that has received the direct command analyzes the command and takes an action of reading data. Thereafter, the data is directly transferred without going through the large-capacity high-speed memory.

  At this time, the internal bus 101 determines the transfer destination path by a direct command issued by the module WDMA before the start of data transfer, and automatically starts RDMA (Read DMA), so that only memory transfer is performed. By such an operation, data can be directly transferred.

  In this way, the first module 102 on the preceding write side can transmit data as if it were transferring data to the large-capacity memory, and the sixth module 107 on the subsequent transfer destination is as large as possible. Since the data can be received as if the data is being read from the capacity memory, it is not necessary to connect each functional module with many wirings, and the speed reduction can be suppressed with a simple circuit configuration.

  In the general target access for the present invention, the system is configured such that the transfer size is notified by a predetermined amount from the writing module in the previous stage. Therefore, a circuit for such transfer is newly added. It is necessary to design to. Furthermore, when processing image data, it is necessary to set the main scanning and sub-scanning sizes separately, which increases the complexity and the circuit scale.

  Next, a case where each module reads data from the external large-capacity memory 113 will be described.

  First, the CPU (not shown) sets the start address of the large capacity memory 113 and the continuous data capacity in the register 112 of the module, and starts the DMA_START command. As a result, the start address and data capacity (basic burst) of the large capacity memory 113 can be issued to the internal bus 101 via the RDMA controller, and the RDMA_CVLD command can be issued to read the data in the smallest unit.

  In order to read the total size desired by each DMA, it is possible to read the minimum unit of data by repeatedly requesting all register setting capacities.

  Next, a case where each module writes data to the external large-capacity memory 113 will be described.

  First, the CPU sets the start address of the large-capacity memory 113 and the continuous data capacity in the register 112, and starts the DMA_START command. As a result, the start address of the large-capacity memory 113 and the data capacity (basic burst), the WDMA_CVLD command, and the write data itself, WDMA_CWD, are issued to the internal bus 101 via the WDMA controller, and the data can be written in the smallest unit. it can.

  In order to write the total size desired by each DMA, writing can be performed by repeatedly requesting data writing in the minimum unit for all register setting capacities.

  The present invention makes the best use of the features of the DMA transfer described above in order to realize a simple circuit configuration when transferring data directly without using a memory.

  That is, the WDMA that directly transfers data secures a transfer destination path for the internal bus 101 and automatically activates the transfer destination size capacity and the DMA_START command before direct transfer.

  For this purpose, the RDMA accepts the size capacity by the direct command (RDMA_DCOM), and when the direct command is received, sets the received size in its own register, and activates its own DMA.

  The operation after DMA activation is the same as the memory access except that RDMA_CVLD is not issued.

RDMA uses RDMA_DVLD command from FIFO (First in First out) 111 and
Since the data is received using the RDMA_DRCV command and the Request-Acknowledge handshake, the operation is as if the data is being read from the memory.

  The WDMA notifies the transfer destination path reservation and the size capacity set in the other party by a direct command before data transfer.

  Once the transfer destination path is secured, the operation is as if the WDMA is writing data to the memory. Regardless of memory access or direct access, the design is unified and simplified if each WDMA issues a direct command each time the DMA is activated.

  When the internal bus 101 receives a direct command from the WDMA, the internal bus 101 determines a transfer destination path for reading the transfer destination address included in the direct command.

  Here, if the transfer destination address is a memory access, the transfer destination path is set to access the memory and the subsequent size information is unnecessary and discarded.

  If the transfer destination address is a port access address, the transfer destination route is determined, and subsequent size information is notified to the transfer destination DMA using a direct command (RDMA_DCOM).

  The end of the data transfer ends when data for the size information issued before the start of the data transfer is transmitted, but there are cases where it is desired to end the data transfer in a state where the data size is less than the issued size. In such a case, the preceding module issues an end command to notify the subsequent transfer destination module that the transfer data size has been changed, so that the DMA can be promptly terminated. The subsequent transfer destination module may respond to the DMA size change when it receives the end command.

  FIG. 3 is a diagram showing an example of commands used by the data processing apparatus of the present invention. The command includes Access Address 1 for setting a transfer destination address at the time of data transfer, Access Message 2 and 4 for notifying the transfer destination of processing contents at the time of data transfer, and Access Size 3 for notifying size information of transfer data to the transfer destination at the time of data transfer. There are five.

  FIG. 4 is a diagram illustrating an example of a bus matrix. The transfer destination path of the internal bus 101 is formed by a bus matrix as shown in FIG. By referring to such a bus matrix, a transfer destination path between each functional module is determined. FIG. 4 shows a data transfer path from the first module 102 on the writing side to the sixth module 107 on the transfer destination as in the above example. By rewriting the port address of the internal bus 101 as shown in FIG. 5, each switch of the bus matrix can be switched, and as a result, a transfer destination path can be secured.

  For example, the first module 102 on the writing side can directly transfer data following the notification of the processing size and the processing content to the sixth module 107 that is the direct transfer destination through the path indicated by the arrow.

It is a block diagram which shows the structure of the data processor of this invention. It is a figure which shows the bus data flow in a data processor. It is a figure which shows the example of the command used by the data processor of this invention. It is a figure which shows the example of a bus matrix. 3 is a diagram illustrating an example of a port address of an internal bus 101. FIG.

Explanation of symbols

101 Internal bus 102 1st module 103 2nd module 104 3rd module 105 4th module 106 5th module 107 6th module 108 7th module 109 Local bus controller 110 SDRAM controller 113 External large capacity memory

Claims (6)

  There are multiple functional modules, and before each functional module starts to transfer data to the internal bus, the functional module on the writing side must send processing information indicating the processing contents directly to the subsequent functional module. A data processing apparatus.   The data processing apparatus according to claim 1, wherein the internal bus determines a transfer destination path by a direct command issued by each functional module before the start of transfer.   3. The data processing according to claim 2, wherein the transfer destination path determined by the internal bus is formed of a bus matrix, and each switch of the bus matrix is switched by rewriting a port address to determine the transfer destination path. apparatus.   The data processing apparatus according to claim 1, wherein after the internal bus determines the transfer destination path, data is transferred in a minimum unit from a functional module on a writing side to a functional module on a subsequent stage.   The data processing apparatus according to claim 1, wherein each functional module has a unique address. A large-capacity memory having a storage capacity equal to or greater than a predetermined capacity;
When transferring data from the writing-side functional module to the subsequent-stage functional module via the large-capacity memory, the command sent by the writing-side functional module sent to the large-capacity memory is sent before starting the data transfer. The data processing apparatus according to claim 1, wherein a subsequent functional module is determined by analysis.

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