JP6631370B2 - Microcomputer and electronic control unit - Google Patents

Description

  The present invention relates to a microcomputer that performs communication between a plurality of cores, and an electronic control device that includes the microcomputer.

  In a microcomputer having a plurality of cores, it is generally necessary to communicate between the cores. Hereinafter, the microcomputer is abbreviated as “microcomputer”. When communication is performed between cores, it is common practice to provide a shared memory that can be accessed from a plurality of cores, or to use a communication channel for communication between two processors, for example, as disclosed in Patent Document 1. Has been done.

  In this configuration, the core that transmits data accesses the storage area of another core via the communication channel, and the core that receives data accesses the corresponding storage area and reads the stored data to establish a connection between the cores. Perform communication. In this case, while the transmitting core is writing data or the receiving core is reading data, other cores can execute other processing, so that data transfer can be performed efficiently.

JP 2005-534094 A

  In the configuration of Patent Document 1, while efficient communication is possible, a combination of communicable cores is determined in advance. Therefore, it is not possible to flexibly change the combination of the cores communicated by the microcomputer including the plurality of cores.

  By the way, as one of means for performing communication between a plurality of cores flexibly and efficiently, it is assumed that a FIFO (Fast In First Out) is used for a common storage area. When the configuration of Patent Document 1 is adopted, the storage area on the receiving side can be directly accessed from the core on the transmitting side, so that management by a program is necessary to realize data communication similar to communication using FIFO for the common storage area. It becomes. Therefore, there is a problem that the processing time of the program increases.

  The present invention has been made in view of the above circumstances, and has as its object to provide a microcomputer capable of realizing FIFO communication between arbitrary cores without the need for management by a program, and an electronic control device including the microcomputer. To provide.

  According to the microcomputer of the first aspect, the buffer provided in the inter-core communication unit is accessed by a plurality of cores, and data transferred by inter-core communication performed between them is stored by first-in first-out control. Then, the interrupt transmitting unit transmits an interrupt signal to the core to control the communication between the cores. With this configuration, data transferred by communication performed between a plurality of cores can be stored in a buffer by first-in first-out control, and transfer between cores performed through the buffer can be controlled by interruption. There is no need to manage the transfer by a program in each core, and FIFO communication can be easily realized.

Further, according to the microcomputer according to claim 1, wherein, by performing a designation by setting register switches the destination of the interrupt signal by the interrupt transmission section in accordance with the state of the data stored in the buffer. Therefore, the transmission destination core can recognize that the data to be received is stored in the buffer by the interruption. Further, since the status register indicates the storage status of data in the buffer, the core can recognize the status of the buffer by referring to the status register when reading / writing of data from / to the buffer is not completed.

According to claim 2 microcomputer according completion as setting register, a source setting register for designating a core for transmitting an interrupt signal when the state data can be written to the buffer, the writing of data to the buffer And a reception source setting register for designating a core to which an interrupt signal is to be transmitted when an error occurs. With this configuration, it is possible to arbitrarily set the data transmission source and transmission destination cores in the inter-core communication and generate an interrupt for each of them.

FIG. 2 is a functional block diagram illustrating a configuration of a microcomputer and an electronic control device according to the first embodiment. Flowchart showing processing related to preparation for inter-core communication Flow chart showing processing by the core on the transmitting side Flow chart showing processing by the core on the receiving side Timing chart showing an example of inter-core communication 2 is a functional block diagram illustrating a configuration of a microcomputer and an electronic control device according to a second embodiment.

(1st Embodiment)
Hereinafter, the first embodiment will be described. As shown in FIG. 1, the microcomputer 1 of the present embodiment is connected to a plurality of cores 2 (1), 2 (2),... 2 (n) and these cores 2 via a shared bus 3. And a FIFO communication device 4. The FIFO communication device 4 includes a buffer register unit 5 and an interrupt transmission unit 6. The buffer / register unit 5 includes a FIFO buffer 7, an interrupt destination setting register 8, and a status register 9. Further, the interrupt transmission unit 6 inputs the interrupt signals INT ′ (1) to INT (n) to each of the cores 2 (1) to 2 (n). The FIFO communication device 4 corresponds to an inter-core communication unit.

  The FIFO buffer 7 is a storage area for managing data in a first-in first-out order. Writing and reading from and to the FIFO buffer 7 from the core 2 are exclusively controlled, and data is not read and written by a plurality of cores 2 at the same time. Data can be written to the FIFO buffer 7 until a predetermined storage capacity is reached. In addition, when there is valid data written in the FIFO buffer 7, data can be read from the FIFO buffer 7.

  When reading data from the FIFO buffer 7, the data is read in the order of writing. Then, the data once read is deleted, and the area where the data is stored becomes a writable area again. Therefore, when the storage capacity of the FIFO buffer 7 reaches the upper limit, data cannot be written, and the writing core 2 needs to wait for a free space in the storage area. Similarly, when there is no valid data in the FIFO buffer 7, the reading core 2 needs to wait until valid data is stored in the FIFO buffer 7.

  The interrupt destination setting register 8 has two setting areas SND and RCV. In these areas, the core 2 to which the interrupt signal is transmitted is specified. An interrupt signal INT is transmitted to the core 2 designated as the area SND when data can be written to the storage area of the FIFO buffer 7. Further, an interrupt signal INT is transmitted to the core 2 designated as the area RCV when valid data exists in the storage area of the FIFO buffer 7. That is, the core 2 on the data transmission side is specified in the area SND, and the core 2 on the data reception side is specified in the area RCV.

  The interrupt signal INT is transmitted from the interrupt transmission unit 6 to the core 2 specified by these areas SND and RCV. If the core 2 is not specified in the area SND, the interrupt signal INT is not transmitted to any of the cores 2. Similarly, if no core 2 is specified in the region RCV, the interrupt signal INT is not transmitted to any core 2. The area SND corresponds to a transmission source setting register, and the area RCV corresponds to a reception source setting register.

  The status register 9 is a register indicating the status of the FIFO buffer 7, and the core 2 can know the status of the FIFO buffer 7 by reading the register value. Specifically, the status register 9 stores (1) a state in which there is no valid data in the storage area of the FIFO buffer 7, (2) a state in which there is no free space in the storage area of the FIFO buffer 7, and (3) a state in which data is stored in the FIFO buffer 7. A state in which data can be added and a state in which data can be read from the FIFO buffer 7 are shown. For example, the electronic control unit 10 for controlling the vehicle is configured by adding a peripheral circuit (not shown) to the microcomputer 1.

  Next, the operation of the present embodiment will be described. As shown in FIG. 2, in preparation for inter-core communication using the FIFO communication device 4, three processes are mainly required. One is to initialize the FIFO buffer 7 (S1), and the other is to set the area RCV of the interrupt destination setting register 8 (S2). In the area RCV, the core 2 on the receiving side is specified among the cores 2 that perform communication as described above. The other one is the setting of the area SND of the register 8 (S3). In the area SND, of the cores 2 that perform communication, the transmission-side core 2 is specified. If no interrupt is used in the process on the transmitting side, this setting can be omitted.

  Note that the above three processes are performed when the number of the buffer / register unit 5 is one as in the present embodiment. When a FIFO communication device including a plurality of buffer / register units 5 is used as in a second embodiment described later, it is necessary to perform the above three processes for all the buffer / register units 5 used for communication ( S4).

  As shown in FIG. 3, when data is written from the core 2 using the FIFO communication device 4, first, data writing to the FIFO buffer 7 is attempted (S11). At this time, since access to the FIFO buffer 7 is exclusively controlled by the logic of the buffer 7, it is not necessary to acquire a lock using an exclusive control mechanism as in the related art. Then, it is determined whether or not the writing to the FIFO buffer 7 has been completed (S12). This determination is made based on a value indicating whether “write completed” or “write error” is set in the write destination. If the writing to the FIFO buffer 7 has been completed (YES), the writing process ends. On the other hand, if the writing has not been completed (NO), it is necessary to wait until the writing becomes possible (S13, S14).

  Here, there are two methods for the above-mentioned standby processing, one of which uses an interrupt. In the preparation process shown in FIG. 2, if the area SND of the interrupt destination setting register 8 has been set, the corresponding core 2 is set to be ready to accept an interrupt, and waits until an interrupt signal INT is input. If the area SND is not set, the reception of the interrupt is set after designating the core 2 on the transmission side, and the apparatus waits until an interrupt signal INT is input. During standby, if an interrupt signal INT is input to the core 2, writing to the FIFO buffer 7 is possible, so writing to the FIFO buffer 7 is tried again.

  Another method is to use the status register 9 of the buffer register unit 5. The register value of the state register 9 reflects the four states (1) to (4) as described above. Therefore, the core 2 may refer to the value of the status register 9 to check whether the value is a state in which data can be added to the FIFO buffer 7. If it is in a writable state, an attempt is made to write 7 into the FIFO buffer again. If it is not in a writable state, reading the value of the state register 9 again and checking the state of the FIFO buffer 7 are repeated.

  As shown in FIG. 4, when the core 2 receives data, first, it tries to read data into the FIFO buffer 7 (S21). At this time, similarly to the writing, it is not necessary to acquire the lock using the exclusive control mechanism. When the reading from the FIFO buffer 7 has been completed ("YES" in S22), the reading process is terminated. If the data cannot be read ("NO" in S22), the process waits until the data can be read (S23, S24). Whether the data can be read from the FIFO buffer 7 can be determined based on the read value. If the value is an error value, the data is not read. If the value is not an error value, the data is read.

  As in the case of the writing, there are two methods for waiting for the data to be read from the FIFO buffer 7 and becoming readable. In the method using the first interrupt, in the preparation flow shown in FIG. 2, immediately after setting the area RCV of the setting register 8, if not set, the receiving side core 2 is set. Wait for the interrupt to be accepted and wait for a notification by the interrupt. If there is a notification by an interrupt during standby, it indicates that reading from the FIFO buffer 7 is possible, and the core 2 retries reading.

  In the method using the second status register 9, the value of the status register 9 is obtained, and it is confirmed whether the data can be read from the FIFO buffer 7 based on the obtained value. If the state is readable, the reading from the FIFO buffer 7 is tried again. If the state is not readable, the reading of the value of the state register 9 and the confirmation of the state are repeated.

  For example, in the example shown in FIG. 5, the core 2 (1) is on the transmitting side, and the core 2 (2) is on the receiving side. The core 2 (1) starts the processing (A) when the areas RCV and SND of the setting register 8 are set in the initialization processing shown in FIG. Here, the writing 1 to the FIFO buffer 7, which is the process on the transmitting side shown in FIG. 3, is performed. When the writing 1 is completed, the state of the FIFO buffer 7 is changed to "Full" (C), which is a state in which there is no empty space from (1) to (2).

  The core 2 that performs the initialization processing shown in FIG. 2 is, for example, a master among a plurality of cores 2. In this case, the core 2 (1) is specified in advance in, for example, a control program. Only the core 2, which is the master, performs this.

  On the other hand, the core 2 (2) also recognizes in advance that it is set on the receiving side in, for example, a control program, and after performing the initialization processing performed on the core 2 (2), the processing on the receiving side. To start. The core 2 (2) cannot read data in the state of “Empty” where the FIFO buffer 7 has been initialized and no valid data exists. However, in this case, the core 2 (2) has not started reading data during the period when the FIFO buffer 7 is "Empty", and a state of waiting for reading has not occurred.

  Subsequently, the core 2 (1) performs the writing 2 of the data to be transmitted next (D), but the reading 1 by the core 2 (2) is not completed, and the FIFO buffer 7 is in the “Full” state. Wait for a while. Here, it waits for a notification by the interrupt from the interrupt transmitting unit 6 (E). When the reading 1 by the core 2 (2) is completed, (F) an interrupt to the core 2 (1) occurs. As a result, the core 2 (1) recognizes that the FIFO buffer 7 has changed to the state (3) “Empty” and performs (G) write 2. On the other hand, the core 2 (2) starts the next processing (H), but also in this case, the FIFO buffer 7 has not started data reading 2 during the “Empty” period, and no standby state has occurred.

  The core 2 (2) starts the reading 2 after the point (I) at which the writing 2 by the core 2 (1) is completed. The core 2 (1) starts the next processing after the completion of the write 2 (J), but does not start the next data write 3 while the FIFO buffer 7 is in the “Full” state, and waits. No condition has occurred.

When the reading 2 is completed (K), the core 2 (2) starts the next reading 3 (L), but the writing 3 by the core 2 (1) is not completed, and the FIFO buffer 7 is in the “Empty” state. It is in. Therefore, the core 2 (2) cannot execute the reading 3, and waits for an interrupt (M). Then, when the writing 3 by the core 2 (1) is completed (N), the core 2 (2) receives the notification by the interrupt signal and executes (O) the reading 3, and thereafter the reading 3 is completed (P). .

  In the example shown in FIG. 5, from the state where the core 2 is waiting for writing or reading, it is recognized by the notification by the interrupt signal that writing or reading has become possible. This may be recognized by the core 2 referring to the status register 9 by polling, as shown in FIGS.

  As described above, according to the present embodiment, the FIFO buffer 7 included in the FIFO communication device 4 is accessed by the plurality of cores 2 and stores data transferred by inter-core communication performed between the cores 2 on a first-in first-out basis. You. The interrupt transmission unit 6 transmits an interrupt signal to the core 2 to control communication between the cores. With this configuration, data transferred by communication performed between the plurality of cores 2 can be stored in the FIFO buffer 7 by first-in first-out control.

  Since data transfer between the cores 2 via the FIFO buffer 7 can be controlled by interruption, management of the transfer by each core 2 in a program is not necessary, and FIFO communication can be easily realized. That is, efficient FIFO communication between the cores 2 can be performed in fewer steps than in the related art, so that the processing load of the program can be reduced and the creation of a program relating to the FIFO communication becomes easy.

  Also, by specifying the setting register 8, the destination of the interrupt signal by the interrupt transmitting unit 6 is switched according to the state of the data stored in the FIFO buffer 7, so that the transmission destination core 2 should receive the signal. The fact that the data has been stored in the FIFO buffer 7 can be recognized by the notification of the interrupt. Further, since the status register 9 indicates the data storage status in the FIFO buffer 7, the core 2 recognizes the status by referring to the status register 9 when reading / writing of data from / to the FIFO buffer 7 is not completed. it can.

  Further, as the setting register 8, an area SND for designating the core 2 that transmits an interrupt signal when data can be written to the FIFO buffer 7, and an interrupt signal when data writing to the FIFO buffer 7 is completed And a region RCV for designating the core 2 to be transmitted. With this configuration, it is possible to arbitrarily set the data transmission source and the transmission destination core 2 in the inter-core communication, and generate an interrupt for each of them.

  If there is no free area in the FIFO buffer 7 where data can be written, the core 2 on the transmission side waits for a write process until a free area is generated. At this time, when an empty area occurs in the FIFO buffer 7, the interrupt transmitting unit 6 transmits an interrupt signal to the core 2 in a data write waiting state. Can confirm the occurrence of an empty area. The transmission-side core 2 can also determine whether or not an empty area has occurred by referring to the status register 9.

  If there is no readable data in the FIFO buffer 7, the core 2 on the receiving side waits for a reading process until data is written to the FIFO buffer 7. At this time, when the writing of data to the FIFO buffer 7 is completed, the interrupt transmitting unit 6 transmits an interrupt signal to the core 2 which is in a data read waiting state. The completion of data writing can be confirmed by the signal. Also, the core 2 on the receiving side can determine whether the writing has been completed by referring to the status register 9.

(2nd Embodiment)
Hereinafter, the same portions as those of the first embodiment will be denoted by the same reference numerals, and the description thereof will be omitted, and different portions will be described. The microcomputer 11 of the second embodiment shown in FIG. 6 includes a FIFO communication device 12 instead of the FIFO communication device 4. The FIFO communication device 12 has a plurality of buffer / register units 5 (1), 5 (2),..., 5 (n), and the common interrupt transmission unit 13 is controlled by these units. The electronic control unit 14 includes the microcomputer 11.

  Each core 2 can access any of the buffer / register sections 5 (1), 5 (2),..., 5 (n) via the shared bus 3. Therefore, for the combination of transmission and reception by the same core 2, inter-core communication using an arbitrary number of buffer registers 5 is possible.

The present invention is not limited only to the embodiments described above or illustrated in the drawings, and the following modifications or extensions are possible.
The process of referring to the status register 9 when judging whether writing or reading is possible may be performed as needed.
The present invention is not limited to the electronic control device for controlling the vehicle, and may be applied to other electronic control devices and microcomputers constituting other devices.

  1 microcomputer, 2 cores, 4 FIFO communication device, 5 buffer register section, 6 interrupt transmission section, 7 FIFO buffer, 8 interrupt destination setting register, 9 status register, 10 electronic control unit.

Claims (10)

A plurality of cores (2);
A buffer (7) in which data accessed by the plurality of cores and transferred by inter-core communication performed between the plurality of cores is stored by first-in first-out control, and an interrupt to the core for controlling the inter-core communication is performed. An inter-core communication unit (4, 12) having an interrupt transmission unit (6, 13) for transmitting a signal,
A setting register (8) for switching a transmission destination of an interrupt signal by the interrupt transmission unit according to a state of data stored in the buffer;
A status register indicating a data storage status in the buffer;
A microcomputer comprising: A source setting register (SND) for designating a core that transmits an interrupt signal when data is ready to be written to the buffer;
A receiver setting register (RCV) for designating a core to which an interrupt signal is transmitted when data writing to the buffer is completed;
The microcomputer according to claim 1, further comprising: It said setting register and claim 1 or 2 microcomputer according comprising a plurality of sets of the status register. Core of the transmission side of the data, unless free space available to write data into the buffer is present, any one of claims 1 to 3, waiting for the write processing for the buffer to said free area is generated The microcomputer according to 1. The interrupt transmitting unit transmits an interrupt signal to a core in a data write waiting state when an empty area occurs in the buffer,
5. The microcomputer according to claim 4 , wherein the core on the transmission side confirms the occurrence of the empty area based on the interrupt signal. The microcomputer according to claim 4, wherein the transmission side core determines whether or not the free area has occurred by referring to the status register. 7. The data receiving core according to any one of claims 1 to 6 , wherein if there is no readable data in the buffer, the core on the data receiving side waits for a reading process on the buffer until data is written in the buffer. Microcomputer. When the writing of the data to the buffer is completed, the interrupt transmitting unit transmits an interrupt signal to the core in a data read waiting state,
8. The microcomputer according to claim 7 , wherein the core on the receiving side confirms the completion of the writing by the interrupt signal. The receiving side to become core you determine the presence or absence of write completion to said buffer by referring to the status register 請 Motomeko 7 microcomputer according. An electronic control device comprising the microcomputer (1, 11) according to any one of claims 1 to 9 .

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