JP2006216936A - Liquid crystal display device, manufacturing method thereof the same and tft array substrate used therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device of low consumption power by higher numerical aperture in which a yield loss by a short circuit is prevented between gate wirings or first electrode wirings, and lines of its pattern is made to be finer by constituting the gate wirings or the first electrode wirings by using a material with small specific resistance, and also to provide a manufacturing method thereof with high yield, and a TFT array substrate used therefor. <P>SOLUTION: A gate electrode and a gate wiring, or a first electrode, a first electrode wiring, and a second electrode are constituted of a two-layer film of Al or Al alloy and a metal layer with higher hardness than Al on the surface side, or a multi-layer films thereof. These elements clean a metal film with higher hardness than Al by brush, and apply patterning to it to thereby prevent a short circuit between wiring portions. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to an active matrix type liquid crystal display device in which a thin film transistor (hereinafter referred to as TFT (Thin Film Transistor)) is mounted as a switching element, a manufacturing method thereof, and a TFT array substrate used in the liquid crystal display device. .

  FIG. 17 is a sectional view showing a manufacturing process of a TFT array substrate on which TFTs of a TFT type liquid crystal display device having a conventional low resistance signal wiring are mounted. In the figure, 1 is a transparent insulating substrate such as a glass substrate, 2 is a gate wiring having a gate electrode formed on the transparent insulating substrate 1, 3 is a common wiring, and 5 is a gate insulating formed on the gate wiring 2. 6 is a semiconductor layer formed on the gate electrode 2 via the gate insulating film 5, 7 is an ohmic contact layer formed on the semiconductor layer 6, 8 is a pixel electrode, and 10 and 11 are on the ohmic contact layer 7. A source electrode and a drain electrode 12 formed on the substrate 12 are protective films.

Next, a method for manufacturing a TFT array substrate on which a conventional TFT is mounted will be described. First, as shown in FIG. 17A, a single layer film made of a metal having a small specific resistance of Al or Al alloy is formed on the surface of the transparent insulating substrate 1, and then patterned using a resist formed by a photolithography method. Then, the gate wiring 2 having the gate electrode and the common wiring 3 are formed. Next, as shown in FIG. 17B, after the silicon nitride film that becomes the gate insulating film 5 and the amorphous silicon film, and the n ⁺ type amorphous silicon film doped with impurities are continuously formed by plasma CVD, The amorphous silicon film and the n ⁺ -type amorphous silicon film are simultaneously patterned by using a resist formed by photolithography, and the semiconductor layer 6 and the ohmic contact layer 7 are formed at a position above the gate wiring 2.

Next, as shown in FIG. 17C, after forming an ITO (Indium Tin Oxide) film as a transparent conductive film, patterning is performed using a resist formed by a photoengraving method to form a pixel electrode 8. Next, the source electrode 10 and the drain electrode 11 are formed on the ohmic contact layer 7. Here, the source electrode 10 and the drain electrode 11 are a film made of Cr, Ti or the like as a barrier metal in order to improve ohmic contact characteristics with the n ⁺ -type amorphous silicon film in the lower layer, and a specific resistance to lower the resistance in the upper layer. Has a two-layer film structure made of a film made of Al or Al alloy. Further, the Al film is dissolved in the developing solution by the resist developing solution used for patterning the Al film, and the ITO film constituting the Al film and the underlying pixel electrode 8 causes a battery reaction in the developing solution. In order to prevent the film from being corroded, W or the like may be added as an Al alloy. Finally, as shown in FIG. 17D, silicon nitride is deposited to form the protective film 12.

  As described above, in order to obtain a low power consumption liquid crystal display device in a conventional TFT type liquid crystal display device, a single layer film made of an Al film or an Al alloy film, or a multilayer film having an Al-based metal film on the surface layer is used. When the low-resistance signal wiring is used, the Al-based metal is soft, so that the surface of the film is damaged when it is strongly cleaned using a brush or the like. For this reason, when forming a resist for patterning an Al-based metal film, cleaning with a pure water jet or ultrasonic waves can be performed, but cleaning with a brush cannot be performed. As a result, the dust on the film surface cannot be removed sufficiently, and the resist remaining in the dust and the periphery of the dust serves as a mask, and the Al-based metal film in that portion remains without being etched, causing a short circuit and reducing the yield. It was decreasing. In addition, when signal wiring is formed with a metal film of relatively high hardness such as a metal film of Cr, Ti, Ta or Mo, or an alloy film other than an Al alloy containing these metals, dust that could not be removed by brush cleaning. Alternatively, there is a problem that even a small amount of dust adhered after washing causes a metal film etching residue to cause a short circuit and reduce the yield.

The present invention has been made to solve the above-described problems, and prevents a decrease in yield due to a short circuit between the wirings, and the signal wiring is formed by using a material having a small specific resistance to form the pattern. An object of the present invention is to provide a liquid crystal display device with low power consumption by thinning and high aperture ratio, a manufacturing method for manufacturing the liquid crystal display device with a high yield , and a TFT array substrate used for the liquid crystal display device .

Method of manufacturing a liquid crystal display device according to the present invention includes a transparent insulating substrate, a gate electrode and gate wiring, a semiconductor layer, a first electrode constituting a thin film transistor with the above semiconductor layer, the first electrode wire and the first substrate having a second electrode, an insulating film formed between the gate electrode and the gate wiring and the semiconductor layer, the second electrode and electrically connected to the pixel electrode, and the second the manufacturing method of the liquid crystal display device having a second substrate sandwiching a liquid crystal material with one of the substrate, the gate electrode and the gate wiring is, Al or Al alloy, and hardness of Al is high metal sequentially deposited Forming a two-layer film, and cleaning the surface of the two-layer film with a brush, forming a resist, and etching the two-layer film.

The method for manufacturing a liquid crystal display device according to the present invention includes a transparent insulating substrate, a gate electrode and a gate wiring, a semiconductor layer, a first electrode that constitutes a thin film transistor together with the semiconductor layer, a first electrode wiring, and A first substrate having a second electrode, an insulating film formed between the gate electrode and gate wiring and the semiconductor layer, and a pixel electrode electrically connected to the second electrode; In the method of manufacturing a liquid crystal display device including a second substrate that sandwiches a liquid crystal material together with the substrate, the first electrode, the second electrode, and the first electrode wiring are films whose surface layers are made of Al or an Al alloy. On top of this, a metal film having a hardness higher than that of Al is formed to form a multilayer film, and a process of etching the multilayer film by forming a resist after cleaning the surface of the metal film having a hardness higher than that of Al with a brush. Characterized in that it is formed by.

The liquid crystal display equipment according to the present invention includes a transparent insulating substrate, Al or Al alloy and, after forming sequentially deposited by double layer hardness higher metal than Al, the surface of the bilayer membrane A gate electrode and gate wiring formed by forming a resist after cleaning with a brush and etching the two-layer film, a semiconductor layer, and a first electrode and a first electrode constituting a thin film transistor together with the semiconductor layer A first substrate having a wiring and a second electrode, an insulating film formed between the gate electrode and the gate wiring and the semiconductor layer, a pixel electrode electrically connected to the second electrode, and A second substrate for sandwiching a liquid crystal material together with the first substrate is provided .

The liquid crystal display equipment includes a transparent insulating substrate, a gate electrode and gate wiring, a semiconductor layer, a first electrode constituting a thin film transistor with the above semiconductor layer, the first electrode wire and the second according to the present invention Together with the first electrode, the gate electrode and the gate wiring, the insulating film formed between the semiconductor layers, the pixel electrode electrically connected to the second electrode, and the first substrate A liquid crystal display device comprising a second substrate for sandwiching a liquid crystal material, wherein the first electrode, the second electrode, and the first electrode wiring are metals whose outermost layer is harder than Al characterized by Rukoto such a multilayer film which is present Al or Al alloy on the underlayer.

The liquid crystal display equipment according to the present invention, a transparent insulating substrate, a semiconductor film formed on the transparent insulating substrate, a gate electrode and is formed through an insulating film on the semiconductor film A first substrate having a gate wiring, a first electrode constituting a thin film transistor together with the semiconductor layer, a first electrode wiring and a second electrode, and a pixel electrode electrically connected to the second electrode; And a second substrate sandwiching a liquid crystal material together with the first substrate, wherein the first electrode, the second electrode, and the first electrode wiring have an outermost surface layer made of Al. also the hardness is higher metal, wherein Rukoto such a multilayer film which is present Al or Al alloy on the underlayer.

The liquid crystal display equipment includes a transparent insulating substrate, a gate electrode and a gate wiring, a semiconductor layer, a first electrode constituting a thin film transistor with the above semiconductor layer, the first electrode wire and the second according to the present invention A first substrate having a gate electrode, a gate electrode wiring, an insulating film formed between the semiconductor layers, a pixel electrode electrically connected to the second electrode, and the first substrate And a second substrate sandwiching a liquid crystal material, wherein the gate electrode and the gate wiring have a Mo film on the outermost surface and an Al or Al alloy layer below the two-layer film. Tona and said Rukoto.

The liquid crystal display device according to the present invention includes a transparent insulating substrate, a gate electrode and gate wiring, a semiconductor layer, a first electrode constituting a thin film transistor with the semiconductor layer, the first electrode wire and the second and the electrode, the first substrate having an insulating film formed between the gate electrode and the gate wiring and the semiconductor layer, the second electrode and electrically connected to the pixel electrode, and the first A second substrate sandwiching a liquid crystal material together with the substrate, and the first electrode, the first electrode wiring, and the second electrode are formed of a metal film having a hardness higher than that of Al on a film of Al or Al alloy. After the multilayer film is formed, the surface of the metal film whose hardness is higher than that of Al is washed with a brush, and then a resist is formed and the multilayer film is etched .

The TFT array substrate according to the present invention is formed by sequentially forming a transparent insulating substrate, Al or an Al alloy, and a metal having a hardness higher than Al to form a two-layer film, and then brushing the surface of the two-layer film. first electrode constituting the gate electrode and a gate wiring which is formed by forming a resist after washing etching the double layer, and the semiconductor layer, a thin film transistor with the semiconductor layer, the first electrode having a wiring and a second electrode, an insulating film formed between the gate electrode and the gate wiring and the semiconductor layer, the second electrode and electrically connected to the pixel electrode.

Further, TFT array substrate according to the present invention includes a transparent insulating substrate, a gate electrode and gate wiring, a semiconductor layer, a first electrode constituting a thin film transistor with the above semiconductor layer, the first electrode wire and and a second electrode, a TFT array substrate having an insulating film formed on the gate electrode and the gate wiring and the semiconductor layer, the second electrode and electrically connected to the pixel electrodes, the first electrode, the second electrode and the first electrode wiring outermost layer is a metal the hardness is higher than Al, that a multilayer film which is present Al or Al alloy on the underlayer Features.

Furthermore, TFT array substrate according to the present invention, the transparent insulation and the substrate, the transparent insulating a semiconductor film formed on a substrate, a gate electrode and a gate formed through an insulating film on the semiconductor film and wiring, the first electrode constituting the thin film transistor together with the upper Symbol semiconductor layer, TFT array substrate having a first electrode wiring and a second electrode, on the SL second electrode and electrically connected to the pixel electrode The first electrode, the second electrode, and the first electrode wiring are made of a multilayer film in which the outermost surface layer is a metal having a hardness higher than that of Al and Al or an Al alloy is present in the lower layer. It is characterized by that.

According to this invention, in order to reduce the resistance of the gate wiring or the first electrode wiring, using a two-layer film or a multilayer film having an Al film or an Al alloy film and a metal film having a hardness higher than that of Al, Even when the gate wiring or the first electrode, the second electrode, and the first electrode wiring are configured, the surface of the metal film having a hardness higher than that of Al can be brush-washed to pattern the gate wiring or the first electrode wiring. Therefore, a short circuit between the gate wiring or the first electrode wiring can be prevented. As a result, since the gate wiring or the first electrode wiring can be formed using a material having a low specific resistance, the pattern can be thinned, and a liquid crystal display device with low power consumption can be obtained by increasing the aperture ratio. can, also the liquid crystal display device can be manufactured with a high yield, even TFT array substrate of the liquid crystal display device together, Ru can be produced in high yield.

  Several embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG.
A method for manufacturing a liquid crystal display device equipped with a thin film transistor (TFT) according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing a manufacturing process of a TFT array substrate of a liquid crystal display device equipped with a channel etch type TFT according to Embodiment 1 of the present invention. In the figure, 1 is a transparent insulating substrate such as a glass substrate, and 2 is a control electrode wiring (a gate wiring in this embodiment) having a control electrode (a gate electrode in this embodiment) formed on the transparent insulating substrate 1. 3 is a common wiring formed on the transparent insulating substrate 1 simultaneously with the gate wiring, 4 is a mask layer formed on the gate wiring 2 and the common wiring 3, and 5 is an insulating film formed on the mask layer 4. (In this embodiment, a gate insulating film), 6 is a semiconductor layer formed on the gate wiring 2 via the gate insulating film 5, 7 is an ohmic contact layer formed on the semiconductor layer 6, 8 is a pixel electrode, 9 is a metal film, 10 and 11 are a first electrode having a first electrode wiring (source wiring in the present embodiment) and a second electrode formed on the ohmic contact layer 7 by patterning the metal film 9. Electrode (this implementation The source electrode and the drain electrode in state), 12 is a protective film.

  Next, a manufacturing method of the TFT array substrate of the liquid crystal display device according to the present embodiment will be described. First, as shown in FIG. 1-a, a metal having a small specific resistance such as Al containing 0.2 atomic% of Cu on the surface of the transparent insulating substrate 1 (hereinafter referred to as Al-0.2 at.% Cu). After forming a film of about 200 nm by sputtering or the like, a resist is formed by photolithography, pattern etching is performed using an etchant mainly composed of phosphoric acid, acetic acid and nitric acid, and gate wiring 2 having a gate electrode and common wiring After forming 3, the resist is removed. At this time, an etching solution mainly composed of phosphoric acid, acetic acid and nitric acid is used for etching the Al-0.2 at.% Cu film. The composition of phosphoric acid, acetic acid and nitric acid is studied in advance, and Al-0.2 at. By forming the etching end face of the% Cu film in a tapered shape, the coverage of the film formed in the upper layer can be improved.

Next, as shown in FIG. 1B, a metal having a hardness higher than that of Al, for example, Cr is formed by sputtering to a thickness of about 200 nm, the surface is brush cleaned, a resist is applied, the gate wiring 2 and the common wiring After patterning the resist so that the pattern is covered with an Al-0.2 at.% Cu film such as 3, the exposed Cr film is removed by etching to form a mask layer 4. Thereafter, the resist is removed, and immersed in an etching solution containing, for example, phosphoric acid, acetic acid and nitric acid as main components for a time necessary for etching an Al-0.2 at. Etching residue such as a short-circuit portion between patterns by the 2 at.% Cu film is removed.

Here, a process of removing the short-circuit defect portion generated in the wiring such as the gate wiring 2 will be described with reference to FIGS. When a short-circuit defect 14 occurs between the wirings 13 such as the gate wiring and the source wiring (FIG. 2-a), first, as shown in FIG. 2-b, the mask layer 4 is formed so as to cover the wiring 13 Next, the substrate on which the mask layer 4 is formed is immersed in an etching solution capable of etching the wiring 13, thereby removing the short-circuit defect portion 14 not covered with the mask layer 4 as shown in FIG.
As shown in FIG. 4, the mask layer 4 may have a shape having an opening 15 only in a portion where the wiring 13 pattern in which a short circuit defect is likely to occur is approaching.

Next, as shown in FIG. 1-c, a silicon nitride film to be the gate insulating film 5 is formed by a plasma CVD method or the like to about 500 nm, an amorphous silicon film is about 200 nm, and an n ⁺ type amorphous silicon film doped with impurities is about After sequentially forming 50 nm, an amorphous silicon film and an n ⁺ -type amorphous silicon film are simultaneously patterned using a resist formed by photolithography, and a semiconductor layer 6 and an ohmic contact layer 7 are formed above the gate wiring 2 To do. Next, as shown in FIG. 1-d, an ITO film having a thickness of about 100 nm is formed as a transparent conductive film by sputtering or the like, and then patterned using a resist formed by photolithography, thereby forming a pixel electrode 8.

Next, as shown in FIG. 1-e, an n ⁺ -type amorphous silicon film constituting the ohmic contact layer 7 in the lowermost layer and a refractory metal such as Cr and Ti having good ohmic contact are about 100 nm in comparison with the intermediate layer. About 300 nm of low resistance Al-0.2 at.% Cu, etc., and about 50 nm of Cr having 130% Vickers hardness that is higher in hardness than Al and capable of brush cleaning are formed on the uppermost layer. After the metal film 9 to be formed is formed, brush cleaning is performed. Subsequently, as shown in FIG. 1-f, the metal film 9 is patterned using an etching resist formed by photolithography, and the source electrode 10 and the drain separated into two on the source wiring and the ohmic contact layer 7 are formed. The electrode 11 is formed. Subsequently, the n ⁺ type amorphous silicon film (ohmic contact layer 9) where the source electrode 10 and the drain electrode 11 are removed is etched by dry etching to form a channel portion, and then the resist is removed. Finally, as shown in FIG. 1-g, a silicon nitride film is formed, and a protective film 12 is formed on portions other than on the pixel electrodes 8.

  The TFT array substrate, which is the first substrate thus formed, and the surface of the counter substrate, which is the second substrate, in which the light shielding layer, the overcoat layer and the counter electrode are formed on another transparent insulating substrate. A liquid crystal panel is formed by forming an alignment film so as to face each other, injecting liquid crystal between them and sealing with a sealant, and disposing a polarizing plate outside the opposing array substrate and the opposing substrate.

Although an Al-0.2 at.% Cu film was used as the material of the gate wiring 2, an Al film or an Al alloy having another composition may be used as long as it has a small specific resistance and does not cause corrosion and hillocks due to water. A film (containing 90 at.% Or more of Al) may be used.
Further, although a Cr film is used as the mask layer 4, other metal films such as a W film may be used as long as they are not attacked by the etching solution for the Al alloy film. Further, as a method for etching the etching residue by the Al alloy film, a dry etching method may be used instead of the wet etching method.

  When a liquid crystal display device was manufactured using the above steps, there was no short-circuit defect between wirings that occurred frequently when an Al-based metal film was used for the gate wiring 2, and brush cleaning was also performed on the source wiring. As a result, the defect of the pattern was reduced.

  According to the present invention, in order to reduce the resistance of the signal wiring, the wiring 13 (gate wiring 2) is formed using a single layer film made of an Al film or an Al alloy film or a multilayer film having an Al-based metal film on the surface layer. Even when configured, the wiring 13 is covered with the mask layer 4 or the like, and the short-circuit defect portion 14 between the wirings 13 is surely removed by etching, or a high-hardness metal layer is formed on the surface layer of the wiring 13 (source wiring). By forming a resist and patterning after cleaning, a short circuit between the wirings 13 can be prevented, and the signal wiring can be made thin by using a material having a small specific resistance, and the consumption can be reduced by increasing the aperture ratio. An electric power liquid crystal display device can be manufactured with a high yield.

Embodiment 2. FIG.
FIG. 5 is a sectional view showing a manufacturing process of a TFT array substrate of a liquid crystal display device on which a channel protective film type TFT according to Embodiment 2 of the present invention is mounted. In the figure, 16 is a metal film, 17 is a resist pattern used to form the metal film 16, 18 is a channel protective film, and 19 is a semiconductor layer. Note that the same parts as those in FIG.

  Next, a manufacturing method of the TFT array substrate of the liquid crystal display device according to the present embodiment will be described. First, as shown in FIG. 5A, a metal having a small specific resistance such as Al-0.2 at.% Cu is formed on the surface of the transparent insulating substrate 1 by a sputtering method or the like to a thickness of about 200 nm. Then, a resist is formed by pattern etching using an etchant mainly composed of phosphoric acid, acetic acid and nitric acid to form the gate wiring 2 and the common wiring 3 having gate electrodes, and then the resist is removed. At this time, an etching solution mainly composed of phosphoric acid, acetic acid and nitric acid is used for etching the Al-0.2 at.% Cu film. The composition of phosphoric acid, acetic acid and nitric acid is studied in advance, and Al-0.2 at. By forming the etching end face of the% Cu film in a tapered shape, the coverage of the film formed in the upper layer can be improved.

Next, as shown in FIG. 5B, a metal having a hardness higher than that of Al, such as Cr, is formed to a thickness of about 100 nm by sputtering, the surface is brush cleaned, a resist is applied, and the gate wiring 2 and common wiring After the resist pattern 17 is formed in a shape to be covered with a pattern of Al-0.2 at.% Cu film such as 3 etc., the exposed Cr film is removed by etching, and the metal film 16 such as Cr film and the resist pattern are removed. A mask layer 4 made of 17 is formed. Thereafter, the Al-0.2 at.% Cu film of about 200 nm is immersed in an etching solution containing phosphoric acid, acetic acid, and nitric acid as main components for a time required to etch the Al-0.2 at.% Cu film. After the etching residue such as the short-circuit portion between the patterns is removed, the resist pattern 17 constituting the mask layer 4 is removed.

Next, as shown in FIG. 5C, a silicon nitride film to be the gate insulating film 5 is formed in a thickness of about 500 nm, an amorphous silicon film is formed in a thickness of about 100 nm, and a channel protective film 18 is formed in a thickness of about 250 nm by plasma CVD or the like. Patterning is performed using a resist formed by a plate making method, and a channel protective film 18 is formed at a position above the gate wiring 2. Subsequently, phosphorus ions are implanted into the amorphous silicon film at an acceleration voltage of 20 KeV, for example, to form an n ⁺ type amorphous silicon layer. Next, as shown in FIG. 5D, the amorphous silicon film and the n ⁺ type amorphous silicon layer formed by implanting phosphorus ions are patterned to form a semiconductor layer 19 having an ohmic contact layer on the surface. Next, as shown in FIG. 5E, an ITO film having a thickness of about 100 nm is formed as a transparent conductive film by a sputtering method or the like, and then patterned using a resist formed by a photolithography method to form a pixel electrode 8.

Next, as shown in FIG. 5F, the lowermost layer is made of Cr, Ti or the like having good ohmic contact with the semiconductor layer 19, and the intermediate layer is made of Al-0.2 at. Then, Cr having a hardness higher than Al and capable of brush cleaning is continuously formed on the uppermost layer by about 50 nm, and after forming the metal film 9 made of a three-layer film, brush cleaning is performed. Subsequently, as shown in FIG. 5G, the metal film 9 is patterned using an etching resist formed by photolithography, and the first electrode wiring (source wiring in the present embodiment) and the semiconductor layer 19 are formed. A first electrode and a second electrode (in this embodiment, the source electrode 10 and the drain electrode 11) separated into two are formed. Subsequently, the resist is removed after the chromium silicide layer and the n ⁺ -type amorphous silicon layer formed in the portion where the source electrode 10 and the drain electrode 11 are removed by dry etching. Finally, as shown in FIG. 5H, a silicon nitride film is formed, and a protective film 12 is formed on portions other than on the pixel electrodes 8.

  The TFT array substrate, which is the first substrate thus formed, and the surface of the counter substrate, which is the second substrate, in which the light shielding layer, the overcoat layer and the counter electrode are formed on another transparent insulating substrate. A liquid crystal panel is formed by forming an alignment film so as to face each other, injecting liquid crystal between them and sealing with a sealant, and disposing a polarizing plate outside the opposing array substrate and the opposing substrate.

Although an Al-0.2 at.% Cu film is used as the material of the gate wiring 2, an Al film or an Al alloy having another composition may be used as long as it has a small specific resistance and does not cause corrosion and hillocks due to water. It may be a membrane.
Further, although a Cr film is used as the metal film 16, other metal films such as a W film may be used as long as they are not eroded by the etching solution for the Al alloy film. Further, as a method for etching the etching residue by the Al alloy film, a dry etching method may be used instead of the wet etching method.

  According to the present embodiment, in the liquid crystal display device on which the channel protective film type TFT is mounted, the same effect as in the first embodiment is obtained, and the wiring portion such as the gate wiring 2 is covered with the mask layer 4. When removing a defective portion such as a short-circuit portion between the wirings, the mask layer 4 has a two-layer structure of a metal film 16 such as a Cr film and a resist pattern 17 for patterning the metal film 16. Corrosion of the wiring due to coating failure can be prevented, and the metal film 16 constituting the mask layer 4 can be thinned.

Embodiment 3 FIG.
In the second embodiment, in the channel protective film type TFT, the mask layer 4 at the time of etching the wiring portion such as the gate wiring 2 is described as having a two-layer structure of the metal film 16 and the resist pattern 17. In the etching type TFT, the same effect as in the second embodiment can be obtained even if the mask layer at the time of etching the wiring portion such as the gate wiring has a two-layer structure of the metal film and the resist pattern.

Embodiment 4 FIG.
6 and 7 are cross-sectional views showing a manufacturing process of a TFT array substrate of a liquid crystal display device equipped with a planar type TFT according to Embodiment 4 of the present invention. In the figure, 20 is an amorphous silicon film, 21 is a channel, 22 is a gate wiring, 23 is a gate electrode, 24 is a source / drain region, 25 is an insulating film, and 26 is a contact hole. Note that the same parts as those in FIG.

Next, a manufacturing method of the TFT array substrate of the liquid crystal display device according to the present embodiment will be described. First, as shown in FIG. 6A, an amorphous silicon film 20 is formed to a thickness of about 100 nm on the surface of the transparent insulating substrate 1 by a plasma CVD method or the like. Next, as shown in FIG. 6B, the amorphous silicon film 20 is crystallized into polysilicon by irradiating a laser beam. At this time, the laser is irradiated with, for example, 100 to 300 mj / cm ² of ArF or XeCl excimer laser having a pulse width of 15 to 50 ns. Thereafter, patterning is performed using a resist formed by a photoengraving method to form a channel 21. Next, as shown in FIG. 6-c, silicon oxide or silicon nitride is formed to a thickness of about 200 nm by plasma CVD, atmospheric pressure CVD, or sputtering to form a gate insulating film 5.

  Next, as shown in FIG. 6-d, for example, a metal having a small specific resistance such as Al-0.2 at.% Cu is formed to a thickness of about 200 nm by sputtering or the like, and then a resist is formed by photolithography. Pattern etching is performed using an etchant mainly composed of phosphoric acid, acetic acid, and nitric acid to form the gate wiring 22, and then the resist is removed. At this time, an etching solution mainly composed of phosphoric acid, acetic acid and nitric acid is used for etching the Al-0.2 at.% Cu film. The composition of phosphoric acid, acetic acid and nitric acid is studied in advance, and Al-0.2 at. By forming the etching end face of the% Cu film in a tapered shape, the coverage of the film formed in the upper layer can be improved.

Next, as shown in FIG. 6-e, a metal having a hardness higher than that of Al, for example, Cr is formed to a thickness of about 100 nm by sputtering, and the surface is brush-washed, and then a resist is applied to form the gate wiring 22. After covering the Al-0.2 at.% Cu film and forming the resist pattern 17 for forming the gate electrode 23 made of the Cr film above the channel 21, the exposed Cr film is removed by etching. Then, a mask layer 4 and a gate electrode 23 made of a metal film 16 such as a Cr film and a resist pattern 17 are formed. Thereafter, the Al-0.2 at.% Cu film of about 200 nm is immersed in an etching solution containing phosphoric acid, acetic acid, and nitric acid as main components for a time required to etch the Al-0.2 at.% Cu film. Etching residue such as a short-circuit portion between patterns is removed.

  Next, as shown in FIG. 6-f, before removing the resist pattern 17, phosphorus ions are implanted into the entire surface with, for example, an acceleration voltage of 70 KeV to form an n-type semiconductor to be the source / drain region 24 in the channel 21. . Here, when the metal film 16 constituting the gate electrode 23 is etched, a side etch of about 2 μm is provided so that phosphorus ions are not implanted into the channel 21 below the resist pattern 17 and an offset transistor can be formed. , Off current can be reduced. Subsequently, hydrogen is diffused into the polysilicon and the gate insulating film 5 in hydrogen plasma by ECR plasma CVD or the like, and hydrogen is bonded to the dangling bonds. Next, as shown in FIG. 6-g, silicon oxide or silicon nitride is formed by plasma CVD, atmospheric pressure CVD, or sputtering to form an insulating film 25. Thereafter, annealing is performed at 350 ° C., for example, to activate the amorphous silicon film constituting the source / drain regions 24. Next, as shown in FIG. 7A, an ITO film having a thickness of about 100 nm is formed as a transparent conductive film by sputtering or the like, and then patterned using a resist formed by photolithography, thereby forming a pixel electrode 8. Next, as shown in FIG. 7B, contact holes 26 are formed in the insulating film 25 on the source / drain regions 24.

Next, as shown in FIG. 7C, the lowermost layer is made of an n-type semiconductor which is the source / drain region 24, and Cr or Ti having good ohmic contact is about 100 nm, and the intermediate layer is Al-0. 2 at.% Cu is about 300 nm, Cr is harder than Al and has a thickness of about 50 nm that can be brush cleaned on the uppermost layer, and after forming a three-layer film, brush cleaning is performed. Subsequently, the three-layer film is patterned using an etching resist formed by photolithography, and the source / drain region 24 is electrically connected to the first electrode wiring (in this embodiment, the source wiring) and the contact hole 26. The first electrode and the second electrode (source electrode 10 and drain electrode 11 in this embodiment) are connected to each other. Finally, as shown in FIG. 7D, a silicon nitride film is formed, and a protective film 12 is formed on portions other than on the pixel electrodes 8.

The TFT array substrate, which is the first substrate thus formed, and the surface of the counter substrate, which is the second substrate, in which the light shielding layer, the overcoat layer, and the counter electrode are formed on another transparent insulating substrate. A liquid crystal panel is configured by forming an alignment film so as to face each other, injecting liquid crystal therebetween and sealing with a sealing agent, and disposing a polarizing plate outside the opposing array substrate and the opposing substrate.
Although an Al-0.2 at.% Cu film is used as the material of the gate wiring 22, an Al film or an Al alloy having another composition may be used as long as it has a small specific resistance and does not cause corrosion and hillocks due to water. It may be a membrane.
Further, although a Cr film is used as the metal film 16, other metal films such as a W film may be used as long as they are not eroded by the etching solution for the Al alloy film. Further, as a method for etching the etching residue by the Al alloy film, a dry etching method may be used instead of the wet etching method.

  According to the present embodiment, the same effect as in the second embodiment can be obtained in the liquid crystal display device on which the planar type TFT is mounted.

Embodiment 5. FIG.
FIG. 8 is a sectional view showing a manufacturing process of a TFT array substrate of a liquid crystal display device on which a TFT according to Embodiment 5 of the present invention is mounted. In the figure, reference numeral 27 denotes auxiliary capacitance wiring. Note that the same parts as those in FIG.

Next, a manufacturing method of the TFT array substrate of the liquid crystal display device according to the present embodiment will be described. First, as shown in FIG. 8A, a metal having a small specific resistance such as Al-0.2 at.% Cu is formed on the surface of the transparent insulating substrate 1 by a sputtering method or the like, and then a photolithography process is performed. Then, a resist is formed by pattern etching using an etchant mainly composed of phosphoric acid, acetic acid and nitric acid to form the gate wiring 2 having the gate electrode and the auxiliary capacitance wiring 27, and then the resist is removed. At this time, an etching solution containing phosphoric acid, acetic acid and nitric acid as main components is used for etching the Al-0.2 at.% Cu film. The composition of phosphoric acid, acetic acid and nitric acid was examined in advance, and Al-0.2 at. By forming the etching end face of the% Cu film in a tapered shape, the coverage of the film formed in the upper layer can be improved.
Further, the auxiliary capacitor wiring 27 has a structure short-circuited with the gate wiring 2 for each pixel, thereby providing a redundant structure against disconnection of the gate wiring 2.

Next, as shown in FIG. 8B, a metal having a hardness higher than that of Al, for example Cr, is formed to a thickness of about 100 nm by sputtering, the surface is brush-cleaned, a resist is applied, gate wiring 2 and auxiliary capacitance After the resist pattern 17 is formed in a shape in which the pattern of the Al-0.2 at.% Cu film such as the wiring 27 for use is covered, the exposed Cr film is removed by etching, and the metal film 16 such as a Cr film is formed. A mask layer 4 made of a resist pattern 17 is formed. Thereafter, for example, an Al-0.2 at.% Cu film of about 300 nm is immersed in an etching solution containing phosphoric acid, acetic acid and nitric acid as main components for the time required to etch the Al-0.2 at.% Cu film. Etching residue such as a short-circuit portion between patterns is removed. Next, as shown in FIG. 8C, the resist pattern 17 and the metal film 16 constituting the mask layer 4 are removed.

The subsequent steps are the same as those after the formation of the gate insulating film by the plasma CVD method or the like in the first or second embodiment, and a channel etch type liquid crystal display device or a channel protective film type liquid crystal display device is formed. .
Although an Al-0.2 at.% Cu film is used as the material of the gate wiring 2, an Al film or an Al alloy having another composition may be used as long as it has a small specific resistance and does not cause corrosion and hillocks due to water. It may be a membrane.
Further, although a Cr film is used as the mask layer 4, other metal films such as a W film may be used as long as they are not attacked by the etching solution for the Al alloy film. Further, as a method for etching the etching residue by the Al alloy film, a dry etching method may be used instead of the wet etching method.

  According to the present embodiment, the same effect as in the second embodiment can be obtained, and after the wiring portion such as the gate wiring 2 is covered with the mask layer 4 and the defective portion such as the short-circuit portion between the wirings is removed, Since the metal film 16 constituting the mask layer 4 is also removed, it is possible to prevent the occurrence of short-circuit defects due to the metal film 16.

Embodiment 6 FIG.
FIG. 9 is a sectional view showing a manufacturing process of a TFT array substrate of a liquid crystal display device on which a TFT according to Embodiment 6 of the present invention is mounted. The reference numerals in the figure are the same as those in FIG.

Next, a manufacturing method of the TFT array substrate of the liquid crystal display device according to the present embodiment will be described. First, as shown in FIG. 9A, a metal having a small specific resistance such as Al-0.2 at.% Cu is formed on the surface of the transparent insulating substrate 1 by a sputtering method or the like, and then a photolithography process is performed. Then, a resist is formed by pattern etching using an etchant mainly composed of phosphoric acid, acetic acid, and nitric acid to form the gate wiring 2 having the gate electrode and the auxiliary capacitor wiring 27, and then the resist is removed. At this time, an etching solution containing phosphoric acid, acetic acid and nitric acid as main components is used for etching the Al-0.2 at.% Cu film. The composition of phosphoric acid, acetic acid and nitric acid was examined in advance, and Al-0.2 at. By forming the etching end face of the% Cu film in a tapered shape, the coverage of the film formed in the upper layer can be improved.
Further, the auxiliary capacitor wiring 27 has a structure short-circuited with the gate wiring 2 for each pixel, thereby providing a redundant structure against disconnection of the gate wiring 2.

  Next, as shown in FIG. 9B, a resist is applied, and a resist pattern 17 is formed in a shape that covers the pattern of the Al-0.2 at.% Cu film such as the gate wiring 2 and the auxiliary capacitance wiring 27. The mask layer 4 is used. Thereafter, for example, an Al-0.2 at.% Cu film of about 300 nm is immersed in an etching solution containing phosphoric acid, acetic acid and nitric acid as main components for the time required to etch the Al-0.2 at.% Cu film. Etching residue such as a short-circuit portion between patterns is removed. Next, as shown in FIG. 9C, the resist pattern 17 constituting the mask layer 4 is removed.

The subsequent steps are the same as those after the formation of the gate insulating film by the plasma CVD method or the like in the first or second embodiment, and a channel etch type liquid crystal display device or a channel protective film type liquid crystal display device is formed. .
Although an Al-0.2 at.% Cu film is used as the material of the gate wiring 2, an Al film or an Al alloy having another composition may be used as long as it has a small specific resistance and does not cause corrosion and hillocks due to water. It may be a membrane.
Further, as a method for etching the etching residue by the Al alloy film, a dry etching method may be used instead of the wet etching method.

  According to the present embodiment, the same effect as in the first embodiment can be obtained, and when a wiring portion such as the gate wiring 2 is covered with the mask layer 4 to remove a defective portion such as a short-circuit portion between the wirings, By using the mask layer 4 as the resist pattern 17, the process can be simplified.

Embodiment 7 FIG.
10 and 11 are cross-sectional views showing a manufacturing process of a TFT array substrate of a storage capacitor on-gate type liquid crystal display device equipped with a channel etch type TFT according to Embodiment 7 of the present invention. In the figure, 28 is a gate terminal portion, 29 is a resist pattern formed in a contact portion of the gate terminal portion 28, 30 is Al ₂ O ₃ , 31 is a terminal, and 32 is formed in a contact portion on the gate terminal portion 28. A contact hole 33 is a terminal connection wiring for electrically connecting the gate terminal portion 28 and the terminal 31. Note that the same parts as those in FIG.

  Next, a manufacturing method of the TFT array substrate of the storage capacitor on-gate type liquid crystal display device according to the present embodiment will be described. First, as shown in FIG. 10-a, a metal having a small specific resistance such as Al-0.2 at.% Cu is formed on the surface of the transparent insulating substrate 1 by a sputtering method or the like to form a film having a thickness of about 300 nm. A resist is formed by the above, pattern etching is performed using an etchant mainly composed of phosphoric acid, acetic acid, and nitric acid to form the gate wiring 2 having the gate electrode and the gate terminal portion 28, and then the resist is removed. At this time, an etching solution mainly composed of phosphoric acid, acetic acid and nitric acid is used for etching the Al-0.2 at.% Cu film. The composition of phosphoric acid, acetic acid and nitric acid is studied in advance, and Al-0.2 at. By forming the etching end face of the% Cu film in a tapered shape, the coverage of the film formed in the upper layer can be improved.

Next, as shown in FIG. 10B, a metal having a hardness higher than that of Al, such as Cr, is formed to a thickness of about 100 nm by sputtering, the surface is brush-washed, a resist is applied, and Al such as gate wiring 2 is applied. A resist pattern 17 is formed in a shape to be covered with a pattern of -0.2 at.% Cu film, and then the exposed Cr film is removed by etching to form a mask made of a metal film 16 such as a Cr film and the resist pattern 17. Layer 4 is formed. Thereafter, for example, an Al-0.2 at.% Cu film of about 300 nm is immersed in an etching solution containing phosphoric acid, acetic acid and nitric acid as main components for the time required to etch the Al-0.2 at.% Cu film. Etching residue such as a short-circuit portion between patterns is removed. Next, as shown in FIG. 10C, the resist pattern 17 and the metal film 16 constituting the mask layer 4 are removed.

Next, as shown in FIG. 10D, after forming the resist pattern 29 in the contact portion with the upper layer of the gate terminal portion 28, in order to prevent corrosion of the gate wiring 2 and interlayer short circuit with the signal wiring, A portion of the Al-0.2 at.% Cu film not covered with the resist of the gate wiring 2 and the gate terminal portion 28 is anodized to form an Al ₂ O ₃ film 30 on the surface thereof, for example, about 100 nm. At this time, the contact portion on the gate terminal portion 28 is not anodized because it is covered with the resist pattern 29. Next, as shown in FIG. 10E, the resist pattern 29 on the gate terminal portion is removed.

Next, as shown in FIG. 10-f, a silicon nitride film to be the gate insulating film 5 is formed by a plasma CVD method or the like to about 500 nm, an amorphous silicon film is about 200 nm, and an n ⁺ type amorphous silicon film doped with impurities is about After sequentially forming 50 nm, an amorphous silicon film and an n ⁺ -type amorphous silicon film are simultaneously patterned using a resist formed by photolithography, and a semiconductor layer 6 and an ohmic contact layer 7 are formed above the gate wiring 2 To do. Next, as shown in FIG. 11-a, ITO is deposited as a transparent conductive film to a thickness of about 100 nm by sputtering or the like, and then patterned using a resist formed by photolithography, so that the pixel electrode 8 and the terminal 31 are formed. Form. Next, as illustrated in FIG. 11B, the silicon nitride film (gate insulating film 5) serving as a contact portion on the gate terminal portion 28 is removed, and a contact hole 32 is formed.

Next, as shown in FIG. 11C, an n ⁺ type amorphous silicon film constituting the ohmic contact layer 7 in the lowermost layer and Cr, Ti or the like having good ohmic contact properties are about 100 nm, and the intermediate layer has a low specific resistance. -0.2at.% Cu is about 300nm, Cr is harder than Al and about 50nm is continuously formed on the uppermost layer, and brush cleaning is performed after forming the metal film 9 consisting of three layers. Do. Subsequently, as shown in FIG. 11-d, the metal film 9 is patterned using an etching resist formed by a photoengraving method, and a source electrode 10 having source wirings separated into two on the ohmic contact layer 7 and The drain electrode 11 and the terminal connection wiring 33 that electrically connects the gate terminal portion 28 and the terminal 31 are formed. Subsequently, the n ⁺ type amorphous silicon film (ohmic contact layer 9) where the source electrode 10 and the drain electrode 11 are removed is etched by dry etching to form a channel portion, and then the resist is removed. Finally, as shown in FIG. 11E, a silicon nitride film is formed, and the protective film 12 is formed on portions other than on the pixel electrodes 8 and the terminals 31.

The TFT array substrate, which is the first substrate thus formed, and the surface of the counter substrate, which is the second substrate, in which the light shielding layer, the overcoat layer, and the counter electrode are formed on another transparent insulating substrate. A liquid crystal panel is configured by forming an alignment film so as to face each other, injecting liquid crystal therebetween and sealing with a sealing agent, and disposing a polarizing plate outside the opposing array substrate and the opposing substrate.
Although an Al-0.2 at.% Cu film is used as the material for the control electrode wiring (the gate wiring 2 in this embodiment), it is a film that has a small specific resistance and does not cause corrosion and hillocks due to water Alternatively, an Al film or an Al alloy film having another composition may be used.
Further, although a Cr film is used as the metal film 16, other metal films such as a W film may be used as long as they are not eroded by the etching solution for the Al alloy film. Further, as a method for etching the etching residue by the Al alloy film, a dry etching method may be used instead of the wet etching method.
Further, although the metal film 16 and the resist pattern 17 are formed as the mask layer 4, the mask layer 4 may be configured by only the resist pattern 17.

According to the present embodiment, the Al-0.2 at.% Cu film of the Al-0.2 at.% Cu film is formed by anodizing the Al-0.2 at.% Cu film constituting the gate wiring 2 to form Al ₂ O ₃ on the surface. Also in the liquid crystal display device having a structure that prevents corrosion and an interlayer short circuit between the gate wiring 2 and another signal wiring, the same effect as in the fifth embodiment or the sixth embodiment can be obtained.

Embodiment 8 FIG.
12 and 13 are cross-sectional views showing a manufacturing process of a TFT array substrate of a storage capacitor on-gate type liquid crystal display device equipped with a channel etch type TFT according to an eighth embodiment of the present invention. In the figure, reference numeral 34 denotes a groove formed by removing the gate insulating film 5. The same parts as those in FIGS. 10 and 11 are denoted by the same reference numerals, and the description thereof is omitted.

  Next, a manufacturing method of the TFT array substrate of the storage capacitor on-gate type liquid crystal display device according to the present embodiment will be described. First, as shown in FIG. 12-a, a metal having a small specific resistance such as Al-0.2 at.% Cu is formed on the surface of the transparent insulating substrate 1 by a sputtering method or the like to form a film having a thickness of about 300 nm. A resist is formed by the above, pattern etching is performed using an etchant mainly composed of phosphoric acid, acetic acid, and nitric acid to form the gate wiring 2 having the gate electrode and the gate terminal portion 28, and then the resist is removed. At this time, an etching solution mainly composed of phosphoric acid, acetic acid and nitric acid is used for etching the Al-0.2 at.% Cu film. The composition of phosphoric acid, acetic acid and nitric acid is studied in advance, and Al-0.2 at. By forming the etching end face of the% Cu film in a tapered shape, the coverage of the film formed in the upper layer can be improved.

Next, as shown in FIG. 12B, after a resist pattern 29 is formed at a position where the contact portion with the upper layer of the gate terminal portion 28 and the adjacent gate wiring 2 are divided, the corrosion of the gate wiring 2 and the signal In order to prevent an interlayer short circuit with the wiring, the Al-0.2 at.% Cu film of the gate wiring 2 and the gate terminal portion 28 not covered with the resist is anodized, and Al ₂ O _{3 is} formed on the surface thereof. The film 30 is formed with a thickness of about 100 nm, for example. At this time, the contact portion on the gate terminal portion 28 is not anodized because it is covered with the resist pattern 29. Further, even when there is an etching residue of Al-0.2 at.% Cu film between adjacent gate wirings 2 in a pixel, the resist pattern 29 is coated at a position where the gate wirings 2 are divided and anodized. Therefore, this etching residue can be removed in a later step. Next, as shown in FIG. 12C, the resist pattern 29 is removed.

Next, as shown in FIG. 12-d, a silicon nitride film to be the gate insulating film 5 is formed by a plasma CVD method or the like to about 500 nm, an amorphous silicon film is about 200 nm, and an n ⁺ type amorphous silicon film doped with impurities is about After sequentially forming 50 nm, the amorphous silicon film and the n ⁺ -type amorphous silicon film are simultaneously patterned using a resist formed by photolithography, and the semiconductor layer 6 and the ohmic contact layer 7 are formed above the gate wiring 2. To do. Next, as shown in FIG. 12-e, ITO is deposited as a transparent conductive film to a thickness of about 100 nm by sputtering or the like, and then patterned using a resist formed by photolithography to form pixel electrodes 8 and terminals 31. To do. Next, as shown in FIG. 12-f, the contact portion on the gate terminal portion 28 covered with the resist pattern 29 and the silicon nitride film (gate insulating film 5) between the adjacent gate wirings 2 are removed and the contact is removed. A hole 32 and a groove 34 are formed.

Next, as shown in FIG. 13A, an n ⁺ type amorphous silicon film constituting the ohmic contact layer 7 in the lowermost layer and Cr, Ti or the like having good ohmic contact are about 100 nm, and the intermediate layer has a low specific resistance. -0.2at.% Cu is about 300nm, Cr is harder than Al and about 50nm is continuously formed on the uppermost layer, and brush cleaning is performed after forming the metal film 9 consisting of three layers. Do. Subsequently, as shown in FIG. 13B, the metal film 9 is patterned using an etching resist formed by a photoengraving method, and the source electrode 10 having source wirings separated into two on the ohmic contact layer 7 and The drain electrode 11 and the terminal connection wiring 33 that electrically connects the gate terminal portion 28 and the terminal 31 are formed. Subsequently, the n ⁺ type amorphous silicon film (ohmic contact layer 9) where the source electrode 10 and the drain electrode 11 are removed is etched by dry etching to form a channel portion, and then the resist is peeled off. Finally, as shown in FIG. 13C, silicon nitride is formed, and the protective film 12 is formed on portions other than the pixel electrode 8, the terminal 31, and the groove 34. Here, the groove 34 corresponds to the opening 15 provided in the portion where the short-circuit defect is likely to occur as shown in FIG.

  As a result of the above process, a region where etching residue that causes a short circuit between the gate wirings 2 is exposed to the surface by forming the groove 34, and other signal wirings such as the gate wiring 2 are Since it is covered with the gate insulating film 5 and the protective film 12, in this state, an Al-0.2 at.% Cu film of about 300 nm is etched in an etching solution mainly composed of phosphoric acid, acetic acid and nitric acid. Then, the etching residue such as a short-circuit portion between the patterns is removed by the Al-0.2 at.% Cu film. At this time, it is desirable to remove the etching residue in a state where the resist formed for patterning the protective film 12 remains, from the viewpoint of preventing corrosion of the signal wiring.

The TFT array substrate, which is the first substrate thus formed, and the surface of the counter substrate, which is the second substrate, in which the light shielding layer, the overcoat layer, and the counter electrode are formed on another transparent insulating substrate. A liquid crystal panel is configured by forming an alignment film so as to face each other, injecting liquid crystal therebetween and sealing with a sealing agent, and disposing a polarizing plate outside the opposing array substrate and the opposing substrate.
Although an Al-0.2 at.% Cu film is used as the material of the gate wiring 2, an Al film or an Al alloy having another composition may be used as long as it has a small specific resistance and does not cause corrosion and hillocks due to water. It may be a membrane.
According to the present embodiment, the same effect as in the seventh embodiment can be obtained without forming a mask layer for protecting the control electrode wiring (the gate wiring 2 in the present embodiment).

Embodiment 9 FIG.
FIG. 14 is a sectional view showing a manufacturing process of a TFT array substrate of a liquid crystal display device on which a TFT according to Embodiment 9 of the present invention is mounted. In the figure, 35 is a metal film. Note that the same parts as those in FIG.

  Next, a manufacturing method of the TFT array substrate of the liquid crystal display device according to the present embodiment will be described. First, as shown in FIG. 14A, the surface of the transparent insulating substrate 1 is sputtered to form a low resistivity metal such as Al-0.2 at. Such a metal having a hardness higher than that of Al is continuously formed, and after forming a metal film 35 composed of a two-layer film, brush cleaning is performed. Subsequently, as shown in FIG. 14B, a resist is formed by a photoengraving method, and an Mo film and an Al-0.2 at.% Cu film are continuously formed using an etching solution mainly composed of phosphoric acid, acetic acid and nitric acid. Etching is performed to form the gate wiring 2 having the gate electrode and the common wiring 3, and then the resist is removed. At this time, two types of metal films constituting the metal film 35 are formed by using a metal that can be etched at the same time, so that the metal film 35 is etched once and the gate wiring 2 having the gate electrode 2 and the common wiring 3. Can be formed.

An etching solution mainly composed of phosphoric acid, acetic acid and nitric acid is used for etching the Al-0.2 at.% Cu film. The composition of phosphoric acid, acetic acid and nitric acid is studied in advance, and the etching rate of the Mo film is set to Al. -The film formed in the upper layer by increasing the etching rate of the 0.2-at% Cu film and increasing the Mo film side etching amount to form the etching end surface of the Al-0.2 at.% Cu film in a tapered shape. The covering property can be improved. Also, the etching end face of the Al-0.2 at.% Cu film can be obtained by using a dry etching method for etching the metal film 35, adding oxygen to the etching gas, and etching the metal film 35 while oxidizing the resist. It can be formed in a tapered shape.
Further, as shown in FIG. 14C, the Mo film may be removed after the metal film 35 is etched and the resist is removed. Alternatively, the upper layer film of the metal film 35 may be formed by using a refractory metal material having a hardness higher than that of Al and performing an anodic oxidation treatment on the Al-0.2 at.% Cu film. As a result, the coverage of the film formed in the upper layer can be improved by reducing the level difference due to the wiring such as the gate wiring 2. Further, by removing the upper layer film of the metal film 35 constituting the gate wiring 2 and the like, dust or the like adhering to the upper layer film can be removed.

The subsequent steps are the same as those after the formation of the gate insulating film by the plasma CVD method or the like in the first or second embodiment, and a channel etch type liquid crystal display device or a channel protective film type liquid crystal display device is formed. .
Although an Al-0.2 at.% Cu film is used as the material of the gate wiring 2, an Al film or an Al alloy having another composition may be used as long as it has a small specific resistance and does not cause corrosion and hillocks due to water. It may be a membrane.
According to the present embodiment, the same effect as in the first embodiment can be obtained by forming a metal layer having high hardness on the surface of the gate wiring 2 and forming a resist after the brush cleaning and patterning.

Embodiment 10 FIG.
15 is a cross-sectional view showing a manufacturing process of a TFT array substrate of a liquid crystal display device on which a TFT according to Embodiment 9 of the present invention is mounted. The reference numerals in the figure are the same as those in FIG.

  Next, a manufacturing method of the TFT array substrate of the liquid crystal display device according to the present embodiment will be described. First, as shown in FIG. 15A, a metal such as Cr or Ta is formed on the surface of the transparent insulating substrate 1 by a sputtering method or the like, and then a resist is formed by a photoengraving method and etching containing nitric acid is performed. Pattern etching is performed using a liquid to form the gate wiring 2 and the common wiring 3 having gate electrodes, and then the resist is removed. At this time, an etching solution containing nitric acid is used for etching the Cr or Ta film, but the composition of the nitric acid is studied in advance, and the etching end face of the Cr or Ta film is formed into a tapered shape to form a film formed on the upper layer. Coverability can be improved.

  Next, as shown in FIG. 15B, after a resist is applied and a resist pattern 17 is formed in a shape that covers the gate wiring 2 and the common wiring 3 etc., a Cr film or Ta constituting the gate wiring 2 etc. An etching solution for a metal film such as a film is immersed for a time necessary for etching the metal film of about 400 nm to remove etching residues such as a short-circuit portion between patterns due to the metal film. Next, as shown in FIG. 15C, the resist pattern 17 constituting the mask layer 4 is removed.

The subsequent steps are the same as those after the formation of the gate insulating film by the plasma CVD method or the like in the first or second embodiment, and a channel etch type liquid crystal display device or a channel protective film type liquid crystal display device is formed. .
According to the present embodiment, even when the gate wiring 2 is formed of a Cr film or the like, the short-circuit defect between the signal wirings is reliably removed by etching, thereby preventing the short-circuiting between the signal wirings. A high-performance liquid crystal display device can be manufactured with a high yield.

Embodiment 11 FIG.
FIG. 16 is a sectional view showing a manufacturing process of a TFT array substrate of a liquid crystal display device on which a channel etch type TFT according to an eleventh embodiment of the present invention is mounted. The reference numerals in the figure are the same as those in FIGS.

  Next, a manufacturing method of the TFT array substrate of the liquid crystal display device according to the present embodiment will be described. First, as shown in FIG. 16A, after depositing a metal such as Cr or Ta on the surface of the transparent insulating substrate 1 by a sputtering method or the like to a thickness of about 400 nm, a resist is formed by a photoengraving method and etching containing nitric acid is performed. Pattern etching is performed using a liquid to form the gate wiring 2 and the common wiring 3 having gate electrodes, and then the resist is removed. At this time, an etching solution containing nitric acid is used for etching the Cr or Ta film, but the composition of the nitric acid is studied in advance, and the etching end face of the Cr or Ta film is formed into a tapered shape to form a film formed on the upper layer. Coverability can be improved.

Next, as shown in FIG. 16B, a silicon nitride film to be the gate insulating film 5 is about 500 nm, an amorphous silicon film is about 200 nm, and an n ⁺ type amorphous silicon film doped with impurities is about After sequentially forming 50 nm, an amorphous silicon film and an n ⁺ -type amorphous silicon film are simultaneously patterned using a resist formed by photolithography, and a semiconductor layer 6 and an ohmic contact layer 7 are formed above the gate wiring 2 To do. Next, as shown in FIG. 16C, ITO is deposited as a transparent conductive film by about 100 nm by sputtering or the like, and then patterned using a resist formed by photolithography, thereby forming the pixel electrode 8.
Next, as shown in FIG. 16D, the silicon nitride film (gate insulating film 5) formed between the gate wirings 2 is etched so as to divide the adjacent gate wirings 2 to form a groove 34. This etching process of the silicon nitride film is performed simultaneously with the etching of the silicon nitride film for forming a contact hole as a contact portion with the upper layer on the gate terminal portion.

Next, as shown in FIG. 16E, the n ⁺ type amorphous silicon film constituting the ohmic contact layer 7 in the lowermost layer and Cr, Ti or the like having good ohmic contact properties are about 100 nm, and the intermediate layer has a low specific resistance. -0.2at.% Cu is about 300nm, Cr is harder than Al and about 50nm is continuously formed on the uppermost layer, and brush cleaning is performed after forming the metal film 9 consisting of three layers. Do. Subsequently, as shown in FIG. 16-f, the metal film 9 is patterned using an etching resist formed by photolithography, and the source electrode 10 and the drain separated into two on the source wiring and the ohmic contact layer 7 are formed. The electrode 11 is formed. Subsequently, the n ⁺ type amorphous silicon film (ohmic contact layer 9) where the source electrode 10 and the drain electrode 11 are removed is etched by dry etching to form a channel portion, and then the resist is removed. Finally, as shown in FIG. 16G, silicon nitride is formed, and the protective film 12 is formed on portions other than the pixel electrode 8 and the groove 34. Here, the groove 34 corresponds to the opening 15 provided in the portion where the short-circuit defect is likely to occur as shown in FIG.

  As a result of the above process, a region where etching residue that causes a short circuit between the gate wirings 2 is exposed to the surface by forming the groove 34, and other signal wirings such as the gate wiring 2 are Since the gate insulating film 5 and the protective film 12 are covered, in this state, the metal film having a thickness of about 400 nm is etched in the etching solution for the metal film such as the Cr film and the Ta film constituting the gate wiring 2. The substrate is immersed for a necessary time to remove etching residues such as a short-circuit portion between patterns by the metal film. At this time, it is desirable to remove the etching residue in a state where the resist formed for patterning the protective film 12 remains, from the viewpoint of preventing corrosion of the signal wiring.

The TFT array substrate, which is the first substrate thus formed, and the surface of the counter substrate, which is the second substrate, in which the light shielding layer, the overcoat layer, and the counter electrode are formed on another transparent insulating substrate. A liquid crystal panel is configured by forming an alignment film so as to face each other, injecting liquid crystal therebetween and sealing with a sealing agent, and disposing a polarizing plate outside the opposing array substrate and the opposing substrate.
According to the present embodiment, the same effect as in the seventh embodiment can be obtained without forming a mask layer for protecting the control electrode wiring (the gate wiring 2 in the present embodiment).

It is sectional drawing which shows the manufacturing process of the liquid crystal display device by Embodiment 1 of this invention. It is a figure for demonstrating the effect | action of Embodiment 1 of this invention. It is a figure for demonstrating the effect | action of Embodiment 1 of this invention. It is a figure for demonstrating the effect | action of Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the liquid crystal display device by Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing process of the liquid crystal display device by Embodiment 4 of this invention. It is sectional drawing which shows the manufacturing process of the liquid crystal display device by Embodiment 4 of this invention. It is sectional drawing which shows the manufacturing process of the liquid crystal display device by Embodiment 5 of this invention. It is sectional drawing which shows the manufacturing process of the liquid crystal display device by Embodiment 6 of this invention. It is sectional drawing which shows the manufacturing process of the liquid crystal display device by Embodiment 7 of this invention. It is sectional drawing which shows the manufacturing process of the liquid crystal display device by Embodiment 7 of this invention. It is sectional drawing which shows the manufacturing process of the liquid crystal display device by Embodiment 8 of this invention. It is sectional drawing which shows the manufacturing process of the liquid crystal display device by Embodiment 8 of this invention. It is sectional drawing which shows the manufacturing process of the liquid crystal display device by Embodiment 9 of this invention. It is sectional drawing which shows the manufacturing process of the liquid crystal display device by Embodiment 10 of this invention. It is sectional drawing which shows the manufacturing process of the liquid crystal display device by Embodiment 11 of this invention. It is sectional drawing which shows the manufacturing process of this kind of conventional liquid crystal display device.

Explanation of symbols

1 substrate, 2 gate wiring, 3 common wiring, 4 mask layer,
5 gate insulating film, 6 semiconductor layer, 7 ohmic contact layer,
8 pixel electrode, 9 metal film, 10 source electrode, 11 drain electrode,
12 protective film, 13 wiring, 14 short-circuit defect, 15 opening,
16 metal film, 17 resist pattern, 18 channel protective film,
19 semiconductor layer, 20 amorphous silicon film, 21 channel,
22 gate wiring, 23 gate electrode, 24 source / drain region,
25 insulating film, 26 contact hole, 27 auxiliary capacitance wiring,
28 gate terminal portion, 29 resist pattern, 30 Al ₂ O ₃ ,
31 terminals, 32 contact holes, 33 terminal connection wiring, 34 grooves,
35 Metal film.

Claims (12)

A transparent insulating substrate, a control electrode and a control electrode wiring, a semiconductor layer, a first electrode, a first electrode wiring and a second electrode, which constitute a semiconductor element together with the semiconductor layer, and the control electrode and the control electrode A first substrate having an insulating film formed between a wiring and the semiconductor layer, a pixel electrode electrically connected to the second electrode, and a second substrate sandwiching a liquid crystal material together with the first substrate In a method for manufacturing a liquid crystal display device including a substrate,
The control electrode and the control electrode wiring are formed by sequentially forming Al or an Al alloy and a metal having high hardness to form a two-layer film, and after cleaning the surface of the two-layer film with a brush, form a resist. A method of manufacturing a liquid crystal display device, characterized by being formed by a step of etching the two-layer film. 2. The method of manufacturing a liquid crystal display device according to claim 1, wherein the metal film having a high hardness constituting the two-layer film is formed of a metal that can be etched by the same etching solution or etching gas as the Al alloy film. 3. The method of manufacturing a liquid crystal display device according to claim 2, wherein the metal film having a high hardness constituting the two-layer film is formed of a metal having an etching rate higher than that of the Al alloy film. 3. The method of manufacturing a liquid crystal display device according to claim 2, wherein the etching condition of the two-layer film is such that a metal film having a higher hardness than an Al alloy film is etched faster. 3. The method for manufacturing a liquid crystal display device according to claim 2, wherein in the etching process of the two-layer film, a dry etching method is used, and oxygen is included in the etching gas for the dry etching. 6. The liquid crystal display device according to claim 1, wherein the metal film having high hardness constituting the two-layer film is removed after the etching of the two-layer film and the removal of the etching resist. Production method. 7. The liquid crystal according to claim 6, wherein the metal film having a high hardness constituting the two-layer film is formed of a refractory metal, and the removal of the refractory metal film is performed by anodizing treatment of an Al alloy film. Manufacturing method of display device. A transparent insulating substrate, Al or an Al alloy, and a metal with high hardness are sequentially formed to form a two-layer film, and then the surface of this two-layer film is washed with a brush and then a resist is formed to form the two-layer film. Control electrode and control electrode wiring formed by etching, semiconductor layer, first electrode, first electrode wiring and second electrode constituting semiconductor element together with semiconductor layer, control electrode and control A first substrate having an insulating film formed between an electrode wiring and the semiconductor layer, a pixel electrode electrically connected to the second electrode, and a second substrate sandwiching a liquid crystal material together with the first substrate A liquid crystal display device comprising the substrate. A transparent insulating substrate, a control electrode and a control electrode wiring, a semiconductor layer, a first electrode, a first electrode wiring and a second electrode, which constitute a semiconductor element together with the semiconductor layer, and the control electrode and the control electrode A first substrate having an insulating film formed between a wiring and the semiconductor layer, a pixel electrode electrically connected to the second electrode, and a second substrate sandwiching a liquid crystal material together with the first substrate In a method for manufacturing a liquid crystal display device including a substrate,
The first electrode, the second electrode, and the first electrode wiring include a step of forming a metal film having a high hardness on a film made of Al or an Al alloy, and brushing the surface of the metal film having a high hardness. A method of manufacturing a liquid crystal display device, comprising: forming a resist after washing by etching, and etching the multilayer film. A transparent insulating substrate, a control electrode and a control electrode wiring, a semiconductor layer, a first electrode, a first electrode wiring and a second electrode, which constitute a semiconductor element together with the semiconductor layer, and the control electrode and the control electrode A first substrate having wiring, an insulating film formed between the semiconductor layers, a pixel electrode electrically connected to the second electrode, and a second substrate sandwiching a liquid crystal material together with the first substrate The first electrode, the second electrode, and the first electrode wiring are provided with a metal whose outermost surface layer is higher in hardness than Al, and Al or an Al alloy exists in the lower layer. A liquid crystal display device comprising a multilayer film. After forming a metal with high hardness on the transparent insulating substrate, the control electrode and control electrode wiring, the semiconductor layer, and the multilayer film made of Al or Al alloy, the surface of the metal film with high hardness is washed with a brush and then resisted Formed by etching the multilayer film and forming the semiconductor element together with the semiconductor layer, the first electrode wiring and the second electrode, the control electrode and the control electrode wiring A first substrate having an insulating film formed between the semiconductor layers and a pixel electrode electrically connected to the second electrode; a second substrate sandwiching a liquid crystal material together with the first substrate; A liquid crystal display device comprising: 10. The method for manufacturing a liquid crystal display device according to claim 1, wherein the metal having a high hardness is a metal having a hardness that does not cause scratches on the surface of the metal by brush cleaning. .

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