JPS6269670A - Manufacture of substrate for display device - Google Patents

Abstract

PURPOSE:To convert Ta in produced pin-hole parts into TaO and avoid layer short circuit by repeating anode oxidization after the processes such as matching of amorphous Si or formation of contact holes. CONSTITUTION:Ta 12 is deposited on a glass substrate 11 and its surface is subjected to anode oxidization 13 to form an address line 12. Then, after SiO2 14, amorphous Si 15 and N<+> type amorphous Si 16 are deposited by plasma CVD, Mo 17 is deposited on them and an island 15 of amorphous Si is formed by patterning. Then anode oxidization is carried out to convert Ta in pin-hole 20 parts into anode oxide films 20a and 20b and a picture element electrode 17 is formed by sputtering and patterning ITO. After that, anode oxidization is carried out and Al is evaporated to form source, drain and data lines 18. By carrying out anode oxidization after the processing as described above, layer short circuit between the data line and the address line is almost completely eliminated.

Description

[Detailed description of the invention] [Technical field of the invention] [Technical background of the invention and its problems] In recent years, amorphous 8i, Odd, 0dSe, etc. have been used as semiconductors and thin film transistors (TPT) have been used as switching elements. Active matrix type display panels have attracted attention, and such transistor arrays have the advantage of being able to form large-area display devices at low cost because they can be formed using a glass substrate in a low-temperature process. FIG. 4 shows an equivalent circuit of a display panel using a thin film transistor array. (41) ((41+t 6
b ・=4In) is an address line (42) that commonly drives the gate electrodes of 'I'F'Ts (43) in the row direction.
(42i, 42!...62m) are data lines that commonly supply image signals to the TFTs 43 in the column direction.

The TFT 43 is provided corresponding to each pixel provided every 70 points on the address line 41 and the data line 42, and each source electrode is connected to a pixel electrode, and each drain is connected to a data electrode. As the display element, a liquid crystal element, an electroluminescence element, an electrochromic element, etc. are used.

Here, taking a liquid crystal element as an example, address lines (4
1) A drive circuit board on which a capacitance (44) provided between a transistor (43) and an α-mountain is integrated, and a counter substrate on which a transparent electrode is formed on the entire surface facing the cap. It is constructed by sandwiching a liquid crystal layer between them. The capacitance (44) is not required if the OFF resistance of the transistor and the resistance of the liquid crystal are largely large. Such a display panel has the advantage that there is no crosstalk and the data line can be driven at nearly 100%.

By the way, if this type of display panel is to be realized with high definition or large area display, the number of transistors will be extremely large. For example, address 200 x data 200
, 400,000 elements are required. It is difficult to completely manufacture such a large transistor array, and various defects occur. These causes include (1) electrical shorts between multilayer wiring or capacitors;
Possible causes include (2) open wiring, and (3) defective transistors. If a point defect is allowed in a display, it is difficult to repair it in the sheet between multilayer wiring. For example, even if an address line is broken at one point, other pixels will not be affected at all by inputting signals from both directions of the address line.

Furthermore, it is not necessary to provide a capacitance if the OFF resistance of the TPT is increased and the resistivity of the liquid crystal is increased.

As described above, in order to make the display defect-free, it is necessary to remove the gaps between the multilayer interconnections.

The sheet between such multilayer interconnections has a gate insulating film of T
It was reported in Japanese Patent Publication No. 6゜-54478 that this can be prevented by creating a two-layer structure of anodic oxide film and SiO or SiN.
It is stated in I quote it below. Glass substrate (31
) on the gate electrode/address line (32
, ·) and ground line (32) and anodize the surface. Next, after depositing 8i0 (33) 17, a-8i
('34) is deposited and buttered. Next, MO and Al are deposited, and the TPT source electrode/data line (
351) and drain electrode/cano (sita electrode (3St)
+ is formed to complete the drive circuit board. As shown in this proposal, anodizing the surface of the address line is effective, but new pinholes are generated in the subsequent manufacturing process of the display device substrate. for example,
As shown in FIG. 2, 810 and TaO are etched in the lead-out portions of the peripheral address lines to make electrical contact with the address lines. In this process, if there is a tear in the resist pattern at the intersection of the address line and the data line, the underlying Ta will come out. Or S10
The a-81 deposited on the part (2) is usually matched by plasma etching, but at this time, there may be pinholes in the lower layer 810, or there may be scratches, etc. around the edges. If 810, which has a fast etching rate, is deposited and there is a tear in the resist pattern, the underlying TaO is also etched away, exposing the Ta. Since data metal wiring is performed after such a process, a seat with the underlying Ta address line occurs. For this reason, even if the number of interlayer sheets can be reduced to zero by using an anodic oxide film for address lines, shibin holes are generated in subsequent processes, the interlayer sheets reoccur, and display line defects occur. was there.

[Purpose of the invention]

The present invention aims to solve the above problems and eliminate pinholes that occur before data wiring.

[Summary of the invention]

In the present invention, after a-8+ matching, contact hole formation, etc., anodic oxidation is performed again to convert the generated pinholes to TaO, thereby eliminating interlayer shorts.

[Embodiments of the invention]

FIG. 1 shows a cross-sectional view of the embodiment. 2000λ of Ta 03 was deposited on a Corning 7059 glass substrate (1), and the surface was anodized to 100V to form address line 03. Next, 5iOx14 was deposited at 250O
A, a-st a'i 300OA, n+a-8
Deposit 50OA of iQl.

Then, anodic oxide films (20a) and (20b) are formed.

Next, ITO 1500A is sputtered to form a pattern as a pixel electrode Oη. After this, anodic oxidation is performed to 100 μm. Cover the pad part with resist and then
A and l are deposited to a thickness of 1 μm to form north, drain, and data lines Q8. n10a-8+ in the channel portion is removed by chemical dry matching to produce a display substrate. By performing post-process anodic oxidation in this manner, the number of sheets between the data line and address line layers can be reduced to almost zero. On the other hand, when no anodic oxidation was performed after the process, approximately 5 lines of address lines were flush with data lines.

The address line is not limited to Ta, but T1. A1 etc. is also fine.

The interlayer insulating film is not limited to SiOx, but also Alt On v S.
iNx is also fine. It is good that there is no metal on the island of BS+, but All, Ti, Zr, Or, W
, a metal that is easily anodized such as Ta or Au,
Metals that are difficult to be anodized, such as Ir, Pt, Rh, and Pd, may also be used.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing a conventional example of a display device substrate, and FIG. 4 is an equivalent circuit diagram of a thin film transistor array of a display device substrate. It is. 1)...Glass substrate, 12...Ta gate, 13...
...TaOx, 14-SiOx, 15 =
a--8i, 16-n tena-8i, 17-M
o1) 8--pinhole, 19-source, drain,
Data lines A, l, 20a, 20b... anodic oxide film.

Claims (3)

[Claims] (1) An address line and gate electrode pattern provided on one main surface of an insulating substrate, an anodic oxide film provided on the surfaces of the address line and gate electrode, and an interlayer insulating film covering the address line and gate electrode. When manufacturing a display device substrate comprising a thin film semiconductor pattern formed on the interlayer insulating film and a source electrode and drain electrode pattern extending from a part of the thin film semiconductor pattern, the thin film semiconductor pattern 1. A method for manufacturing a display device substrate, characterized in that the address line and the gate electrode are anodized from the semiconductor surface after the formation of the source and drain electrodes and before the formation of the source and drain electrodes. (2) A method for manufacturing a display device substrate according to claim 1, characterized in that a protective metal thin film is provided on the thin film semiconductor pattern. (3) Protective metal thin film is Mo, Al, Ti, Zr, Cr
, W, Ta, Au, Ir, Pt, Rh, or Pd.