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JP2006086359A - Multilayer ceramic capacitor - Google Patents

Multilayer ceramic capacitor Download PDF

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JP2006086359A
JP2006086359A JP2004270044A JP2004270044A JP2006086359A JP 2006086359 A JP2006086359 A JP 2006086359A JP 2004270044 A JP2004270044 A JP 2004270044A JP 2004270044 A JP2004270044 A JP 2004270044A JP 2006086359 A JP2006086359 A JP 2006086359A
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ceramic capacitor
multilayer ceramic
multilayer
internal electrode
electrode
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Satoshi Kazama
智 風間
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Taiyo Yuden Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer ceramic capacitor having superior heat dissipation capacity. <P>SOLUTION: The multilayer ceramic capacitor includes a parallelopiped multilayer chip 11, on which two first internal electrodes 12 present in the same layer and a common internal electrode 13 present in a layer different from the layer with the first electrodes 12 present are provided alternately via a ceramic layer (not numbered) and facing each other; two first external electrodes 14 provided on both sides of the lower surface of the multilayer chip 11 and one second external electrode 15 provided at the center of the lower surface without contacting the first external electrodes 14; and a heat-dissipating conductor 16 provided on the upper surface of the multilayer chip 11 and connecting to the upper edge of the common internal electrode 13. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、積層チップ内に複数の内部電極を対向して備える積層セラミックコンデンサに関する。   The present invention relates to a multilayer ceramic capacitor having a plurality of internal electrodes facing each other in a multilayer chip.

図1〜図3は特開平11−288838号公報に開示された従来の積層セラミックコンデンサを示す。図1は積層セラミックコンデンサの斜視図、図2は図1のa1−a1線断面図、図3は図1のa2−a2線断面図である。   1 to 3 show a conventional multilayer ceramic capacitor disclosed in JP-A-11-288838. 1 is a perspective view of the multilayer ceramic capacitor, FIG. 2 is a sectional view taken along line a1-a1 in FIG. 1, and FIG. 3 is a sectional view taken along line a2-a2 in FIG.

この積層セラミックコンデンサは、直方体形状を成すセラミック素子内に複数の内部電極1がセラミック層2を介して対向するように配されている。複数の内部電極1は平面形状が長方形状を成していて、各内部電極1の長さ方向の端縁はセラミック素子の長さ方向の一方の面3aと他方の面3bに交互に引き出されている。面3aに引き出された一部の内部電極1の端縁は一方の外部電極4aに接続され、且つ、面3bに引き出された残りの内部電極1の端縁は他方の外部電極4bに接続されている。   The multilayer ceramic capacitor is arranged such that a plurality of internal electrodes 1 are opposed to each other with a ceramic layer 2 in a ceramic element having a rectangular parallelepiped shape. The plurality of internal electrodes 1 have a rectangular planar shape, and the lengthwise edges of the internal electrodes 1 are alternately drawn out to one surface 3a and the other surface 3b in the length direction of the ceramic element. ing. An edge of a part of the internal electrode 1 drawn to the surface 3a is connected to one external electrode 4a, and an edge of the remaining internal electrode 1 drawn to the surface 3b is connected to the other external electrode 4b. ing.

また、隣接する内部電極1間のセラミック層2それぞれには放熱用内部電極5が内部電極1と非接触で配されている。複数の放熱用内部電極5は平面形状が十字形状を成していて、各放熱用内部電極5の幅方向の端縁はセラミック素子の幅方向の一方の面6aと他方の面6bに引き出されている。面6aに引き出された全ての放熱用内部電極5の端縁は一方の放熱用外部電極7aに接続され、且つ、面6bに引き出された全ての放熱用内部電極5の端縁は他方の放熱用外部電極7bに接続されている。   Further, each of the ceramic layers 2 between the adjacent internal electrodes 1 is provided with a heat radiating internal electrode 5 in a non-contact manner with the internal electrode 1. The plurality of internal electrodes 5 for heat dissipation have a cross shape in plan, and the edges in the width direction of the internal electrodes 5 for heat dissipation are drawn out to one surface 6a and the other surface 6b in the width direction of the ceramic element. ing. The edges of all the heat dissipating internal electrodes 5 drawn to the surface 6a are connected to one heat dissipating external electrode 7a, and the edges of all the heat dissipating internal electrodes 5 drawn to the face 6b are the other heat dissipating elements. Connected to the external electrode 7b.

この積層セラミックコンデンサでは、セラミック素子内の内部電極1間それぞれに放熱用内部電極5を非接触で配し、この複数の放熱用内部電極5を放熱用外部電極7a,7bに接続することにより、コンデンサ自体の熱を放熱用内部電極5及び放熱用外部電極7a,7bを利用して外部に放出するようにしている。
特開平11−288838号公報
In this multilayer ceramic capacitor, by disposing the heat dissipating internal electrodes 5 between the internal electrodes 1 in the ceramic element in a non-contact manner, and connecting the plurality of heat dissipating internal electrodes 5 to the heat dissipating external electrodes 7a and 7b, The heat of the capacitor itself is released to the outside using the internal electrode 5 for heat dissipation and the external electrodes 7a and 7b for heat dissipation.
Japanese Patent Laid-Open No. 11-288838

ところで、積層セラミックコンデンサの温度上昇は、主として、電圧印加時に内部電極1で発生する熱と、実装基板から外部電極4a,4bを通じて内部電極1等に伝わる熱に依存する。   Incidentally, the temperature rise of the multilayer ceramic capacitor mainly depends on the heat generated in the internal electrode 1 when a voltage is applied and the heat transmitted from the mounting substrate to the internal electrode 1 through the external electrodes 4a and 4b.

前記の積層セラミックコンデンサでは、セラミック素子内の内部電極1間それぞれに非接触で配された放熱用内部電極5とこの複数の放熱用内部電極5に接続された放熱用外部電極7a,7bを利用して放熱を行うようにしているが、内部電極1と放熱用内部電極5との間それぞれにセラミック層2が存在するため、このセラミック層2が内部電極1から放熱用内部電極5への伝熱の妨げとなってしまう。   The multilayer ceramic capacitor uses a heat dissipating internal electrode 5 disposed in a non-contact manner between the internal electrodes 1 in the ceramic element and heat dissipating external electrodes 7a and 7b connected to the plurality of heat dissipating internal electrodes 5. However, since the ceramic layer 2 exists between the internal electrode 1 and the internal heat radiation electrode 5, the ceramic layer 2 is transferred from the internal electrode 1 to the internal heat radiation electrode 5. It becomes an obstacle to heat.

つまり、セラミック層2は内部電極1等の導体に比べて伝熱性が遥かに劣る絶縁材であることから、内部電極1の熱を放熱用内部電極5に効率良く伝えることが難しく、結果的に所期の放熱が行えずに積層セラミックコンデンサの温度上昇を抑制することが難しい。   That is, since the ceramic layer 2 is an insulating material whose heat conductivity is far lower than that of the conductor such as the internal electrode 1, it is difficult to efficiently transfer the heat of the internal electrode 1 to the internal electrode 5 for heat dissipation. It is difficult to suppress the temperature rise of the multilayer ceramic capacitor without performing the desired heat dissipation.

本発明は前記事情に鑑みて創作されたもので、その目的とするところは、放熱能力に優れた積層セラミックコンデンサを提供することにある。   The present invention was created in view of the above circumstances, and an object of the present invention is to provide a multilayer ceramic capacitor excellent in heat dissipation capability.

前記目的を達成するため、本発明に係る積層セラミックコンデンサは、同一層に存する2以上の第1内部電極と、第1内部電極が存する層とは異なる層に存する共通内部電極とが、セラミック層を介して交互に、且つ、対向して配された直方体形状の積層チップと、積層チップの1つの面に設けられ、各第1内部電極と導通する2以上の第1外部電極と、積層チップの前記1つの面に第1外部電極と非接触で設けられ、共通内部電極と導通する少なくとも1つの第2外部電極と、積層チップの前記1つの面とは異なる少なくとも1つの面に設けられ、2以上の第1内部電極の少なくとも1つ、または、共通内部電極と導通する少なくとも1つの放熱導体部とを備える、ことをその特徴とする。   In order to achieve the above object, a multilayer ceramic capacitor according to the present invention includes a ceramic layer in which two or more first internal electrodes in the same layer and a common internal electrode in a layer different from the layer in which the first internal electrode exists are formed. A rectangular parallelepiped laminated chip arranged alternately and oppositely via each other, two or more first external electrodes provided on one surface of the laminated chip and electrically connected to each first internal electrode, and a laminated chip The at least one second external electrode that is provided in contact with the first external electrode and is in contact with the common internal electrode, and is provided on at least one surface different from the one surface of the multilayer chip, It is characterized by comprising at least one of two or more first internal electrodes, or at least one heat radiating conductor portion conducting with the common internal electrode.

また、本発明に係る積層セラミックコンデンサは、同一層に存する2以上の第1内部電極と、第1内部電極が存する層とは異なる層に存する2以上の第2内部電極とが、セラミック層を介して交互に、且つ、対向して配された直方体形状の積層チップと、積層チップの1つの面に設けられ、各第1内部電極と導通する2以上の第1外部電極と、積層チップの1つの面に第1外部電極と非接触で設けられ、各第2内部電極と導通する2以上の第2外部電極と、積層チップの前記1つの面とは異なる少なくとも1つの面に設けられ、2以上の第1内部電極の少なくとも1つ、または、2以上の第2内部電極の少なくとも1つと導通する少なくとも1つの放熱導体部とを備える、ことをその特徴とする。   In the multilayer ceramic capacitor according to the present invention, two or more first internal electrodes existing in the same layer and two or more second internal electrodes existing in a layer different from the layer where the first internal electrode exists include a ceramic layer. A rectangular parallelepiped laminated chip arranged alternately and opposed to each other, two or more first external electrodes provided on one surface of the laminated chip and electrically connected to each first internal electrode, and the laminated chip Two or more second external electrodes which are provided in contact with the first external electrode on one surface and are electrically connected to each second internal electrode, and are provided on at least one surface different from the one surface of the multilayer chip; It is characterized by comprising at least one of the two or more first internal electrodes or at least one heat radiating conductor portion that conducts with at least one of the two or more second internal electrodes.

前記の積層セラミックコンデンサによれば、実装後の積層セラミックコンデンサへの電圧印加時に各内部電極で熱が発生すると、また、実装基板からの熱が各外部電極を通じて各内部電極に伝わると、この熱は第1内部電極の少なくとも一方または共通内部電極、或いは、第1内部電極の少なくとも一方または第2内部電極の少なくとも一方から放熱導体部に直接的に伝わって該放熱導体部から外部に放出されることになる。要するに、積層セラミックコンデンサの熱を直接的に、且つ、高効率で放熱導体部に伝えて、コンデンサ自体の熱を効果的に外部に放出してその温度上昇を抑制することができる。   According to the multilayer ceramic capacitor, when heat is generated in each internal electrode when a voltage is applied to the multilayer ceramic capacitor after mounting, and when heat from the mounting substrate is transmitted to each internal electrode through each external electrode, this heat is generated. Is directly transmitted from at least one of the first internal electrodes or the common internal electrode, or at least one of the first internal electrodes, or at least one of the second internal electrodes to the heat radiating conductor, and is discharged to the outside from the heat radiating conductor. It will be. In short, the heat of the multilayer ceramic capacitor can be directly and efficiently transmitted to the heat dissipating conductor portion, and the heat of the capacitor itself can be effectively released to the outside to suppress the temperature rise.

本発明によれば、放熱能力に優れた積層セラミックコンデンサを提供できる。   ADVANTAGE OF THE INVENTION According to this invention, the laminated ceramic capacitor excellent in the heat dissipation capability can be provided.

本発明の前記目的とそれ以外の目的と、構成特徴と、作用効果は、以下の説明と添付図面によって明らかとなる。   The above object and other objects, structural features, and operational effects of the present invention will become apparent from the following description and the accompanying drawings.

[第1実施形態]
図4〜図9は本発明の第1実施形態を示す。図4は積層セラミックコンデンサの上面側から見た斜視図、図5は積層セラミックコンデンサの下面側から見た斜視図、図6(A)及び図6(B)は図4に示した積層セラミックコンデンサをy−y方向と平行で位置が異なる2つのラインで切断した縦断面図、図7(A)及び図7(B)は図4に示した積層コンデンサをx−x方向と平行で位置が異なる2つのラインで切断した縦断面図、図8(A)〜図8(C)と図9(A)及び図9(B)は図4に示した積層セラミックコンデンサの製法説明図である。
[First Embodiment]
4 to 9 show a first embodiment of the present invention. 4 is a perspective view as seen from the upper surface side of the multilayer ceramic capacitor, FIG. 5 is a perspective view as seen from the lower surface side of the multilayer ceramic capacitor, and FIGS. 6 (A) and 6 (B) are the multilayer ceramic capacitor shown in FIG. FIG. 7A and FIG. 7B show the multilayer capacitor shown in FIG. 4 parallel to the xx direction and at a position parallel to the xy direction. FIG. 8 (A) to FIG. 8 (C), FIG. 9 (A), and FIG. 9 (B) are longitudinal sectional views cut along two different lines, and are explanatory diagrams of a method for manufacturing the multilayer ceramic capacitor shown in FIG.

第1実施形態の積層セラミックコンデンサ10は、直方体形状を成す積層チップ11を備える。この積層チップ11は、同一層に存する2つの第1内部電極12と、第1内部電極12が存する層とは異なる層に存する共通内部電極13とが、セラミック層(符号無し)を介して交互に、且つ、対向して配された構成を有する。図面には第1内部電極12が存する層と共通内部電極13が存する層を6つずつ交互に積層したものを示してあるが、両者の層数は必要とする静電容量に応じて任意に設定される。   The multilayer ceramic capacitor 10 of the first embodiment includes a multilayer chip 11 having a rectangular parallelepiped shape. In this multilayer chip 11, two first internal electrodes 12 existing in the same layer and a common internal electrode 13 existing in a layer different from the layer where the first internal electrode 12 exists are alternately arranged via a ceramic layer (not indicated). Moreover, it has the structure arranged oppositely. In the drawing, six layers each including the first internal electrode 12 and six layers including the common internal electrode 13 are alternately stacked. The number of both layers is arbitrarily determined according to the required capacitance. Is set.

図6(A)に示すように、同一層に存する2つの第1内部電極12はそれぞれ縦長長方形を成し、両者間には所定の間隙が設けられている。各第1内部電極12はその下端一側に所定幅の引出部12aを有し、該引出部12aの下縁は積層チップ11の下面に露出している。また、各第1内部電極12の上縁及び側縁は積層チップ11の上面及びy−y方向の1側面から離れた内側位置にある。   As shown in FIG. 6A, the two first internal electrodes 12 existing in the same layer each have a vertically long rectangle, and a predetermined gap is provided between them. Each first internal electrode 12 has a lead portion 12 a having a predetermined width on one lower end side, and the lower edge of the lead portion 12 a is exposed on the lower surface of the multilayer chip 11. In addition, the upper edge and the side edge of each first internal electrode 12 are at inner positions away from the upper surface of the multilayer chip 11 and one side surface in the yy direction.

図6(B)に示すように、共通内部電極13は2つの第1内部電極12と向き合うに十分な大きさを有する横長長方形を成す。共通内部電極13はその下端中央に所定幅の引出部13aを有し、該引出部13aの下縁は積層チップ11の下面に引出部12aと非接触で露出している。また、共通内部電極13の上縁は積層チップ11の上面に露出しており、両側縁は積層チップ11のy−y方向の2側面から離れた内側位置にある。   As shown in FIG. 6B, the common internal electrode 13 forms a horizontally long rectangle having a size sufficient to face the two first internal electrodes 12. The common internal electrode 13 has a lead portion 13 a having a predetermined width at the center of the lower end thereof, and the lower edge of the lead portion 13 a is exposed on the lower surface of the laminated chip 11 in a non-contact manner with the lead portion 12 a. Further, the upper edge of the common internal electrode 13 is exposed on the upper surface of the multilayer chip 11, and both side edges are at inner positions away from the two side surfaces of the multilayer chip 11 in the yy direction.

積層チップ11の下面両側には第1外部電極14がx−x方向に帯状に設けられ、下面中央には2つの第1外部電極14と非接触で第2外部電極15がx−x方向に帯状に設けられている。図6(A)及び図7(A)から分かるように一方の第1内部電極12の引出部12aの下縁は一方の第1外部電極14に接続し、他方の第1内部電極12の引出部12aの下縁は他方の第1外部電極14に接続している。図6(B)及び図7(B)から分かるように共通内部電極13の引出部13aの下縁は第2外部電極15に接続している。   The first external electrodes 14 are provided in a strip shape in the xx direction on both sides of the lower surface of the multilayer chip 11, and the second external electrodes 15 are not in contact with the two first external electrodes 14 in the center of the lower surface in the xx direction. It is provided in a band shape. 6A and 7A, the lower edge of the lead portion 12a of one first internal electrode 12 is connected to one first external electrode 14 and the other first internal electrode 12 is drawn. The lower edge of the portion 12 a is connected to the other first external electrode 14. As can be seen from FIGS. 6B and 7B, the lower edge of the lead-out portion 13 a of the common internal electrode 13 is connected to the second external electrode 15.

また、積層チップ11の上面には該上面全体を覆うように放熱導体部16が設けられている。図6(B),図7(A)及び図7(B)から分かるように共通内部電極13の上縁は放熱導体部16に接続している。   Further, a heat radiating conductor 16 is provided on the upper surface of the multilayer chip 11 so as to cover the entire upper surface. As can be seen from FIGS. 6B, 7 </ b> A, and 7 </ b> B, the upper edge of the common internal electrode 13 is connected to the heat radiating conductor 16.

前記積層セラミックコンデンサ10を製造するに際しては、まず、チタン酸バリウム等の誘電体粉末を含有した未焼成セラミックシートの一面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して第1内部電極12用の未焼成内部電極C11を形成した第1シートS11(図8(A)参照)と、未焼成セラミックシートの一面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して共通内部電極13用の未焼成内部電極C12を形成した第2シートS12(図8(B)参照)とを交互に所定枚数積み重ねて、未焼成内部電極を形成していない未焼成セラミックシートから成るダミーシートS13(図8(C)参照)をその両側に重ね合わせて全体を熱圧着し、これを焼成する。図8には1部品に対応した大きさの未焼成セラミックシートを示したが、実際上は多数個取りを可能とした大きさの未焼成セラミックシートを用いて積層圧着後にこれを部品寸法に切断して焼成することで積層チップ11を得る。   When the multilayer ceramic capacitor 10 is manufactured, first, a conductor paste containing metal powder such as silver or nickel is printed on one surface of an unfired ceramic sheet containing dielectric powder such as barium titanate. The first sheet S11 (see FIG. 8A) on which the unfired internal electrode C11 for the electrode 12 is formed and the conductor paste containing metal powder such as silver or nickel printed on one surface of the unfired ceramic sheet A dummy made of unfired ceramic sheets in which unfired internal electrodes are not formed by alternately stacking a predetermined number of second sheets S12 (see FIG. 8B) on which unfired internal electrodes C12 for internal electrodes 13 are formed. A sheet S13 (see FIG. 8C) is superposed on both sides, and the whole is thermocompression bonded and fired. FIG. 8 shows an unfired ceramic sheet of a size corresponding to one part. In practice, however, an unfired ceramic sheet of a size that can be picked up in large numbers is used, and this is cut into component dimensions after laminating and pressing. Then, the multilayer chip 11 is obtained by firing.

次に、焼成により得られた積層チップ11の上面(図9(A)参照)に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して未焼成放熱導体部(図示省略)を形成し、且つ、積層チップ11の下面(図9(B)参照)に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して2つの未焼成第1外部電極(図示省略)と1つの未焼成第2外部電極(図示省略)を形成し、これらに焼き付け処理を施す。勿論、未焼成放熱導体部,未焼成第1外部電極及び未焼成第2外部電極の焼き付け処理は積層チップの焼成処理と同時に行うこともできる。   Next, a conductor paste containing metal powder such as silver or nickel is printed on the upper surface (see FIG. 9A) of the laminated chip 11 obtained by firing to form an unfired heat radiating conductor (not shown). In addition, a conductive paste containing a metal powder such as silver or nickel is printed on the lower surface of the multilayer chip 11 (see FIG. 9B), and two unfired first external electrodes (not shown) and one unfired Second external electrodes (not shown) are formed and subjected to a baking process. Of course, the baking process of the unsintered heat radiation conductor part, the unsintered first external electrode and the unsintered second external electrode can be performed simultaneously with the firing process of the laminated chip.

第1実施形態の積層セラミックコンデンサ10は、一方の第1外部電極14と第2外部電極15との間に一方の第1内部電極12と共通内部電極13の一部との対向面積及び積層数に準じた所定の静電容量を得ることができ、他方の第1外部電極14と第2外部電極15との間に他方の第1内部電極12と共通内部電極13の一部との対向面積及び積層数に準じた所定の静電容量を得ることができる。また、2つの第1外部電極14と共通内部電極13との間に2つの第1内部電極12と共通内部電極13との対向面積及び積層数に準じた所定の静電容量を得ることができる。つまり、2つの第1外部電極14と1つの第2外部電極15との接続形態に応じて、積層セラミックコンデンサ10を2つのコンデンサが組み合わされたコンデンサアレイ、または、単独のコンデンサとして使用することができる。   In the multilayer ceramic capacitor 10 of the first embodiment, the facing area and the number of stacked layers between one first internal electrode 12 and a part of the common internal electrode 13 between one first external electrode 14 and the second external electrode 15. A predetermined capacitance according to the above can be obtained, and the opposing area of the other first internal electrode 12 and a part of the common internal electrode 13 between the other first external electrode 14 and the second external electrode 15. In addition, a predetermined capacitance according to the number of layers can be obtained. In addition, a predetermined capacitance according to the facing area and the number of stacked layers between the two first internal electrodes 12 and the common internal electrode 13 can be obtained between the two first external electrodes 14 and the common internal electrode 13. . That is, the multilayer ceramic capacitor 10 may be used as a capacitor array in which two capacitors are combined or as a single capacitor depending on the connection form between the two first external electrodes 14 and the one second external electrode 15. it can.

この積層セラミックコンデンサ10にあっては、2つの第1内部電極12と共通内部電極13との間に不要な導体層が存しないため、つまり、図1〜図3に示した従来の積層セラミックコンデンサのように隣接する内部電極1間それぞれに内部電極1とは別の放熱用内部電極5が存しないため、一方の第1外部電極14と第2外部電極15との間、他方の第1外部電極14と第2外部電極15との間、さらには、2つの第1外部電極14と第2外部電極15との間に、所期の静電容量を安定して確保することができる。   In this multilayer ceramic capacitor 10, an unnecessary conductor layer does not exist between the two first internal electrodes 12 and the common internal electrode 13, that is, the conventional multilayer ceramic capacitor shown in FIGS. Thus, there is no heat dissipating internal electrode 5 different from the internal electrode 1 between the adjacent internal electrodes 1, so that between the first external electrode 14 and the second external electrode 15, the other first external electrode A desired electrostatic capacity can be stably ensured between the electrode 14 and the second external electrode 15 and between the two first external electrodes 14 and the second external electrode 15.

また、この積層セラミックコンデンサ10にあっては、実装後の積層セラミックコンデンサ10への電圧印加時に各内部電極12,13で熱が発生すると、また、実装基板からの熱が各外部電極14,15から各内部電極12,13に伝わると、この熱は共通内部電極13から放熱導体部16に直接的に伝わって該放熱導体部16から外部に放出される。要するに、積層セラミックコンデンサ10を熱を直接的に、且つ、高効率で放熱導体部16に伝えることにより、コンデンサ自体の熱を効果的に外部に放出してその温度上昇を確実に抑制することができる。しかも、放熱導体部16に十分な面積が確保できるので前記の熱放出をより効果的に行うことができる。   In the multilayer ceramic capacitor 10, when heat is generated in the internal electrodes 12 and 13 when a voltage is applied to the multilayer ceramic capacitor 10 after mounting, the heat from the mounting substrate is also transferred to the external electrodes 14 and 15. Is transmitted from the common internal electrode 13 directly to the heat radiating conductor 16 and is released to the outside from the heat radiating conductor 16. In short, by transferring heat to the multilayer ceramic capacitor 10 directly and with high efficiency to the heat radiating conductor portion 16, it is possible to effectively release the heat of the capacitor itself to the outside and reliably suppress the temperature rise. it can. In addition, since a sufficient area can be secured in the heat radiating conductor portion 16, the heat release can be performed more effectively.

尚、図1〜図9には同一層に2つの第1内部電極12を設けたものを示したが、同一層に3以上の第1内部電極を設け、これらに対向する大きさを有する共通内部電極を設ければ、3以上のコンデンサが組み合わされたコンデンサアレイ(単独のコンデンサとしても使用可能)として構成することもできる。第1内部電極を3以上設ける場合には第1内部電極の数に応じて外部電極の数は増加することになる。   1 to 9 show two first internal electrodes 12 provided in the same layer, but three or more first internal electrodes are provided in the same layer and have a size opposite to these. If an internal electrode is provided, a capacitor array in which three or more capacitors are combined (can be used as a single capacitor) can also be configured. When three or more first internal electrodes are provided, the number of external electrodes increases according to the number of first internal electrodes.

また、外部電極の数は必ずしも第1内部電極の数+1とする必要はなく、例えば図10に示した積層セラミックコンデンサ10’のように各第1内部電極12’の下端中央に引出部12aを設け、共通内部電極13’の下端中央と下端両側に計3個の引出部13aを設けた構成を採用すれば、外部電極の数を任意に増加させることも可能である。   The number of external electrodes is not necessarily the number of first internal electrodes + 1. For example, a lead-out portion 12a is provided at the center of the lower end of each first internal electrode 12 ′ as in the multilayer ceramic capacitor 10 ′ shown in FIG. The number of external electrodes can be increased arbitrarily by adopting a configuration in which a total of three lead portions 13a are provided at the center of the lower end of the common internal electrode 13 ′ and both sides of the lower end.

以下に、前記第1実施形態の構造変形例を図11〜図17を引用して説明する。   Hereinafter, structural modifications of the first embodiment will be described with reference to FIGS.

図11〜図12は第1構造変形例を示すもので、この積層セラミックコンデンサ10−1が前記積層セラミックコンデンサ10と異なるところは、2つの放熱導体部16−1を積層チップ11のy−y方向の2側面にそれぞれ設けると共に、共通内部電極13−1としてその両側縁が積層チップ11のy−y方向の2側面に露出し、且つ、その上縁が積層チップ11の上面から離れた内側位置にあるものを採用して、該共通内部電極13−1の両側縁を放熱導体部17−1にそれぞれ接続した点にある。製法及び機能は前記積層セラミックコンデンサ10と同様である。   FIGS. 11 to 12 show a first structural modification example. The multilayer ceramic capacitor 10-1 is different from the multilayer ceramic capacitor 10 in that two heat radiating conductor portions 16-1 are connected to the y-y of the multilayer chip 11. FIG. Are provided on two side surfaces in the direction, and both side edges of the common internal electrode 13-1 are exposed on the two side surfaces in the yy direction of the laminated chip 11, and the upper edge is an inner side away from the upper surface of the laminated chip 11. It is in the point which employ | adopted the thing in position and connected both the side edges of this common internal electrode 13-1 to the thermal radiation conductor part 17-1. The manufacturing method and function are the same as those of the multilayer ceramic capacitor 10.

この積層セラミックコンデンサ10−1によれば、積層セラミックコンデンサ10−1の熱を直接的に、且つ、高効率で放熱導体部16−1に伝えることにより、前記積層セラミックコンデンサ10と同様の放熱効果を得ることができる。この場合の放熱導体部は、積層チップ11のy−y方向の2側面とx−x方向の1側面に連続して、または、積層チップ11のy−y方向の2側面とx−x方向の2側面に連続して設けられていてもよい。   According to the multilayer ceramic capacitor 10-1, the heat dissipation effect similar to that of the multilayer ceramic capacitor 10 can be obtained by directly and efficiently transmitting the heat of the multilayer ceramic capacitor 10-1 to the heat radiating conductor 16-1. Can be obtained. In this case, the heat radiating conductor portion is continuous with the two side surfaces in the y-y direction and one side surface in the xx direction of the multilayer chip 11 or the two side surfaces in the yy direction of the multilayer chip 11 and the xx direction. It may be provided continuously on the two side surfaces.

図13〜図14は第2構造変形例を示すもので、この積層セラミックコンデンサ10−2が前記積層セラミックコンデンサ10と異なるところは、放熱導体部16−2を積層チップ11の上面とy−y方向の2側面に連続して設けた点にある。製法及び機能は前記積層セラミックコンデンサ10と同様である。   FIGS. 13 to 14 show a second structural modification example. This multilayer ceramic capacitor 10-2 is different from the multilayer ceramic capacitor 10 in that the radiating conductor portion 16-2 is connected to the upper surface of the multilayer chip 11 and yy. It is in the point provided continuously on the two side surfaces of the direction. The manufacturing method and function are the same as those of the multilayer ceramic capacitor 10.

この積層セラミックコンデンサ10−2によれば、積層セラミックコンデンサ10−2の熱を直接的に、且つ、高効率で放熱導体部16−2に伝えることにより、前記積層セラミックコンデンサ10と同様の放熱効果を得ることができる。この場合の放熱導体部は、積層チップ11の上面とy−y方向の2側面とx−x方向の1側面に連続して、または、積層チップ11の上面とy−y方向の2側面とx−x方向の2側面に連続して設けられていてもよい。   According to the multilayer ceramic capacitor 10-2, the heat dissipation effect similar to that of the multilayer ceramic capacitor 10 can be obtained by directly and efficiently transmitting the heat of the multilayer ceramic capacitor 10-2 to the heat radiating conductor 16-2. Can be obtained. In this case, the heat radiating conductor portion is continuous with the upper surface of the multilayer chip 11, the two side surfaces in the yy direction, and the one side surface in the xx direction, or the upper surface of the multilayer chip 11 and the two side surfaces in the yy direction. It may be provided continuously on the two side surfaces in the xx direction.

図15は第3構造変形例を示すもので、この積層セラミックコンデンサ10−3が前記積層セラミックコンデンサ10と異なるところは、放熱導体部16−2を積層チップ11の上面とy−y方向の2側面に連続して設けると共に、共通内部電極13−1としてその両側縁が積層チップ11のy−y方向の2側面に露出し、且つ、その上縁が積層チップ11の上面から離れた内側位置にあるものを採用して、該共通内部電極13−1の両側縁を放熱導体部16−2にそれぞれ接続した点にある。製法及び機能は前記積層セラミックコンデンサ10と同様である。   FIG. 15 shows a third structural modification example. This multilayer ceramic capacitor 10-3 is different from the multilayer ceramic capacitor 10 in that the heat dissipating conductor 16-2 is connected to the top surface of the multilayer chip 11 in the yy direction. An inner position where both side edges of the common internal electrode 13-1 are exposed on the two side surfaces in the yy direction of the multilayer chip 11 and the upper edge is away from the upper surface of the multilayer chip 11. And the both side edges of the common internal electrode 13-1 are respectively connected to the heat radiating conductor 16-2. The manufacturing method and function are the same as those of the multilayer ceramic capacitor 10.

この積層セラミックコンデンサ10−3によれば、積層セラミックコンデンサ10−3の熱を直接的に、且つ、高効率で放熱導体部16−2に伝えることにより、前記積層セラミックコンデンサ10と同様の放熱効果を得ることができる。この場合の放熱導体部は、積層チップ11の上面とy−y方向の2側面とx−x方向の1側面に連続して、または、積層チップ11の上面とy−y方向の2側面とx−x方向の2側面に連続して設けられていてもよい。   According to the multilayer ceramic capacitor 10-3, the heat dissipation effect similar to that of the multilayer ceramic capacitor 10 can be obtained by directly and efficiently transmitting the heat of the multilayer ceramic capacitor 10-3 to the heat radiating conductor 16-2. Can be obtained. In this case, the heat radiating conductor portion is continuous with the upper surface of the multilayer chip 11, the two side surfaces in the yy direction, and the one side surface in the xx direction, or the upper surface of the multilayer chip 11 and the two side surfaces in the yy direction. It may be provided continuously on the two side surfaces in the xx direction.

図16〜図17は第4構造変形例を示すもので、この積層セラミックコンデンサ10−4が前記積層セラミックコンデンサ10と異なるところは、積層チップ11の上面に2つの放熱導体部16−3を離隔して設け、2つの放熱導体部16−4を積層チップ11のy−y方向の2側面にそれぞれ設けると共に、共通内部電極13−2としてその両側縁が積層チップ11のy−y方向の2側面に露出し、且つ、その上端に設けた2つの引出部13bの上縁が積層チップ11の上面に露出したものを採用し、該共通内部電極13−2の両側縁を放熱導体部16−4にそれぞれ接続し、且つ、引出部13bの上縁を放熱導体部16−3にそれぞれ接続した点にある。製法及び機能は前記積層セラミックコンデンサ10と同様である。   FIGS. 16 to 17 show a fourth structural modification example. This multilayer ceramic capacitor 10-4 is different from the multilayer ceramic capacitor 10 in that the two radiating conductor portions 16-3 are separated on the upper surface of the multilayer chip 11. FIG. The two heat radiating conductors 16-4 are respectively provided on the two side surfaces of the multilayer chip 11 in the y-y direction, and both side edges of the common chip 13-2 are 2 in the y-y direction of the multilayer chip 11. The one exposed at the side surface and having the upper edges of the two lead portions 13b provided at the upper ends thereof exposed at the upper surface of the multilayer chip 11 is adopted, and both side edges of the common internal electrode 13-2 are connected to the heat radiation conductor portion 16-. 4 and the upper edge of the lead portion 13b is connected to the heat radiating conductor portion 16-3. The manufacturing method and function are the same as those of the multilayer ceramic capacitor 10.

この積層セラミックコンデンサ10−4によれば、積層セラミックコンデンサ10−4の熱を直接的に、且つ、高効率で放熱導体部16−3,16−4に伝えることにより、前記積層セラミックコンデンサ10と同様の放熱効果を得ることができる。この場合の上面側の放熱導体部は、積層チップ11の上面とx−x方向の1側面に連続して、または、積層チップ11の上面とx−x方向の2側面に連続して設けられていてもよく、一方、側面側の放熱導体部は積層チップ11のy−y方向の1側面とx−x方向の1側面に連続して、または、積層チップ11のy−y方向の1側面とx−x方向の2側面に連続して設けられていてもよい。   According to this multilayer ceramic capacitor 10-4, by transferring the heat of the multilayer ceramic capacitor 10-4 directly and highly efficiently to the heat radiating conductors 16-3 and 16-4, A similar heat dissipation effect can be obtained. In this case, the heat radiation conductor portion on the upper surface side is provided continuously with the upper surface of the multilayer chip 11 and one side surface in the xx direction, or continuously with the upper surface of the multilayer chip 11 and two side surfaces in the xx direction. On the other hand, the heat radiation conductor part on the side surface side is continuous with one side surface in the yy direction of the multilayer chip 11 and one side surface in the xx direction, or 1 in the yy direction of the multilayer chip 11. It may be provided continuously on the side surface and the two side surfaces in the xx direction.

[第2実施形態]
図18〜図20は本発明の第2実施形態を示す。図18は積層セラミックコンデンサの上面側から見た斜視図、図19(A)及び図19(B)は図18に示した積層セラミックコンデンサをy−y方向と平行で位置が異なる2つのラインで切断した縦断面図、図20(A)〜図20(C)は図18に示した積層セラミックコンデンサの製法説明図である。
[Second Embodiment]
18 to 20 show a second embodiment of the present invention. 18 is a perspective view seen from the upper surface side of the multilayer ceramic capacitor, and FIGS. 19A and 19B are views of the multilayer ceramic capacitor shown in FIG. 18 in two lines parallel to the y-y direction and having different positions. FIG. 20 (A) to FIG. 20 (C) are sectional views for explaining a method of manufacturing the multilayer ceramic capacitor shown in FIG.

第2実施形態の積層セラミックコンデンサ20は、直方体形状を成す積層チップ21を備える。この積層チップ21は、同一層に存する2つの第1内部電極22A,22Bと、第1内部電極22A,22Bが存する層とは異なる層に存する共通電極23とが、セラミック層(符号無し)を介して交互に、且つ、対向して配された構成を有する。第1内部電極22A,22Bが存する層の数と共通内部電極23が存する層の数は必要とする静電容量に応じて任意に設定される。   The multilayer ceramic capacitor 20 of the second embodiment includes a multilayer chip 21 having a rectangular parallelepiped shape. In this laminated chip 21, two first internal electrodes 22A and 22B in the same layer and a common electrode 23 in a layer different from the layer in which the first internal electrodes 22A and 22B exist have ceramic layers (no symbol). Via each other and opposite to each other. The number of layers in which the first internal electrodes 22A and 22B exist and the number of layers in which the common internal electrode 23 exists are arbitrarily set according to the required capacitance.

図19(A)に示すように、2つの第1内部電極22A,22Bはそれぞれ縦長長方形を成し、両者間には所定の間隙が設けられている。一方の第1内部電極22Aはその下端一側に所定幅の引出部22Aaを有し、該引出部22Aaの下縁は積層チップ21の下面に露出している。また、一方の第1内部電極22Aの上縁は積層チップ21の上面に露出しており、側縁は積層チップ21のy−y方向の1側面から離れた内側位置にある。他方の第1内部電極22Bはその下端一側に所定幅の引出部22Baを有し、該引出部22Baの下縁は積層チップ21の下面に露出している。また、他方の第1内部電極22Bの上縁及び側縁は積層チップ21の上面及びy−y方向の1側面から離れた内側位置にある。   As shown in FIG. 19A, the two first internal electrodes 22A and 22B each have a vertically long rectangle, and a predetermined gap is provided between them. One first internal electrode 22 </ b> A has a lead portion 22 </ b> Aa having a predetermined width on one lower end side, and the lower edge of the lead portion 22 </ b> Aa is exposed on the lower surface of the multilayer chip 21. Further, the upper edge of one first internal electrode 22A is exposed on the upper surface of the multilayer chip 21, and the side edge is at an inner position away from one side surface of the multilayer chip 21 in the yy direction. The other first internal electrode 22 </ b> B has a lead portion 22 </ b> Ba having a predetermined width on one lower end side, and the lower edge of the lead portion 22 </ b> Ba is exposed on the lower surface of the multilayer chip 21. Further, the upper edge and the side edge of the other first internal electrode 22B are located at the inner positions away from the upper surface of the multilayer chip 21 and one side surface in the yy direction.

図19(B)に示すように、共通内部電極23は2つの第1内部電極22A,22Bと向き合うに十分な大きさを有する横長長方形を成す。共通内部電極23はその下端中央に所定幅の引出部23aを有し、該引出部23aの下縁は積層チップ21の下面に引出部22Aa,22Baと非接触で露出している。また、共通内部電極23の上縁と両側縁は積層チップ21の上面及びy−y方向の2側面から離れた内側位置にある。   As shown in FIG. 19B, the common internal electrode 23 forms a horizontally long rectangle having a size sufficient to face the two first internal electrodes 22A and 22B. The common internal electrode 23 has a lead portion 23a having a predetermined width at the center of its lower end, and the lower edge of the lead portion 23a is exposed on the lower surface of the laminated chip 21 in a non-contact manner with the lead portions 22Aa and 22Ba. Further, the upper edge and both side edges of the common internal electrode 23 are located at inner positions away from the upper surface of the multilayer chip 21 and the two side surfaces in the yy direction.

積層チップ21の下面両側には第1外部電極24がx−x方向に帯状に設けられ、下面中央には2つの第1外部電極24と非接触で第2外部電極25がx−x方向に帯状に設けられている。図19(A)から分かるように一方の第1内部電極22Aの引出部22Aaの下縁は一方の第1外部電極24に接続し、他方の第1内部電極22Bの引出部22Baの下縁は他方の第1外部電極24に接続している。図19(B)から分かるように共通内部電極23の引出部23aの下縁は第2外部電極25に接続している。   The first external electrodes 24 are provided in a strip shape in the xx direction on both sides of the lower surface of the multilayer chip 21, and the second external electrodes 25 are not in contact with the two first external electrodes 24 in the center of the lower surface in the xx direction. It is provided in a band shape. As can be seen from FIG. 19A, the lower edge of the lead portion 22Aa of one first internal electrode 22A is connected to one first external electrode 24, and the lower edge of the lead portion 22Ba of the other first internal electrode 22B is The other first external electrode 24 is connected. As can be seen from FIG. 19B, the lower edge of the lead portion 23 a of the common internal electrode 23 is connected to the second external electrode 25.

また、積層チップ21の上面には該上面全体を覆うように放熱導体部26が設けられている。図19(A)から分かるように一方の第1内部電極22Aの上縁は放熱導体部26に接続している。   Further, a heat radiating conductor portion 26 is provided on the upper surface of the multilayer chip 21 so as to cover the entire upper surface. As can be seen from FIG. 19A, the upper edge of one first internal electrode 22 </ b> A is connected to the heat radiating conductor portion 26.

前記積層セラミックコンデンサ20を製造するに際しては、まず、チタン酸バリウム等の誘電体粉末を含有した未焼成セラミックシートの一面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して第1内部電極22A用の未焼成内部電極C21Aと第1内部電極22B用の未焼成内部電極C21Bを形成した第1シートS21(図20(A)参照)と、未焼成セラミックシートの一面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して共通内部電極23用の未焼成内部電極C22を形成した第2シートS22(図20(B)参照)とを交互に所定枚数積み重ねて、未焼成内部電極を形成していない未焼成セラミックシートから成るダミーシートS23(図20(C)参照)をその両側に重ね合わせて全体を熱圧着し、これを焼成する。図20には1部品に対応した大きさの未焼成セラミックシートを示したが、実際上は多数個取りを可能とした大きさの未焼成セラミックシートを用いて積層圧着後にこれを部品寸法に切断して焼成することで積層チップ21を得る。   When the multilayer ceramic capacitor 20 is manufactured, first, a conductor paste containing a metal powder such as silver or nickel is printed on one surface of an unfired ceramic sheet containing a dielectric powder such as barium titanate. The first sheet S21 (see FIG. 20A) on which the unfired internal electrode C21A for the electrode 22A and the unfired internal electrode C21B for the first internal electrode 22B are formed, and silver, nickel, etc. on one surface of the unfired ceramic sheet A predetermined number of second sheets S22 (see FIG. 20B) on which a conductive paste containing the metal powder is printed to form an unfired internal electrode C22 for the common internal electrode 23 are alternately stacked to form an unfired interior. A dummy sheet S23 (see FIG. 20C) made of an unfired ceramic sheet on which no electrode is formed is superposed on both sides, and the whole is thermocompression bonded, Les firing. FIG. 20 shows an unfired ceramic sheet of a size corresponding to one part. In practice, however, an unfired ceramic sheet of a size that can be picked up in large numbers is used, and this is cut into component dimensions after laminating and pressing. Then, the laminated chip 21 is obtained by firing.

次に、焼成により得られた積層チップ21の上面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して未焼成放熱導体部(図示省略)を形成し、且つ、積層チップ21の下面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して2つの未焼成第1外部電極(図示省略)と1つの未焼成第2外部電極(図示省略)を形成し、これらに焼き付け処理を施す。勿論、未焼成放熱導体部,未焼成第1外部電極及び未焼成第2外部電極の焼き付け処理は積層チップの焼成処理と同時に行うこともできる。   Next, a conductive paste containing metal powder such as silver or nickel is printed on the upper surface of the laminated chip 21 obtained by firing to form an unfired heat radiating conductor (not shown), and the lower surface of the laminated chip 21 A conductive paste containing a metal powder such as silver or nickel is printed on the substrate to form two unfired first external electrodes (not shown) and one unfired second external electrode (not shown), which are baked. Apply. Of course, the baking process of the unsintered heat radiation conductor part, the unsintered first external electrode and the unsintered second external electrode can be performed simultaneously with the firing process of the laminated chip.

第2実施形態の積層セラミックコンデンサ20は、一方の第1外部電極24と第2外部電極25との間に一方の第1内部電極22Aと共通内部電極23の一部との対向面積及び積層数に準じた所定の静電容量を得ることができ、他方の第1外部電極24と第2外部電極25との間に他方の第1内部電極22Bと共通内部電極23の一部との対向面積及び積層数に準じた所定の静電容量を得ることができる。また、2つの第1外部電極24と共通内部電極23との間に2つの第1内部電極22A,22Bと共通内部電極23との対向面積及び積層数に準じた所定の静電容量を得ることができる。つまり、2つの第1外部電極24と1つの第2外部電極25との接続形態に応じて、積層セラミックコンデンサ20を2つのコンデンサが組み合わされたコンデンサアレイ、または、単独のコンデンサとして使用することができる。   In the multilayer ceramic capacitor 20 of the second embodiment, the facing area and the number of layers between one first internal electrode 22A and a part of the common internal electrode 23 between one first external electrode 24 and the second external electrode 25. A predetermined capacitance according to the above can be obtained, and the opposing area of the other first internal electrode 22B and a part of the common internal electrode 23 between the other first external electrode 24 and the second external electrode 25 In addition, a predetermined capacitance according to the number of layers can be obtained. Further, a predetermined capacitance according to the facing area and the number of stacked layers between the two first internal electrodes 22A and 22B and the common internal electrode 23 is obtained between the two first external electrodes 24 and the common internal electrode 23. Can do. That is, the multilayer ceramic capacitor 20 may be used as a capacitor array in which two capacitors are combined or as a single capacitor depending on the connection form between the two first external electrodes 24 and the one second external electrode 25. it can.

この積層セラミックコンデンサ20にあっては、2つの第1内部電極22A,22Bと共通内部電極23との間に不要な導体層が存しないため、つまり、図1〜図3に示した従来の積層セラミックコンデンサのように隣接する内部電極1間それぞれに内部電極1とは別の放熱用内部電極5が存しないため、一方の第1外部電極24と第2外部電極25との間、他方の第1外部電極24と第2外部電極25との間、さらには、2つの第1外部電極24と第2外部電極25との間に、所期の静電容量を安定して確保することができる。   In this multilayer ceramic capacitor 20, there is no unnecessary conductor layer between the two first internal electrodes 22A, 22B and the common internal electrode 23, that is, the conventional multilayer capacitor shown in FIGS. Since there is no heat dissipating internal electrode 5 different from the internal electrode 1 between the adjacent internal electrodes 1 like a ceramic capacitor, between the first external electrode 24 and the second external electrode 25, A desired capacitance can be stably secured between the first external electrode 24 and the second external electrode 25 and between the two first external electrodes 24 and the second external electrode 25. .

また、この積層セラミックコンデンサ20にあっては、実装後の積層セラミックコンデンサ20への電圧印加時に各内部電極22A,22B,23で熱が発生すると、また、実装基板からの熱が各外部電極24,25から各内部電極22A,22B,23に伝わると、この熱は一方の第1内部電極22Aから放熱導体部26に直接的に伝わって該放熱導体部26から外部に放出される。要するに、積層セラミックコンデンサ20を熱を直接的に、且つ、高効率で放熱導体部26に伝えることにより、コンデンサ自体の熱を効果的に外部に放出してその温度上昇を確実に抑制することができる。しかも、放熱導体部26に十分な面積が確保できるので前記の熱放出をより効果的に行うことができる。   In the multilayer ceramic capacitor 20, when heat is generated in the internal electrodes 22A, 22B, and 23 when a voltage is applied to the multilayer ceramic capacitor 20 after mounting, the heat from the mounting substrate is also transferred to the external electrodes 24. , 25 is transmitted to the internal electrodes 22A, 22B, 23 from the first internal electrode 22A, directly to the heat radiating conductor 26, and is released to the outside from the heat radiating conductor 26. In short, by transferring heat to the multilayer ceramic capacitor 20 directly and with high efficiency to the heat radiating conductor portion 26, it is possible to effectively release the heat of the capacitor itself to the outside and reliably suppress the temperature rise. it can. In addition, since a sufficient area can be secured in the heat radiating conductor portion 26, the heat release can be performed more effectively.

尚、図18〜図20には同一層に2つの第1内部電極22A,22Bを設けたものを示したが、同一層に3以上の第1内部電極を設け、これらに対向する大きさを有する共通内部電極を設ければ、3以上のコンデンサが組み合われたコンデンサアレイ(単独のコンデンサとしても使用可能)として構成することもできる。第1内部電極を3以上設ける場合には第1内部電極の数に応じて外部電極の数は増加することになる。   18 to 20 show two first internal electrodes 22A and 22B provided in the same layer, but three or more first internal electrodes are provided in the same layer, and the size facing these is shown. If the common internal electrode which has is provided, it can also be comprised as a capacitor | condenser array (it can be used also as an independent capacitor | condenser) which combined the 3 or more capacitor | condenser. When three or more first internal electrodes are provided, the number of external electrodes increases according to the number of first internal electrodes.

また、外部電極の数は必ずしも第1内部電極の数+1とする必要はなく、例えば図21に示した積層セラミックコンデンサ20’のように各第1内部電極22A’,22B’の下端中央に引出部22aを設け、共通内部電極23’の下端中央と下端両側に計3個の引出部23aを設けた構成を採用すれば、外部電極の数を任意に増加させることも可能である。   The number of external electrodes is not necessarily the number of first internal electrodes + 1. For example, as shown in the multilayer ceramic capacitor 20 ′ shown in FIG. 21, the external electrodes are led to the center of the lower ends of the first internal electrodes 22A ′ and 22B ′. By adopting a configuration in which the portion 22a is provided and a total of three lead portions 23a are provided at the center of the lower end of the common internal electrode 23 ′ and both sides of the lower end, the number of external electrodes can be arbitrarily increased.

以下に、前記第2実施形態の構造変形例を図22〜図29を引用して説明する。   Hereinafter, structural modifications of the second embodiment will be described with reference to FIGS.

図22〜図23は第1構造変形例を示すもので、この積層セラミックコンデンサ20−1が前記積層セラミックコンデンサ20と異なるところは、2つの放熱導体部26−1を積層チップ21のy−y方向の2側面に第1外部電極24と接続するようにそれぞれ設けると共に、一方の第1内部電極22A−1としてその上縁が積層チップ21の上面から離れた内側位置にあるものを採用した点にある。製法及び機能は前記積層セラミックコンデンサ20と同様である。   22 to 23 show a first structural modification example. This multilayer ceramic capacitor 20-1 is different from the multilayer ceramic capacitor 20 in that two radiating conductor portions 26-1 are connected to the y-y of the multilayer chip 21. FIG. Are provided so as to be connected to the first external electrode 24 on the two side surfaces in the direction, and the first inner electrode 22A-1 has an upper edge at an inner position away from the upper surface of the laminated chip 21. It is in. The manufacturing method and function are the same as those of the multilayer ceramic capacitor 20.

この積層セラミックコンデンサ20−1によれば、積層セラミックコンデンサ20−1の熱を直接的に、且つ、高効率で放熱導体部26−1に伝えることにより、前記積層セラミックコンデンサ20と同様の放熱効果を得ることができる。この場合の各放熱導体部は、積層チップ21のy−y方向の1側面とx−x方向の1側面に連続して、または、積層チップ21のy−y方向の1側面とx−x方向の2側面に連続して設けられていてもよい。   According to the multilayer ceramic capacitor 20-1, the heat radiation effect similar to that of the multilayer ceramic capacitor 20 is achieved by directly and efficiently transmitting the heat of the multilayer ceramic capacitor 20-1 to the heat radiation conductor 26-1. Can be obtained. In this case, each radiating conductor portion is continuous with one side surface in the yy direction and one side surface in the xx direction of the multilayer chip 21 or one side surface in the yy direction of the multilayer chip 21 and xx. It may be provided continuously on the two side surfaces in the direction.

図24は第2構造変形例を示すもので、この積層セラミックコンデンサ20−2が前記積層セラミックコンデンサ20と異なるところは、2つの放熱導体部26−1を積層チップ21のy−y方向の2側面に第1外部電極24と接続するようにそれぞれ設けると共に、一方の第1内部電極22A−2としてその側縁が積層チップ21のy−y方向の1側面に露出し、且つ、その上縁が積層チップ21の上面から離れた内側位置にあるものを採用して、該第1内部電極22A−2の側縁を一方の放熱導体部26−1に接続し、さらに、他方の第1内部電極22B−1としてその側縁が積層チップ21のy−y方向の1側面に露出したものを採用して、該第1内部電極22B−1の側縁を他方の放熱導体部26−1に接続した点にある。製法及び機能は前記積層セラミックコンデンサ20と同様である。   FIG. 24 shows a second structural modification example. This multilayer ceramic capacitor 20-2 is different from the multilayer ceramic capacitor 20 in that two heat radiating conductor portions 26-1 are arranged in the y-y direction of the multilayer chip 21. FIG. Each side surface is provided so as to be connected to the first external electrode 24, and the side edge of the first internal electrode 22 </ b> A- 2 is exposed on one side surface in the yy direction of the multilayer chip 21, and the upper edge thereof Is employed at an inner position away from the upper surface of the multilayer chip 21, and the side edge of the first internal electrode 22A-2 is connected to one of the heat radiating conductors 26-1, and the other first internal electrode As the electrode 22B-1, one whose side edge is exposed on one side surface in the y-y direction of the multilayer chip 21 is adopted, and the side edge of the first internal electrode 22B-1 is used as the other heat radiating conductor 26-1. It is at the point of connection. The manufacturing method and function are the same as those of the multilayer ceramic capacitor 20.

この積層セラミックコンデンサ20−2によれば、積層セラミックコンデンサ20−2の熱を直接的に、且つ、高効率で放熱導体部26−1に伝えることにより、前記積層セラミックコンデンサ20と同様の放熱効果を得ることができる。この場合の各放熱導体部は、積層チップ21のy−y方向の1側面とx−x方向の1側面に連続して、または、積層チップ21のy−y方向の1側面とx−x方向の2側面に連続して設けられていてもよい。   According to the multilayer ceramic capacitor 20-2, the heat radiation effect similar to that of the multilayer ceramic capacitor 20 is achieved by directly and efficiently transmitting the heat of the multilayer ceramic capacitor 20-2 to the heat radiation conductor 26-1. Can be obtained. In this case, each radiating conductor portion is continuous with one side surface in the yy direction and one side surface in the xx direction of the multilayer chip 21 or one side surface in the yy direction of the multilayer chip 21 and xx. It may be provided continuously on the two side surfaces in the direction.

図25〜図26は第3構造変形例を示すもので、この積層セラミックコンデンサ20−3が前記積層セラミックコンデンサ20と異なるところは、放熱導体部26−2を積層チップ21の上面とy−y方向の2側面に連続して設けた点にある。製法及び機能は前記積層セラミックコンデンサ10と同様である。   FIG. 25 to FIG. 26 show a third structural modification. The laminated ceramic capacitor 20-3 is different from the laminated ceramic capacitor 20 in that the radiating conductor portion 26-2 is connected to the upper surface of the laminated chip 21 and yy. It is in the point provided continuously on the two side surfaces of the direction. The manufacturing method and function are the same as those of the multilayer ceramic capacitor 10.

この積層セラミックコンデンサ20−3によれば、積層セラミックコンデンサ20−3の熱を直接的に、且つ、高効率で放熱導体部26−2に伝えることにより、前記積層セラミックコンデンサ20と同様の放熱効果を得ることができる。この場合の放熱導体部は、積層チップ21の上面とy−y方向の2側面とx−x方向の1側面に連続して、または、積層チップ21の上面とy−y方向の2側面とx−x方向の2側面に連続して設けられていてもよい。   According to the multilayer ceramic capacitor 20-3, the heat dissipation effect similar to that of the multilayer ceramic capacitor 20 can be obtained by directly and efficiently transmitting the heat of the multilayer ceramic capacitor 20-3 to the heat radiation conductor 26-2. Can be obtained. In this case, the heat radiating conductor portion is continuous with the upper surface of the multilayer chip 21, the two side surfaces in the yy direction, and the one side surface in the xx direction, or the upper surface of the multilayer chip 21 and the two side surfaces in the yy direction. It may be provided continuously on the two side surfaces in the xx direction.

図27は第4構造変形例を示すもので、この積層セラミックコンデンサ20−4が前記積層セラミックコンデンサ20と異なるところは、放熱導体部26−2を積層チップ21の上面とy−y方向の2側面に連続して設けると共に、一方の第1内部電極22A−3としてその側縁が積層チップ21のy−y方向の1側面に露出し、且つ、その上縁が積層チップ21の上面から離れた内側位置にあるものを採用して、該第1内部電極22A−3の側縁を放熱導体部26−2に接続した点にある。製法及び機能は前記積層セラミックコンデンサ20と同様である。   FIG. 27 shows a fourth structural modification example. This multilayer ceramic capacitor 20-4 is different from the multilayer ceramic capacitor 20 in that the heat radiating conductor portion 26-2 is connected to the top surface of the multilayer chip 21 and 2 in the y-y direction. The first inner electrode 22 </ b> A- 3 is continuously provided on the side surface, the side edge of the first internal electrode 22 </ b> A- 3 is exposed on one side surface of the multilayer chip 21 in the y-y direction, and the upper edge is separated from the upper surface of the multilayer chip 21. What is in the inner position is that the side edge of the first internal electrode 22A-3 is connected to the heat radiating conductor 26-2. The manufacturing method and function are the same as those of the multilayer ceramic capacitor 20.

この積層セラミックコンデンサ20−4によれば、積層セラミックコンデンサ20−4の熱を直接的に、且つ、高効率で放熱導体部26−2に伝えることにより、前記積層セラミックコンデンサ20と同様の放熱効果を得ることができる。この場合の放熱導体部は、積層チップ21の上面とy−y方向の2側面とx−x方向の1側面に連続して、または、積層チップ21の上面とy−y方向の2側面とx−x方向の2側面に連続して設けられていてもよい。   According to the multilayer ceramic capacitor 20-4, the heat dissipation effect similar to that of the multilayer ceramic capacitor 20 can be obtained by directly and efficiently transmitting the heat of the multilayer ceramic capacitor 20-4 to the heat radiating conductor 26-2. Can be obtained. In this case, the heat radiating conductor portion is continuous with the upper surface of the multilayer chip 21, the two side surfaces in the yy direction, and the one side surface in the xx direction, or the upper surface of the multilayer chip 21 and the two side surfaces in the yy direction. It may be provided continuously on the two side surfaces in the xx direction.

図28〜図29は第5構造変形例を示すもので、この積層セラミックコンデンサ20−5が前記積層セラミックコンデンサ20と異なるところは、放熱導体部26−3を積層チップ21の上面に2つ離隔して設け、2つの放熱導体部26−4を積層チップ21のy−y方向の2側面に第1外部電極24と接続するようにそれぞれ設けると共に、第1内部電極22A−4,22B−2としてその1側縁が積層チップ21のy−y方向の1側面に露出し、且つ、その上端に設けた引出部22Ab,22Bbの上縁が積層チップ21の上面に露出したものを採用して、該第1内部電極22A−4,22B−2の1側縁を放熱導体部26−4にそれぞれ接続し、且つ、引出部22Ab,22Bbの上縁を放熱導体部26−3にそれぞれ接続した点にある。製法及び機能は前記積層セラミックコンデンサ20と同様である。   FIGS. 28 to 29 show a fifth structural modification example. This multilayer ceramic capacitor 20-5 is different from the multilayer ceramic capacitor 20 in that the heat radiation conductor portion 26-3 is separated by two on the upper surface of the multilayer chip 21. FIG. The two heat radiating conductors 26-4 are provided on the two side surfaces of the multilayer chip 21 in the y-y direction so as to be connected to the first external electrode 24, and the first internal electrodes 22A-4 and 22B-2 are provided. The one side edge is exposed on one side surface of the laminated chip 21 in the y-y direction, and the upper edge of the lead portions 22Ab and 22Bb provided on the upper end is exposed on the upper surface of the laminated chip 21. In addition, one side edge of each of the first internal electrodes 22A-4 and 22B-2 is connected to the heat radiating conductor portion 26-4, and the upper edge of each of the lead portions 22Ab and 22Bb is connected to the heat radiating conductor portion 26-3. To the point . The manufacturing method and function are the same as those of the multilayer ceramic capacitor 20.

この積層セラミックコンデンサ20−5によれば、積層セラミックコンデンサ20−5の熱を直接的に、且つ、高効率で放熱導体部26−3,26−4に伝えることにより、前記積層セラミックコンデンサ20と同様の放熱効果を得ることができる。この場合の上面側の放熱導体部は、積層チップ21の上面とx−x方向の1側面に連続して、または、積層チップ21の上面とx−x方向の2側面に連続して設けられていてもよく、一方、側面側の放熱導体部は積層チップ21のy−y方向の1側面とx−x方向の1側面に連続して、または、積層チップ21のy−y方向の1側面とx−x方向の2側面に連続して設けられていてもよい。   According to the multilayer ceramic capacitor 20-5, the heat of the multilayer ceramic capacitor 20-5 is directly and efficiently transmitted to the heat radiating conductors 26-3 and 26-4, so that the multilayer ceramic capacitor 20-5 A similar heat dissipation effect can be obtained. In this case, the radiating conductor portion on the upper surface side is continuously provided on the upper surface of the multilayer chip 21 and one side surface in the xx direction, or continuously on the upper surface of the multilayer chip 21 and two side surfaces in the xx direction. On the other hand, the radiating conductor portion on the side surface side is continuous with one side surface in the yy direction of the multilayer chip 21 and one side surface in the xx direction, or 1 in the yy direction of the multilayer chip 21. It may be provided continuously on the side surface and the two side surfaces in the xx direction.

[第3実施形態]
図30〜図32は本発明の第3実施形態を示す。図30は積層セラミックコンデンサの上面側から見た斜視図、図31(A)及び図31(B)は図30に示した積層セラミックコンデンサをy−y方向と平行で位置が異なる2つのラインで切断した縦断面図、図32(A)〜図32(C)は図30に示した積層セラミックコンデンサの製法説明図である。
[Third Embodiment]
30 to 32 show a third embodiment of the present invention. 30 is a perspective view seen from the upper surface side of the multilayer ceramic capacitor, and FIGS. 31A and 31B are views of the multilayer ceramic capacitor shown in FIG. 30 in two lines parallel to the y-y direction and having different positions. FIG. 32 (A) to FIG. 32 (C) are sectional views for explaining a method of manufacturing the multilayer ceramic capacitor shown in FIG.

第3実施形態の積層セラミックコンデンサ30は、直方体形状を成す積層チップ31を備える。この積層チップ31は、同一層に存する2つの第1内部電極32A,32Bと、第1内部電極32A,32Bが存する層とは異なる層に存する共通電極33とが、セラミック層(符号無し)を介して交互に、且つ、対向して配された構成を有する。第1内部電極22A,22Bが存する層の数と共通内部電極33が存する層の数は必要とする静電容量に応じて任意に設定される。   A multilayer ceramic capacitor 30 according to the third embodiment includes a multilayer chip 31 having a rectangular parallelepiped shape. In the multilayer chip 31, two first internal electrodes 32A and 32B existing in the same layer and a common electrode 33 existing in a layer different from the layer where the first internal electrodes 32A and 32B exist are ceramic layers (no symbol). Via each other and opposite to each other. The number of layers in which the first internal electrodes 22A and 22B exist and the number of layers in which the common internal electrode 33 exists are arbitrarily set according to the required capacitance.

図31(A)に示すように、2つの第1内部電極32A,32Bはそれぞれ縦長長方形を成し、両者間には所定の間隙が設けられている。一方の第1内部電極32Aはその下端一側に所定幅の引出部32Aaを有し、該引出部32Aaの下縁は積層チップ31の下面に露出している。また、一方の第1内部電極32Aの側縁は積層チップ31のy−y方向の1側面に露出しており、上縁は積層チップ31の上面から離れた内側位置にある。他方の第1内部電極32Bはその下端一側に所定幅の引出部32Baを有し、該引出部32Baの下縁は積層チップ31の下面に露出している。また、他方の第1内部電極32Bの側縁は積層チップ31のy−y方向の1側面に露出しており、上縁は積層チップ31の上面から離れた内側位置にある。   As shown in FIG. 31A, the two first internal electrodes 32A and 32B each have a vertically long rectangle, and a predetermined gap is provided between them. One first internal electrode 32 </ b> A has a lead portion 32 </ b> Aa having a predetermined width on one lower end side, and the lower edge of the lead portion 32 </ b> Aa is exposed on the lower surface of the multilayer chip 31. Further, the side edge of one first internal electrode 32 </ b> A is exposed on one side surface in the y-y direction of the multilayer chip 31, and the upper edge is in an inner position away from the upper surface of the multilayer chip 31. The other first internal electrode 32 </ b> B has a lead portion 32 </ b> Ba having a predetermined width on one lower end side, and the lower edge of the lead portion 32 </ b> Ba is exposed on the lower surface of the multilayer chip 31. The side edge of the other first internal electrode 32 </ b> B is exposed on one side surface in the y-y direction of the multilayer chip 31, and the upper edge is at an inner position away from the upper surface of the multilayer chip 31.

図31(B)に示すように、共通内部電極33は2つの第1内部電極32A,32Bと向き合うに十分な大きさを有する横長長方形を成す。共通内部電極33はその下端中央に所定幅の引出部33aを有し、該引出部33aの下縁は積層チップ31の下面に引出部32Aa,32Baと非接触で露出している。また、共通内部電極33の上縁は積層チップ31の上面に露出しており、両側縁は積層チップ31のy−y方向の2側面から離れた内側位置にある。   As shown in FIG. 31B, the common internal electrode 33 forms a horizontally long rectangle having a size sufficient to face the two first internal electrodes 32A and 32B. The common internal electrode 33 has a lead portion 33a having a predetermined width at the center of its lower end, and the lower edge of the lead portion 33a is exposed on the lower surface of the laminated chip 31 in a non-contact manner with the lead portions 32Aa and 32Ba. Further, the upper edge of the common internal electrode 33 is exposed on the upper surface of the multilayer chip 31, and both side edges are located at inner positions away from the two side surfaces of the multilayer chip 31 in the yy direction.

積層チップ31の下面両側には第1外部電極34がx−x方向に帯状に設けられ、下面中央には2つの第1外部電極34と非接触で第2外部電極35がx−x方向に帯状に設けられている。図31(A)から分かるように一方の第1内部電極32Aの引出部32Aaの下縁は一方の第1外部電極34に接続し、他方の第1内部電極32Bの引出部32Baの下縁は他方の第1外部電極34に接続している。図31(B)から分かるように共通内部電極33の引出部33aの下縁は第2外部電極35に接続している。   The first external electrodes 34 are provided in a strip shape in the xx direction on both sides of the lower surface of the multilayer chip 31, and the second external electrodes 35 are not in contact with the two first external electrodes 34 in the center of the lower surface in the xx direction. It is provided in a band shape. As can be seen from FIG. 31A, the lower edge of the lead portion 32Aa of one first inner electrode 32A is connected to one first outer electrode 34, and the lower edge of the lead portion 32Ba of the other first inner electrode 32B is The other first external electrode 34 is connected. As can be seen from FIG. 31B, the lower edge of the lead portion 33 a of the common internal electrode 33 is connected to the second external electrode 35.

また、積層チップ31の上面には該上面全体をほぼ覆うように放熱導体部36が設けられている。図31(B)から分かるように共通内部電極33の上縁は放熱導体部36に接続している。また、積層チップ31のy−y方向の2側面には放熱導体部37が第1外部電極34と接続するようにそれぞれ設けられている。図31(A)から分かるように一方の第1内部電極32Aの側縁は一方の放熱導体部37に接続し、他方の第1内部電極32Bの側縁は他方の放熱導体部38に接続している。この場合の上面側の放熱導体部36は積層チップ31の上面とx−x方向の1側面に連続して、または、積層チップ31の上面とx−x方向の2側面に連続して設けられていてもよく、一方、側面側の各放熱導体部37は積層チップ31のy−y方向の1側面とx−x方向の1側面に連続して、または、積層チップ31のy−y方向の1側面とx−x方向の2側面に連続して設けられていてもよい。   Further, a heat radiating conductor 36 is provided on the upper surface of the multilayer chip 31 so as to substantially cover the entire upper surface. As can be seen from FIG. 31B, the upper edge of the common internal electrode 33 is connected to the heat radiating conductor 36. Further, heat radiation conductors 37 are provided on the two side surfaces of the multilayer chip 31 in the yy direction so as to be connected to the first external electrode 34. As can be seen from FIG. 31A, the side edge of one first internal electrode 32A is connected to one heat radiating conductor portion 37, and the side edge of the other first internal electrode 32B is connected to the other heat radiating conductor portion 38. ing. In this case, the radiating conductor 36 on the upper surface side is provided continuously on the upper surface of the multilayer chip 31 and one side surface in the xx direction, or continuously on the upper surface of the multilayer chip 31 and two side surfaces in the xx direction. On the other hand, each of the heat radiation conductors 37 on the side surface side is continuous with one side surface in the yy direction of the multilayer chip 31 and one side surface in the xx direction, or in the yy direction of the multilayer chip 31. May be provided continuously on one side surface and two side surfaces in the xx direction.

前記積層セラミックコンデンサ30を製造するに際しては、まず、チタン酸バリウム等の誘電体粉末を含有した未焼成セラミックシートの一面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して第1内部電極32A用の未焼成内部電極C31Aと第1内部電極32B用の未焼成内部電極C31Bを形成した第1シートS31(図32(A)参照)と、未焼成セラミックシートの一面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して共通内部電極33用の未焼成内部電極C32を形成した第2シートS32(図32(B)参照)とを交互に所定枚数積み重ねて、未焼成内部電極を形成していない未焼成セラミックシートから成るダミーシートS33(図32(C)参照)をその両側に重ね合わせて全体を熱圧着し、これを焼成する。図32には1部品に対応した大きさの未焼成セラミックシートを示したが、実際上は多数個取りを可能とした大きさの未焼成セラミックシートを用いて積層圧着後にこれを部品寸法に切断して焼成することで積層チップ31を得る。   When the multilayer ceramic capacitor 30 is manufactured, first, a conductor paste containing a metal powder such as silver or nickel is printed on one surface of an unfired ceramic sheet containing a dielectric powder such as barium titanate. The first sheet S31 (see FIG. 32A) on which the unfired internal electrode C31A for the electrode 32A and the unfired internal electrode C31B for the first internal electrode 32B are formed, and silver, nickel, etc. on one surface of the unfired ceramic sheet A predetermined number of second sheets S32 (see FIG. 32B) on which a conductive paste containing the metal powder is printed to form the unfired internal electrode C32 for the common internal electrode 33 are alternately stacked, and the unfired interior A dummy sheet S33 (see FIG. 32C) made of an unfired ceramic sheet on which no electrode is formed is superimposed on both sides, and the whole is thermocompression bonded, Les firing. FIG. 32 shows an unfired ceramic sheet of a size corresponding to one part. However, in actuality, an unfired ceramic sheet of a size that can be picked up in large numbers is used, and this is cut into component dimensions after laminating and pressing. Then, the multilayer chip 31 is obtained by firing.

次に、焼成により得られた積層チップ31の上面とy−y方向の2側面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して未焼成放熱導体部(図示省略)を形成し、且つ、積層チップ31の下面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して2つの未焼成第1外部電極(図示省略)と1つの未焼成第2外部電極(図示省略)を形成し、これらに焼き付け処理を施す。勿論、未焼成放熱導体部,未焼成第1外部電極及び未焼成第2外部電極の焼き付け処理は積層チップの焼成処理と同時に行うこともできる。   Next, a conductive paste containing metal powder such as silver or nickel is printed on the upper surface and two side surfaces in the y-y direction of the laminated chip 31 obtained by firing to form an unfired heat radiating conductor (not shown). In addition, a conductor paste containing a metal powder such as silver or nickel is printed on the lower surface of the multilayer chip 31, and two unfired first external electrodes (not shown) and one unfired second external electrode (not shown) These are baked. Of course, the baking process of the unsintered heat radiation conductor part, the unsintered first external electrode and the unsintered second external electrode can be performed simultaneously with the firing process of the laminated chip.

第3実施形態の積層セラミックコンデンサ30は、一方の第1外部電極34と第2外部電極35との間に一方の第1内部電極32Aと共通内部電極33の一部との対向面積及び積層数に準じた所定の静電容量を得ることができ、他方の第1外部電極34と第2外部電極35との間に他方の第1内部電極32Bと共通内部電極33の一部との対向面積及び積層数に準じた所定の静電容量を得ることができる。また、2つの第1外部電極34と共通内部電極33との間に2つの第1内部電極32A,32Bと共通内部電極33との対向面積及び積層数に準じた所定の静電容量を得ることができる。つまり、2つの第1外部電極34と1つの第2外部電極35との接続形態に応じて、積層セラミックコンデンサ30を2つのコンデンサが組み合わされたコンデンサアレイ、または、単独のコンデンサとして使用することができる。   In the multilayer ceramic capacitor 30 of the third embodiment, the facing area and the number of stacked layers between one first internal electrode 32A and a part of the common internal electrode 33 between one first external electrode 34 and the second external electrode 35. A predetermined capacitance according to the above can be obtained, and the opposing area of the other first internal electrode 32B and a part of the common internal electrode 33 between the other first external electrode 34 and the second external electrode 35. In addition, a predetermined capacitance according to the number of layers can be obtained. Further, a predetermined capacitance according to the facing area and the number of stacked layers of the two first internal electrodes 32A, 32B and the common internal electrode 33 is obtained between the two first external electrodes 34 and the common internal electrode 33. Can do. That is, the multilayer ceramic capacitor 30 may be used as a capacitor array in which two capacitors are combined or as a single capacitor depending on the connection form of the two first external electrodes 34 and the one second external electrode 35. it can.

この積層セラミックコンデンサ30にあっては、2つの第1内部電極32A,32Bと共通内部電極33との間に不要な導体層が存しないため、つまり、図1〜図3に示した従来の積層セラミックコンデンサのように隣接する内部電極1間それぞれに内部電極1とは別の放熱用内部電極5が存しないため、一方の第1外部電極34と第2外部電極35との間、他方の第1外部電極34と第2外部電極35との間、さらには、2つの第1外部電極34と第2外部電極35との間に、所期の静電容量を安定して確保することができる。   In this multilayer ceramic capacitor 30, an unnecessary conductor layer does not exist between the two first internal electrodes 32A, 32B and the common internal electrode 33, that is, the conventional multilayer capacitor shown in FIGS. Since there is no heat dissipating internal electrode 5 different from the internal electrode 1 between the adjacent internal electrodes 1 like a ceramic capacitor, between the first external electrode 34 and the second external electrode 35, A desired capacitance can be stably secured between the first external electrode 34 and the second external electrode 35 and between the two first external electrodes 34 and the second external electrode 35. .

また、この積層セラミックコンデンサ30にあっては、実装後の積層セラミックコンデンサ30への電圧印加時に各内部電極32A,32B,33で熱が発生すると、また、実装基板からの熱が各外部電極34,35から各内部電極32A,32B,33に伝わると、この熱は各第1内部電極32A,32Bから側面側の放熱導体部37に直接的に伝わると共に共通内部電極33から上面側の放熱導体部36に直接的に伝わって該放熱導体部36,37から外部に放出される。要するに、積層セラミックコンデンサ30を熱を直接的に、且つ、高効率で放熱導体部36,37に伝えることにより、コンデンサ自体の熱を効果的に外部に放出してその温度上昇を確実に抑制することができる。しかも、放熱導体部36,37に十分な面積が確保できるので前記の熱放出をより効果的に行うことができる。   Further, in this multilayer ceramic capacitor 30, when heat is generated in each of the internal electrodes 32A, 32B, 33 when a voltage is applied to the multilayer ceramic capacitor 30 after mounting, the heat from the mounting substrate is also transferred to each external electrode 34. , 35 is transmitted to the internal electrodes 32A, 32B, 33 from the first internal electrodes 32A, 32B directly to the side heat radiation conductors 37, and from the common internal electrode 33 to the heat radiation conductor on the upper surface side. It is directly transmitted to the portion 36 and is discharged to the outside from the heat radiating conductor portions 36 and 37. In short, by transferring heat directly to the radiating conductors 36 and 37 through the multilayer ceramic capacitor 30 with high efficiency, the heat of the capacitor itself is effectively released to the outside and the temperature rise is reliably suppressed. be able to. In addition, since a sufficient area can be secured for the heat radiating conductor portions 36 and 37, the heat release can be performed more effectively.

尚、図30〜図32には同一層に2つの第1内部電極32A,32Bを設けたものを示したが、同一層に3以上の第1内部電極を設け、これらに対向する大きさを有する共通内部電極を設ければ、3以上のコンデンサが組み合われたコンデンサアレイ(単独のコンデンサとしても使用可能)として構成することもできる。第1内部電極を3以上設ける場合には第1内部電極の数に応じて外部電極の数は増加することになる。   30 to 32 show the case where two first internal electrodes 32A and 32B are provided in the same layer, but three or more first internal electrodes are provided in the same layer, and the size facing these is shown. If the common internal electrode which has is provided, it can also be comprised as a capacitor | condenser array (it can be used also as an independent capacitor | condenser) which combined the 3 or more capacitor | condenser. When three or more first internal electrodes are provided, the number of external electrodes increases according to the number of first internal electrodes.

また、外部電極の数は必ずしも第1内部電極の数+1とする必要はなく、例えば図33に示した積層セラミックコンデンサ30’のように各第1内部電極32A’,32B’の下端中央に引出部32aを設け、共通内部電極33’の下端中央と下端両側に計3個の引出部33aを設けた構成を採用すれば、外部電極の数を任意に増加させることも可能である。   The number of external electrodes is not necessarily the number of first internal electrodes + 1. For example, as shown in the multilayer ceramic capacitor 30 ′ shown in FIG. 33, the external electrodes are led to the center of the lower ends of the first internal electrodes 32A ′ and 32B ′. If the configuration in which the portion 32a is provided and a total of three lead portions 33a are provided at the center of the lower end of the common internal electrode 33 ′ and both sides of the lower end is employed, the number of external electrodes can be arbitrarily increased.

以下に、前記第3実施形態の構造変形例を図34〜図37を引用して説明する。   Hereinafter, structural modifications of the third embodiment will be described with reference to FIGS.

図34〜図35は第1構造変形例を示すもので、この積層セラミックコンデンサ30−1が前記積層セラミックコンデンサ30と異なるところは、2つの放熱導体部37−1を積層チップ31のy−y方向の2側面に第1外部電極34と非接触でそれぞれ設けると共に、一方の第1内部電極32A−1としてその上縁が積層チップ31の上面に露出し、且つ、その側縁が積層チップ31のy−y方向の1側面から離れた内側位置にあるものを採用して、該第1内部電極32A−1の上縁を上面側の放熱導体部36に接続し、且つ、側縁を一方の側面側の放熱導体部37−1に接続し、さらに、共通内部電極33−1としてその1側縁が積層チップ31のy−y方向の1側面に露出し、且つ、その上縁が積層チップ31の上面から離れた内側位置にあるものを採用して、該共通内部電極33−1の1側縁を一方の側面側の放熱導体部37−1に接続した点にある。製法及び機能は前記積層セラミックコンデンサ30と同様である。   34 to 35 show a first structural modification example. The multilayer ceramic capacitor 30-1 is different from the multilayer ceramic capacitor 30 in that two radiating conductor portions 37-1 are connected to the yy of the multilayer chip 31. FIG. The first outer electrode 34 is provided on two side surfaces in a non-contact manner, and the upper edge of the first inner electrode 32A-1 is exposed on the upper surface of the multilayer chip 31, and the side edge thereof is the multilayer chip 31. Of the first inner electrode 32A-1 is connected to the heat-radiating conductor 36 on the upper surface side, and the side edge is one side. Further, one side edge as the common internal electrode 33-1 is exposed on one side surface in the yy direction of the laminated chip 31, and the upper edge is laminated. Inside position away from the top surface of the chip 31 Adopted what is, lies in connecting the 1-side edge of the common internal electrodes 33-1 to heat conductor portion 37-1 of one side surface side. The manufacturing method and function are the same as those of the multilayer ceramic capacitor 30.

この積層セラミックコンデンサ30−1によれば、積層セラミックコンデンサ30−1の熱を一方の第1内部電極32A−1から上面側の放熱導体部36に伝え、他方の第1内部電極32Bから側面側の一方の放熱導体部37−1に伝え、共通内部電極33−1から側面側の他方の放熱導体部37−1に伝えることにより、前記積層セラミックコンデンサ30と同様の放熱効果を得ることができる。この場合の上面側の放熱導体部36は、積層チップ31の上面とx−x方向の1側面に連続して、または、積層チップ31の上面とx−x方向の2側面に連続して設けられていてもよく、一方、側面側の各放熱導体部37−1は積層チップ31のy−y方向の1側面とx−x方向の1側面に連続して、または、積層チップ31のy−y方向の1側面とx−x方向の2側面に連続して設けられていてもよい。   According to the multilayer ceramic capacitor 30-1, the heat of the multilayer ceramic capacitor 30-1 is transmitted from one first internal electrode 32A-1 to the heat-radiating conductor 36 on the upper surface side, and from the other first internal electrode 32B to the side surface side. The heat radiation effect similar to that of the multilayer ceramic capacitor 30 can be obtained by transmitting to one heat radiation conductor portion 37-1 and transmitting from the common internal electrode 33-1 to the other heat radiation conductor portion 37-1. . In this case, the heat-radiating conductor 36 on the upper surface side is continuously provided on the upper surface of the multilayer chip 31 and one side surface in the xx direction, or continuously on the upper surface of the multilayer chip 31 and two side surfaces in the xx direction. On the other hand, each of the heat radiation conductors 37-1 on the side surface side is continuous with one side surface in the y-y direction and one side surface in the xx direction of the multilayer chip 31, or y of the multilayer chip 31. It may be provided continuously on one side surface in the −y direction and two side surfaces in the xx direction.

図36〜図37は第2構造変形例を示すもので、この積層セラミックコンデンサ30−2が前記積層セラミックコンデンサ30と異なるところは、積層チップ31の上面に2つの放熱導体部36−1を離隔して設け、2つの放熱導体部37−1を積層チップ31のy−y方向の2側面に第1外部電極34と非接触でそれぞれ設けると共に、第1内部電極32A−1,32B−1としてその上縁が積層チップ31の上面に露出し、且つ、その側縁が積層チップ31のy−y方向の1側面に露出したものを採用して、各第1内部電極32A−1,32B−1の上縁を上面側の放熱導体部36−1にそれぞれ接続し、さらに、共通内部電極33−2としてその両側縁が積層チップ31のy−y方向の2側面に露出し、且つ、その上縁が積層チップ31の上面から離れた内側位置にあるものを採用して、該共通内部電極33−2の側縁を放熱導体部37−1にそれぞれ接続した点にある。製法及び機能は前記積層セラミックコンデンサ30と同様である。   FIG. 36 to FIG. 37 show a second structural modification example. This multilayer ceramic capacitor 30-2 is different from the multilayer ceramic capacitor 30 in that the two radiating conductor portions 36-1 are separated on the upper surface of the multilayer chip 31. FIG. The two heat radiating conductors 37-1 are provided on the two side surfaces in the y-y direction of the multilayer chip 31 in a non-contact manner with the first external electrode 34, respectively, and as the first internal electrodes 32A-1 and 32B-1 The first inner electrodes 32A-1, 32B- are formed by using the one whose upper edge is exposed on the upper surface of the multilayer chip 31 and whose side edge is exposed on one side surface in the yy direction of the multilayer chip 31. 1 is connected to the heat-radiating conductor 36-1 on the upper surface side, and both side edges of the common internal electrode 33-2 are exposed on the two side surfaces in the yy direction of the laminated chip 31, and The upper edge is a laminated chip 3 Adopted what is inside position apart from the upper surface, lies in that connected to the side edges of the common internal electrodes 33-2 to heat conductor portion 37-1. The manufacturing method and function are the same as those of the multilayer ceramic capacitor 30.

この積層セラミックコンデンサ30−2によれば、積層セラミックコンデンサ30−2の熱を一方の第1内部電極32A−1から上面側の一方の放熱導体部36−1に伝え、他方の第1内部電極32B−1から上面側の他方の放熱導体部36−1に伝え、共通内部電極33−1から側面側の両方の放熱導体部37−1に伝えることにより、前記積層セラミックコンデンサ30と同様の放熱効果を得ることができる。この場合の上面側の放熱導体部36−1は、積層チップ31の上面とx−x方向の1側面に連続して、または、積層チップ31の上面とx−x方向の2側面に連続して設けられていてもよく、一方、側面側の各放熱導体部37−1は積層チップ31のy−y方向の1側面とx−x方向の1側面に連続して、または、積層チップ31のy−y方向の1側面とx−x方向の2側面に連続して設けられていてもよい。   According to this multilayer ceramic capacitor 30-2, the heat of the multilayer ceramic capacitor 30-2 is transferred from one first internal electrode 32A-1 to one heat radiating conductor 36-1 on the upper surface side, and the other first internal electrode The heat radiation similar to that of the multilayer ceramic capacitor 30 is transmitted from 32B-1 to the other heat radiating conductor portion 36-1 on the upper surface side and from the common internal electrode 33-1 to both heat radiating conductor portions 37-1 on the side surface side. An effect can be obtained. In this case, the heat radiation conductor 36-1 on the upper surface side is continuous with the upper surface of the multilayer chip 31 and one side surface in the xx direction, or is continuous with the upper surface of the multilayer chip 31 and two side surfaces in the xx direction. On the other hand, each heat radiation conductor 37-1 on the side surface side is continuous with one side surface in the yy direction and one side surface in the xx direction of the multilayer chip 31, or the multilayer chip 31. May be provided continuously on one side surface in the y-y direction and two side surfaces in the xx direction.

[第4実施形態]
図38〜図40は本発明の第4実施形態を示す。図38は積層セラミックコンデンサの上面側から見た斜視図、図39(A)及び図39(B)は図38に示した積層セラミックコンデンサをy−y方向と平行で位置が異なる2つのラインで切断した縦断面図、図40(A)〜図40(C)は図38に示した積層セラミックコンデンサの製法説明図である。
[Fourth Embodiment]
38 to 40 show a fourth embodiment of the present invention. FIG. 38 is a perspective view seen from the upper surface side of the multilayer ceramic capacitor, and FIGS. 39A and 39B are views of the multilayer ceramic capacitor shown in FIG. 38 in two lines parallel to the y-y direction and different in position. FIG. 40 (A) to FIG. 40 (C), which are cut longitudinal sectional views, are diagrams for explaining a method of manufacturing the multilayer ceramic capacitor shown in FIG.

第4実施形態の積層セラミックコンデンサ40は、直方体形状を成す積層チップ41を備える。この積層チップ41は、同一層に存する2つの第1内部電極42A,42Bと、第1内部電極42A,42Bが存する層とは異なる層に存する2つの第2内部電極43とが、セラミック層(符号無し)を介して交互に、且つ、対向して配された構成を有する。第1内部電極42A,42Bが存する層の数と第2内部電極43が存する層の数は必要とする静電容量に応じて任意に設定される。   The multilayer ceramic capacitor 40 of the fourth embodiment includes a multilayer chip 41 having a rectangular parallelepiped shape. This laminated chip 41 includes two first internal electrodes 42A and 42B in the same layer and two second internal electrodes 43 in a layer different from the layer in which the first internal electrodes 42A and 42B exist. And a configuration in which they are arranged alternately and face each other. The number of layers in which the first internal electrodes 42A and 42B exist and the number of layers in which the second internal electrodes 43 exist are arbitrarily set according to the required capacitance.

図39(A)に示すように、2つの第1内部電極42A,42Bはそれぞれ縦長長方形を成し、両者間には所定の間隙が設けられている。一方の第1内部電極42Aはその下端一側に所定幅の引出部42Aaを有し、該引出部42Aaの下縁は積層チップ41の下面に露出している。また、一方の第1内部電極42Aの上縁は積層チップ41の上面に露出しており、側縁は積層チップ41のy−y方向の1側面から離れた内側位置にある。他方の第1内部電極42Bはその下端一側に所定幅の引出部42Baを有し、該引出部42Baの下縁は積層チップ41の下面に露出している。また、他方の第1内部電極42Bの上縁は積層チップ41の上面から離れた内側位置にあり、側縁は積層チップ41のy−y方向の1側面から離れた内側位置にある。   As shown in FIG. 39A, the two first internal electrodes 42A and 42B each have a vertically long rectangle, and a predetermined gap is provided between them. One first internal electrode 42 </ b> A has a leading portion 42 </ b> Aa having a predetermined width on one lower end side, and the lower edge of the leading portion 42 </ b> Aa is exposed on the lower surface of the multilayer chip 41. The upper edge of one first internal electrode 42A is exposed on the upper surface of the multilayer chip 41, and the side edge is at an inner position away from one side surface of the multilayer chip 41 in the yy direction. The other first internal electrode 42 </ b> B has a lead portion 42 </ b> Ba having a predetermined width on one lower end side, and the lower edge of the lead portion 42 </ b> Ba is exposed on the lower surface of the multilayer chip 41. The upper edge of the other first internal electrode 42B is at an inner position away from the upper surface of the multilayer chip 41, and the side edge is at an inner position away from one side surface of the multilayer chip 41 in the yy direction.

図39(B)に示すように、2つの第2内部電極43はそれぞれ縦長長方形を成し、両者間には所定の間隙が設けられている。各第2内部電極43はその下端一側に所定幅の引出部43aを有し、該引出部43aの下縁は積層チップ41の下面に引出部42Aa,42Baと非接触で露出している。また、各第2内部電極43の上縁は積層チップ41の上面から離れた内側位置にあり、側縁は積層チップ41のy−y方向の1側面から離れた内側位置にある。   As shown in FIG. 39B, the two second internal electrodes 43 each have a vertically long rectangle, and a predetermined gap is provided between them. Each second internal electrode 43 has a lead portion 43a having a predetermined width on one lower end side, and the lower edge of the lead portion 43a is exposed on the lower surface of the laminated chip 41 in a non-contact manner with the lead portions 42Aa and 42Ba. Further, the upper edge of each second internal electrode 43 is at an inner position away from the upper surface of the multilayer chip 41, and the side edge is at an inner position away from one side surface of the multilayer chip 41 in the yy direction.

積層チップ41の下面には2つの第1外部電極44がx−x方向に帯状に設けられ、第1外部電極46と間隔をおいて交互に並ぶように2つの第2外部電極45がx−x方向に帯状に設けられている。図39(A)から分かるように一方の第1内部電極42Aの引出部42Aaの下縁は一方の第1外部電極44に接続し、他方の第1内部電極42Bの引出部42Baの下縁は他方の第1外部電極44に接続している。図39(B)から分かるように一方の第2内部電極43の引出部43aの下縁は一方の第2外部電極45に接続し、他方の第2内部電極43の引出部43aの下縁は他方の第2外部電極45に接続している。   Two first external electrodes 44 are provided in a strip shape in the xx direction on the lower surface of the multilayer chip 41, and the two second external electrodes 45 are arranged in an x− direction so as to be alternately arranged with a distance from the first external electrode 46. It is provided in a strip shape in the x direction. As can be seen from FIG. 39A, the lower edge of the lead portion 42Aa of one first inner electrode 42A is connected to one first outer electrode 44, and the lower edge of the lead portion 42Ba of the other first inner electrode 42B is The other first external electrode 44 is connected. As can be seen from FIG. 39B, the lower edge of the lead portion 43a of one second internal electrode 43 is connected to one second external electrode 45, and the lower edge of the lead portion 43a of the other second internal electrode 43 is The other second external electrode 45 is connected.

また、積層チップ41の上面には該上面全体を覆うように放熱導体部46が設けられている。図39(A)から分かるように一方の第1内部電極42Aの上縁は放熱導体部46に接続している。   Further, a heat radiating conductor portion 46 is provided on the upper surface of the multilayer chip 41 so as to cover the entire upper surface. As can be seen from FIG. 39A, the upper edge of one first internal electrode 42A is connected to the heat radiating conductor 46.

前記積層セラミックコンデンサ40を製造するに際しては、まず、チタン酸バリウム等の誘電体粉末を含有した未焼成セラミックシートの一面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して第1内部電極42A用の未焼成内部電極C41Aと第1内部電極42B用の未焼成内部電極C41Bを形成した第1シートS41(図40(A)参照)と、未焼成セラミックシートの一面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して第2内部電極43用の2つの未焼成内部電極C42を形成した第2シートS42(図40(B)参照)とを交互に所定枚数積み重ねて、未焼成内部電極を形成していない未焼成セラミックシートから成るダミーシートS43(図40(C)参照)をその両側に重ね合わせて全体を熱圧着し、これを焼成する。図40には1部品に対応した大きさの未焼成セラミックシートを示したが、実際上は多数個取りを可能とした大きさの未焼成セラミックシートを用いて積層圧着後にこれを部品寸法に切断して焼成することで積層チップ41を得る。   In manufacturing the multilayer ceramic capacitor 40, first, a conductor paste containing a metal powder such as silver or nickel is printed on one surface of an unfired ceramic sheet containing a dielectric powder such as barium titanate. The first sheet S41 (see FIG. 40A) on which the unfired internal electrode C41A for the electrode 42A and the unfired internal electrode C41B for the first internal electrode 42B are formed, and silver, nickel, etc. on one surface of the unfired ceramic sheet The second sheet S42 (see FIG. 40B) on which the conductive paste containing the metal powder is printed to form the two unfired internal electrodes C42 for the second internal electrodes 43 is alternately stacked a predetermined number of times, A dummy sheet S43 (see FIG. 40C) made of an unfired ceramic sheet on which unfired internal electrodes are not formed is superposed on both sides, and the whole is hot-pressed. And, I fired it. FIG. 40 shows an unfired ceramic sheet of a size corresponding to one part. In practice, however, an unfired ceramic sheet of a size that allows multiple pieces is used, and this is cut into component dimensions after laminating and pressing. Then, the laminated chip 41 is obtained by firing.

次に、焼成により得られた積層チップ41の上面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して未焼成放熱導体部(図示省略)を形成し、且つ、積層チップ41の下面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して2つの未焼成第1外部電極(図示省略)と2つの未焼成第2外部電極(図示省略)を形成し、これらに焼き付け処理を施す。勿論、未焼成放熱導体部,未焼成第1外部電極及び未焼成第2外部電極の焼き付け処理は積層チップの焼成処理と同時に行うこともできる。   Next, a conductive paste containing metal powder such as silver or nickel is printed on the upper surface of the laminated chip 41 obtained by firing to form an unfired heat radiating conductor (not shown), and the lower surface of the laminated chip 41 A conductive paste containing a metal powder such as silver or nickel is printed on the substrate to form two unfired first external electrodes (not shown) and two unfired second external electrodes (not shown), and these are baked. Apply. Of course, the baking process of the unsintered heat radiation conductor part, the unsintered first external electrode and the unsintered second external electrode can be performed simultaneously with the firing process of the laminated chip.

第4実施形態の積層セラミックコンデンサ40は、一方の第1外部電極44と一方の第2外部電極45との間に一方の第1内部電極42Aと一方の第2内部電極43との対向面積及び積層数に準じた所定の静電容量を得ることができ、他方の第1外部電極44と他方の第2外部電極45との間に他方の第1内部電極42Bと他方の第2内部電極43との対向面積及び積層数に準じた所定の静電容量を得ることができる。つまり、積層セラミックコンデンサ40を2つのコンデンサが組み合わされたコンデンサアレイとして使用することができる。勿論、2つのコンデンサの静電容量の和に等しい静電容量を2つの第1外部電極44と2つの第2外部電極45との間で得ることも可能である。   The multilayer ceramic capacitor 40 according to the fourth embodiment includes an opposing area between one first internal electrode 42A and one second internal electrode 43 between one first external electrode 44 and one second external electrode 45. A predetermined capacitance according to the number of stacked layers can be obtained, and the other first internal electrode 42B and the other second internal electrode 43 are provided between the other first external electrode 44 and the other second external electrode 45. A predetermined capacitance according to the facing area and the number of stacked layers can be obtained. That is, the multilayer ceramic capacitor 40 can be used as a capacitor array in which two capacitors are combined. Of course, a capacitance equal to the sum of the capacitances of the two capacitors can be obtained between the two first external electrodes 44 and the two second external electrodes 45.

この積層セラミックコンデンサ40にあっては、2つの第1内部電極42A,42Bと2つの第2内部電極43との間に不要な導体層が存しないため、つまり、図1〜図3に示した従来の積層セラミックコンデンサのように隣接する内部電極1間それぞれに内部電極1とは別の放熱用内部電極5が存しないため、一方の第1外部電極44と一方の第2外部電極45との間と、他方の第1外部電極44と他方の第2外部電極45との間に、所期の静電容量を安定して確保することができる。   In this multilayer ceramic capacitor 40, an unnecessary conductor layer does not exist between the two first internal electrodes 42A and 42B and the two second internal electrodes 43, that is, as shown in FIGS. Since there is no heat dissipating internal electrode 5 different from the internal electrode 1 between the adjacent internal electrodes 1 as in the conventional multilayer ceramic capacitor, there is no difference between one first external electrode 44 and one second external electrode 45. A desired electrostatic capacity can be stably ensured between the first external electrode 44 and the second external electrode 45 on the other side.

また、この積層セラミックコンデンサ40にあっては、実装後の積層セラミックコンデンサ40への電圧印加時に各内部電極42A,42B,43で熱が発生すると、また、実装基板からの熱が各外部電極44,45から各内部電極42A,42B,43に伝わると、この熱は一方の第1内部電極42Aから放熱導体部46に直接的に伝わって該放熱導体部46から外部に放出される。要するに、積層セラミックコンデンサ40を熱を直接的に、且つ、高効率で放熱導体部46に伝えることにより、コンデンサ自体の熱を効果的に外部に放出してその温度上昇を確実に抑制することができる。しかも、放熱導体部46に十分な面積が確保できるので前記の熱放出をより効果的に行うことができる。   In the multilayer ceramic capacitor 40, when heat is generated in each of the internal electrodes 42A, 42B, 43 when a voltage is applied to the multilayer ceramic capacitor 40 after mounting, the heat from the mounting substrate is also transferred to each external electrode 44. , 45 is transmitted to the internal electrodes 42A, 42B, 43 from the one first internal electrode 42A directly to the heat radiating conductor 46 and released from the heat radiating conductor 46 to the outside. In short, by transferring heat to the multilayer ceramic capacitor 40 directly and with high efficiency to the heat radiating conductor portion 46, it is possible to effectively release the heat of the capacitor itself to the outside and reliably suppress the temperature rise. it can. In addition, since a sufficient area can be secured in the heat radiating conductor 46, the heat release can be performed more effectively.

尚、図38〜図40には同一層に2つの第1内部電極42A,42Bを設け、これとは異なる層に2つの第2内部電極43を設けたものを示したが、同一層に3以上の第1内部電極を設け、これとは異なる層に3以上の第2内部電極を各第1内部電極と対向するように設ければ、3以上のコンデンサが組み合わされたコンデンサアレイとして構成することもできる。第1内部電極及び第2内部電極を3以上設ける場合には第1内部電極及び第2内部電極の数に応じて外部電極の数は増加することになる。   In FIGS. 38 to 40, two first internal electrodes 42A and 42B are provided in the same layer and two second internal electrodes 43 are provided in a different layer. If the above first internal electrodes are provided and three or more second internal electrodes are provided on a different layer so as to face each first internal electrode, a capacitor array in which three or more capacitors are combined is configured. You can also When three or more first internal electrodes and second internal electrodes are provided, the number of external electrodes increases according to the number of first internal electrodes and second internal electrodes.

また、図38〜図40には一方の第1内部電極42Aと一方の第2内部電極43とを対向させ、且つ、他方の第1内部電極42Bと他方の第2内部電極43とを対向させたものを示したが、例えば図41に示した積層セラミックコンデンサ40’のように一方の第1内部電極42A’の幅を小さくし他方の第1内部電極42B’の幅を大きくして他方の第1内部電極42B’が2つの第2内部電極43と向き合うように構成すれば、一方の第1外部電極44と一方の第2外部電極45との間で得られる静電容量と、他方の第1外部電極44と他方の第2外部電極45との間で得られる静電容量を変化させることもできる。この場合の放熱導体部46’は第1内部電極42B’または第1内部電極42Aに接続されていればよい。   38 to 40, one first internal electrode 42A and one second internal electrode 43 are opposed to each other, and the other first internal electrode 42B and the other second internal electrode 43 are opposed to each other. For example, like the multilayer ceramic capacitor 40 ′ shown in FIG. 41, the width of one first internal electrode 42A ′ is reduced and the width of the other first internal electrode 42B ′ is increased. If the first internal electrode 42B ′ is configured to face the two second internal electrodes 43, the capacitance obtained between one first external electrode 44 and one second external electrode 45, and the other The capacitance obtained between the first external electrode 44 and the other second external electrode 45 can also be changed. In this case, the heat radiating conductor portion 46 'may be connected to the first internal electrode 42B' or the first internal electrode 42A.

以下に、前記第4実施形態の構造変形例を図42〜図46を引用して説明する。   Hereinafter, structural modifications of the fourth embodiment will be described with reference to FIGS.

図42〜図43は第1構造変形例を示すもので、この積層セラミックコンデンサ40−1が前記積層セラミックコンデンサ40と異なるところは、放熱導体部46−1を積層チップ41のy−y方向の1側面に一方の第1外部電極44と接続するように設けると共に、一方の第1内部電極42A−1としてその上縁が積層チップ41の上面から離れた内側位置にあり、且つ、その側縁が積層チップ41のy−y方向の1側面に露出したものを採用して、該第1内部電極42a−1の側縁を放熱導体部46−1に接続した点にある。製法及び機能は前記積層セラミックコンデンサ40と同様である。   42 to 43 show a first structural modification example. The laminated ceramic capacitor 40-1 is different from the laminated ceramic capacitor 40 in that the radiating conductor portion 46-1 is arranged in the y-y direction of the laminated chip 41. FIG. It is provided on one side surface so as to be connected to one first external electrode 44, and the upper edge of one first internal electrode 42A-1 is at an inner position away from the upper surface of the laminated chip 41, and its side edge However, the one exposed on one side surface in the y-y direction of the multilayer chip 41 is adopted, and the side edge of the first internal electrode 42a-1 is connected to the heat radiating conductor 46-1. The manufacturing method and function are the same as those of the multilayer ceramic capacitor 40.

この積層セラミックコンデンサ40−1によれば、積層セラミックコンデンサ40−1の熱を直接的に、且つ、高効率で放熱導体部46−1に伝えることにより、前記積層セラミックコンデンサ40と同様の放熱効果を得ることができる。この場合の放熱導体部は、積層チップ41のy−y方向の1側面とx−x方向の1側面に連続して、または、積層チップ41のy−y方向の1側面とx−x方向の2側面に連続して、さらには、積層チップ41のy−y方向の1側面とx−x方向の2側面とy−y方向の残りの1側面に連続して設けられていてもよい。   According to the multilayer ceramic capacitor 40-1, the heat radiation effect similar to that of the multilayer ceramic capacitor 40 can be obtained by directly and efficiently transmitting the heat of the multilayer ceramic capacitor 40-1 to the heat radiating conductor 46-1. Can be obtained. In this case, the heat radiating conductor portion is continuous with one side surface in the yy direction and one side surface in the xx direction of the multilayer chip 41 or one side surface in the yy direction of the multilayer chip 41 and the xx direction. Further, the laminated chip 41 may be provided continuously on one side surface in the yy direction, two side surfaces in the xx direction, and one remaining side surface in the yy direction. .

図44〜図45は第2構造変形例を示すもので、この積層セラミックコンデンサ40−2が前記積層セラミックコンデンサ40と異なるところは、放熱導体部46−2を積層チップ41の上面とy−y方向の2側面に連続して設けた点にある。製法及び機能は前記積層セラミックコンデンサ40と同様である。   44 to 45 show a second structural modification example. The laminated ceramic capacitor 40-2 is different from the laminated ceramic capacitor 40 in that the radiating conductor portion 46-2 is connected to the upper surface of the laminated chip 41 and yy. It is in the point provided continuously on the two side surfaces of the direction. The manufacturing method and function are the same as those of the multilayer ceramic capacitor 40.

この積層セラミックコンデンサ40−2によれば、積層セラミックコンデンサ40−2の熱を直接的に、且つ、高効率で放熱導体部46−2に伝えることにより、前記積層セラミックコンデンサ40と同様の放熱効果を得ることができる。この場合の放熱導体部は、積層チップ41の上面とy−y方向の2側面とx−x方向の1側面に連続して、または、積層チップ41の上面とy−y方向の2側面とx−x方向の2側面に連続して設けられていてもよい。   According to the multilayer ceramic capacitor 40-2, the heat radiation effect similar to that of the multilayer ceramic capacitor 40 can be obtained by directly and efficiently transmitting the heat of the multilayer ceramic capacitor 40-2 to the heat radiation conductor 46-2. Can be obtained. In this case, the heat radiating conductor portion is continuous with the upper surface of the multilayer chip 41, two side surfaces in the yy direction, and one side surface in the xx direction, or the upper surface of the multilayer chip 41 and two side surfaces in the yy direction. It may be provided continuously on the two side surfaces in the xx direction.

図46は第3構造変形例を示すもので、この積層セラミックコンデンサ40−3が前記積層セラミックコンデンサ40と異なるところは、放熱導体部46−2を積層チップ41の上面とy−y方向の2側面に連続して設けると共に、一方の第1内部電極42A−2としてその側縁が積層チップ41のy−y方向の1側面に露出し、且つ、その上縁が積層チップ41の上面から離れた内側位置にあるものを採用して、該第1内部電極42A−2の側縁を放熱導体部46−2に接続した点にある。製法及び機能は前記積層セラミックコンデンサ40と同様である。   FIG. 46 shows a third structural modification example. This multilayer ceramic capacitor 40-3 is different from the multilayer ceramic capacitor 40 in that the heat radiating conductor portion 46-2 is connected to the top surface of the multilayer chip 41 in the yy direction. The first inner electrode 42 </ b> A- 2 is continuously provided on the side surface, and the side edge of the first internal electrode 42 </ b> A- 2 is exposed on one side surface in the yy direction of the multilayer chip 41, and the upper edge is separated from the upper surface of the multilayer chip 41. What is in the inner position is that the side edge of the first internal electrode 42A-2 is connected to the heat radiating conductor portion 46-2. The manufacturing method and function are the same as those of the multilayer ceramic capacitor 40.

この積層セラミックコンデンサ40−3によれば、積層セラミックコンデンサ40−3の熱を直接的に、且つ、高効率で放熱導体部46−2に伝えることにより、前記積層セラミックコンデンサ40と同様の放熱効果を得ることができる。この場合の放熱導体部は、積層チップ41の上面とy−y方向の2側面とx−x方向の1側面に連続して、または、積層チップ41の上面とy−y方向の2側面とx−x方向の2側面に連続して設けられていてもよい。   According to the multilayer ceramic capacitor 40-3, the heat dissipation effect similar to that of the multilayer ceramic capacitor 40 can be obtained by directly and efficiently transmitting the heat of the multilayer ceramic capacitor 40-3 to the heat radiating conductor portion 46-2. Can be obtained. In this case, the heat radiating conductor portion is continuous with the upper surface of the multilayer chip 41, two side surfaces in the yy direction, and one side surface in the xx direction, or the upper surface of the multilayer chip 41 and two side surfaces in the yy direction. It may be provided continuously on the two side surfaces in the xx direction.

[第5実施形態]
図47〜図49は本発明の第5実施形態を示す。図47は積層セラミックコンデンサの上面側から見た斜視図、図48(A)及び図48(B)は図47に示した積層セラミックコンデンサをy−y方向と平行で位置が異なる2つのラインで切断した縦断面図、図49(A)〜図49(C)は図47に示した積層セラミックコンデンサの製法説明図である。
[Fifth Embodiment]
47 to 49 show a fifth embodiment of the present invention. 47 is a perspective view seen from the upper surface side of the multilayer ceramic capacitor, and FIGS. 48A and 48B are views of the multilayer ceramic capacitor shown in FIG. 47 in two lines parallel to the y-y direction and having different positions. FIG. 49A to FIG. 49C are sectional views of the laminated ceramic capacitor shown in FIG.

第4実施形態の積層セラミックコンデンサ50は、直方体形状を成す積層チップ51を備える。この積層チップ51は、同一層に存する2つの第1内部電極52と、第1内部電極52が存する層とは異なる層に存する2つの第2内部電極53とが、セラミック層(符号無し)を介して交互に、且つ、対向して配された構成を有する。第1内部電極52が存する層の数と第2内部電極53が存する層の数は必要とする静電容量に応じて任意に設定される。   A multilayer ceramic capacitor 50 according to the fourth embodiment includes a multilayer chip 51 having a rectangular parallelepiped shape. In this multilayer chip 51, two first internal electrodes 52 that exist in the same layer and two second internal electrodes 53 that exist in a layer different from the layer in which the first internal electrode 52 exists include a ceramic layer (no symbol). Via each other and opposite to each other. The number of layers in which the first internal electrodes 52 exist and the number of layers in which the second internal electrodes 53 exist are arbitrarily set according to the required capacitance.

図48(A)に示すように、2つの第1内部電極52はそれぞれ縦長長方形を成し、両者間には所定の間隙が設けられている。各第1内部電極52はその下端一側に所定幅の引出部52aを有し、該引出部52aの下縁は積層チップ51の下面に露出している。また、各第1内部電極52の上縁は積層チップ51の上面に露出しており、側縁は積層チップ51のy−y方向の1側面から離れた内側位置にある。   As shown in FIG. 48A, the two first internal electrodes 52 each have a vertically long rectangle, and a predetermined gap is provided between them. Each first internal electrode 52 has a lead portion 52 a having a predetermined width on one lower end side, and the lower edge of the lead portion 52 a is exposed on the lower surface of the multilayer chip 51. Further, the upper edge of each first internal electrode 52 is exposed on the upper surface of the multilayer chip 51, and the side edge is at an inner position away from one side surface of the multilayer chip 51 in the yy direction.

図48(B)に示すように、2つの第2内部電極53はそれぞれ縦長長方形を成し、両者間には所定の間隙が設けられている。各第2内部電極53はその下端一側に所定幅の引出部53aを有し、該引出部53aの下縁は積層チップ51の下面に引出部52aと非接触で露出している。また、各第2内部電極53の上縁は積層チップ51の上面から離れた内側位置にあり、側縁は積層チップ51のy−y方向の1側面から離れた内側位置にある。   As shown in FIG. 48B, the two second internal electrodes 53 each have a vertically long rectangle, and a predetermined gap is provided between them. Each second internal electrode 53 has a leading portion 53a having a predetermined width on one lower end side, and the lower edge of the leading portion 53a is exposed on the lower surface of the multilayer chip 51 in a non-contact manner with the leading portion 52a. The upper edge of each second internal electrode 53 is at an inner position away from the upper surface of the multilayer chip 51, and the side edge is at an inner position away from one side surface of the multilayer chip 51 in the yy direction.

積層チップ51の下面には2つの第1外部電極54がx−x方向に帯状に設けられ、第1外部電極54と間隔をおいて交互に並ぶように2つの第2外部電極55がx−x方向に帯状に設けられている。図48(A)から分かるように一方の第1内部電極52の引出部52aの下縁は一方の第1外部電極54に接続し、他方の第1内部電極52の引出部52aの下縁は他方の第1外部電極54に接続している。図48(B)から分かるように一方の第2内部電極53の引出部53aの下縁は一方の第2外部電極55に接続し、他方の第2内部電極53の引出部53aの下縁は他方の第2外部電極54に接続している。   Two first external electrodes 54 are provided in a strip shape in the xx direction on the lower surface of the multilayer chip 51, and the two second external electrodes 55 are arranged in an alternating manner with the first external electrodes 54 at intervals. It is provided in a strip shape in the x direction. As can be seen from FIG. 48A, the lower edge of the lead portion 52a of one first internal electrode 52 is connected to one first external electrode 54, and the lower edge of the lead portion 52a of the other first internal electrode 52 is The other first external electrode 54 is connected. 48B, the lower edge of the lead portion 53a of one second internal electrode 53 is connected to one second external electrode 55, and the lower edge of the lead portion 53a of the other second internal electrode 53 is The other second external electrode 54 is connected.

また、積層チップ51の上面には2つの放熱導体部56が離隔して設けられている。図48(A)から分かるように一方の第1内部電極52の上縁は一方の放熱導体部56に接続し、他方の第1内部電極52の上縁は他方の放熱導体部56に接続している。   Further, two heat radiating conductors 56 are provided on the upper surface of the multilayer chip 51 so as to be separated from each other. As can be seen from FIG. 48A, the upper edge of one first internal electrode 52 is connected to one heat radiating conductor 56, and the upper edge of the other first internal electrode 52 is connected to the other heat radiating conductor 56. ing.

前記積層セラミックコンデンサ50を製造するに際しては、まず、チタン酸バリウム等の誘電体粉末を含有した未焼成セラミックシートの一面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して第1内部電極52用の2つの未焼成内部電極C51を形成した第1シートS51(図49(A)参照)と、未焼成セラミックシートの一面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して第2内部電極53用の2つの未焼成内部電極C52を形成した第2シートS52(図49(B)参照)とを交互に所定枚数積み重ねて、未焼成内部電極を形成していない未焼成セラミックシートから成るダミーシートS53(図49(C)参照)をその両側に重ね合わせて全体を熱圧着し、これを焼成する。図49には1部品に対応した大きさの未焼成セラミックシートを示したが、実際上は多数個取りを可能とした大きさの未焼成セラミックシートを用いて積層圧着後にこれを部品寸法に切断して焼成することで積層チップ51を得る。   When manufacturing the multilayer ceramic capacitor 50, first, a conductive paste containing a metal powder such as silver or nickel is printed on one surface of an unfired ceramic sheet containing a dielectric powder such as barium titanate. A first sheet S51 (see FIG. 49A) on which two unfired internal electrodes C51 for the electrode 52 are formed, and a conductor paste containing metal powder such as silver or nickel are printed on one surface of the unfired ceramic sheet. A predetermined number of second sheets S52 (see FIG. 49B) on which two unfired internal electrodes C52 for the second internal electrode 53 are formed are alternately stacked to form unfired internal electrodes. A dummy sheet S53 (see FIG. 49C) made of a ceramic sheet is superposed on both sides, and the whole is thermocompression bonded and fired. FIG. 49 shows an unfired ceramic sheet of a size corresponding to one part. However, in practice, an unfired ceramic sheet of a size that can be picked up in large numbers is used, and this is cut into component dimensions after laminating and pressing. Then, the laminated chip 51 is obtained by firing.

次に、焼成により得られた積層チップ51の上面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して2つの未焼成放熱導体部(図示省略)を形成し、且つ、積層チップ51の下面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して2つの未焼成第1外部電極(図示省略)と2つの未焼成第2外部電極(図示省略)を形成し、これらに焼き付け処理を施す。勿論、未焼成放熱導体部,未焼成第1外部電極及び未焼成第2外部電極の焼き付け処理は積層チップの焼成処理と同時に行うこともできる。   Next, a conductive paste containing metal powder such as silver or nickel is printed on the upper surface of the laminated chip 51 obtained by firing to form two unfired heat radiating conductor portions (not shown), and the laminated chip 51 A conductor paste containing a metal powder such as silver or nickel is printed on the lower surface of the substrate to form two unfired first external electrodes (not shown) and two unfired second external electrodes (not shown). A baking process is performed. Of course, the baking process of the unsintered heat radiation conductor part, the unsintered first external electrode and the unsintered second external electrode can be performed simultaneously with the firing process of the laminated chip.

第5実施形態の積層セラミックコンデンサ50は、一方の第1外部電極54と一方の第2外部電極55との間に一方の第1内部電極52と一方の第2内部電極53との対向面積及び積層数に準じた所定の静電容量を得ることができ、他方の第1外部電極54と他方の第2外部電極55との間に他方の第1内部電極52と他方の第2内部電極53との対向面積及び積層数に準じた所定の静電容量を得ることができる。つまり、積層セラミックコンデンサ50を2つのコンデンサが組み合わされたコンデンサアレイとして使用することができる。勿論、2つのコンデンサの静電容量の和に等しい静電容量を2つの第1外部電極54と2つの第2外部電極55との間で得ることも可能である。   The multilayer ceramic capacitor 50 according to the fifth embodiment includes an opposing area between one first internal electrode 52 and one second internal electrode 53 between one first external electrode 54 and one second external electrode 55. A predetermined capacitance according to the number of stacked layers can be obtained, and the other first internal electrode 52 and the other second internal electrode 53 are provided between the other first external electrode 54 and the other second external electrode 55. A predetermined capacitance according to the facing area and the number of stacked layers can be obtained. That is, the multilayer ceramic capacitor 50 can be used as a capacitor array in which two capacitors are combined. Of course, a capacitance equal to the sum of the capacitances of the two capacitors can be obtained between the two first external electrodes 54 and the two second external electrodes 55.

この積層セラミックコンデンサ50にあっては、2つの第1内部電極52と2つの第2内部電極53との間に不要な導体層が存しないため、つまり、図1〜図3に示した従来の積層セラミックコンデンサのように隣接する内部電極1間それぞれに内部電極1とは別の放熱用内部電極5が存しないため、一方の第1外部電極54と一方の第2外部電極55との間と、他方の第1外部電極54と他方の第2外部電極55との間に、所期の静電容量を安定して確保することができる。   In this multilayer ceramic capacitor 50, an unnecessary conductor layer does not exist between the two first internal electrodes 52 and the two second internal electrodes 53, that is, the conventional ceramic capacitor 50 shown in FIGS. Since there is no heat radiating internal electrode 5 different from the internal electrode 1 between the adjacent internal electrodes 1 as in the case of a multilayer ceramic capacitor, between one first external electrode 54 and one second external electrode 55 The desired capacitance can be stably ensured between the other first external electrode 54 and the other second external electrode 55.

また、この積層セラミックコンデンサ50にあっては、実装後の積層セラミックコンデンサ50への電圧印加時に各内部電極52,53で熱が発生すると、また、実装基板からの熱が各外部電極54,55から各内部電極52,53に伝わると、この熱は各第1内部電極52から各放熱導体部56に直接的に伝わって該放熱導体部56から外部に放出される。要するに、積層セラミックコンデンサ50を熱を直接的に、且つ、高効率で放熱導体部56に伝えることにより、コンデンサ自体の熱を効果的に外部に放出してその温度上昇を確実に抑制することができる。しかも、放熱導体部56に十分な面積が確保できるので前記の熱放出をより効果的に行うことができる。   In the multilayer ceramic capacitor 50, when heat is generated in the internal electrodes 52 and 53 when a voltage is applied to the multilayer ceramic capacitor 50 after mounting, the heat from the mounting substrate is also transferred to the external electrodes 54 and 55. When the heat is transmitted from the first internal electrodes 52 to the internal electrodes 52, 53, the heat is directly transmitted from the first internal electrodes 52 to the heat radiating conductors 56 and released from the heat radiating conductors 56 to the outside. In short, by transferring heat to the multilayer ceramic capacitor 50 directly and with high efficiency to the heat radiating conductor 56, it is possible to effectively release the heat of the capacitor itself to the outside and reliably suppress the temperature rise. it can. In addition, since a sufficient area can be secured in the heat radiating conductor portion 56, the heat release can be performed more effectively.

尚、図47〜図49には同一層に2つの第1内部電極52を設け、これとは異なる層に2つの第2内部電極53を設けたものを示したが、同一層に3以上の第1内部電極を設け、これとは異なる層に3以上の第2内部電極を各第1内部電極と対向するように設ければ、3以上のコンデンサが組み合わされたコンデンサアレイとして構成することもできる。第1内部電極及び第2内部電極を3以上設ける場合には第1内部電極及び第2内部電極の数に応じて外部電極の数は増加することになる。   47 to 49, two first internal electrodes 52 are provided in the same layer, and two second internal electrodes 53 are provided in a different layer, but three or more are provided in the same layer. If a first internal electrode is provided and three or more second internal electrodes are provided on a different layer so as to face each first internal electrode, a capacitor array in which three or more capacitors are combined may be configured. it can. When three or more first internal electrodes and second internal electrodes are provided, the number of external electrodes increases according to the number of first internal electrodes and second internal electrodes.

以下に、前記第5実施形態の構造変形例を図50〜図56を引用して説明する。   Hereinafter, structural modifications of the fifth embodiment will be described with reference to FIGS. 50 to 56.

図50〜図51は第1構造変形例を示すもので、この積層セラミックコンデンサ50−1が前記積層セラミックコンデンサ50と異なるところは、2つの放熱導体部56−1を積層チップ51のy−y方向の2側面に第1外部電極54と接続するようにそれぞれ設けると共に、一方の第1内部電極52−1としてその上縁が積層チップ51の上面から離れた内側位置にあり、且つ、その側縁が積層チップ51のy−y方向の1側面に露出したものを採用して、該第1内部電極52−1の側縁を一方の放熱導体部56−1に接続し、さらに、他方の第1内部電極52−2としてその上縁が積層チップ51の上面から離れた内側位置にあり、且つ、その側縁が積層チップ51のy−y方向の1側面に露出したものを採用して、該第1内部電極52−2の側縁を他方の放熱導体部56−1に接続した点と、2つの第1外部電極54の間に2つの第2外部電極55を間隔をおいて設けた点にある。製法及び機能は前記積層セラミックコンデンサ50と同様である。   50 to 51 show a first structural modification example. The laminated ceramic capacitor 50-1 is different from the laminated ceramic capacitor 50 in that two radiating conductor portions 56-1 are connected to the y-y of the laminated chip 51. FIG. Are provided so as to be connected to the first external electrode 54 on the two side surfaces in the direction, and the upper edge of the first internal electrode 52-1 is located at the inner position away from the upper surface of the multilayer chip 51, and the side The one whose edge is exposed on one side surface in the y-y direction of the multilayer chip 51 is adopted, the side edge of the first internal electrode 52-1 is connected to one heat radiation conductor portion 56-1, and the other As the first internal electrode 52-2, an electrode whose upper edge is at an inner position away from the upper surface of the multilayer chip 51 and whose side edge is exposed on one side surface in the yy direction of the multilayer chip 51 is adopted. The first internal electrode 52 A point of connecting the second side edge to the other heat conductor portion 56-1 is a two second external electrodes 55 between the two first outer electrode 54 in that spaced apart. The manufacturing method and function are the same as those of the multilayer ceramic capacitor 50.

この積層セラミックコンデンサ50−1によれば、積層セラミックコンデンサ50−1の熱を直接的に、且つ、高効率で放熱導体部56−1に伝えることにより、前記積層セラミックコンデンサ50と同様の放熱効果を得ることができる。この場合の各放熱導体部は、積層チップ51のy−y方向の1側面とx−x方向の1側面に連続して、または、積層チップ51のy−y方向の1側面とx−x方向の2側面に連続して設けられていてもよい。   According to the multilayer ceramic capacitor 50-1, the heat dissipation effect similar to that of the multilayer ceramic capacitor 50 is achieved by directly and efficiently transmitting the heat of the multilayer ceramic capacitor 50-1 to the heat dissipation conductor portion 56-1. Can be obtained. In this case, each radiating conductor portion is continuous with one side surface in the yy direction and one side surface in the xx direction of the multilayer chip 51 or one side surface in the yy direction of the multilayer chip 51 and xx. It may be provided continuously on the two side surfaces in the direction.

図52は第2構造変形例を示すもので、この積層セラミックコンデンサ50−2が前記積層セラミックコンデンサ50と異なるところは、2つの放熱導体部56−1を積層チップ51のy−y方向の2側面に第1外部電極54と接続するようにそれぞれ設けると共に、一方の第1内部電極52−3としてその上縁が積層チップ51の上面から離れた内側位置にあり、且つ、その側縁が積層チップ51のy−y方向の1側面から離れた内側位置にあるものを採用し、さらに、他方の第1内部電極52−4としてその上縁が積層チップ51の上面から離れた内側位置にあり、且つ、その側縁が積層チップ51のy−y方向の1側面から離れた内側位置にあるものを採用した点と、2つの第1外部電極54の間に2つの第2外部電極55を間隔をおいて設けた点にある。製法及び機能は前記積層セラミックコンデンサ50と同様である。   FIG. 52 shows a second structural modification example. This multilayer ceramic capacitor 50-2 is different from the multilayer ceramic capacitor 50 in that two radiating conductor portions 56-1 are arranged in the y-y direction of the multilayer chip 51. Each side surface is provided so as to be connected to the first external electrode 54, and the upper edge of the first internal electrode 52-3 is located at an inner position away from the upper surface of the multilayer chip 51, and the side edge is laminated. The chip 51 has an inner position away from one side surface in the y-y direction, and the upper edge of the other first internal electrode 52-4 is at an inner position away from the upper surface of the multilayer chip 51. In addition, two second external electrodes 55 are provided between the two first external electrodes 54 and the point that the side edge is located at an inner position away from one side surface in the y-y direction of the multilayer chip 51. Interval Lies in that provided Te. The manufacturing method and function are the same as those of the multilayer ceramic capacitor 50.

この積層セラミックコンデンサ50−2によれば、積層セラミックコンデンサ50−2の熱を直接的に、且つ、高効率で放熱導体部56−1に伝えることにより、前記積層セラミックコンデンサ50と同様の放熱効果を得ることができる。この場合の各放熱導体部は、積層チップ51のy−y方向の1側面とx−x方向の1側面に連続して、または、積層チップ51のy−y方向の1側面とx−x方向の2側面に連続して設けられていてもよい。   According to the multilayer ceramic capacitor 50-2, the heat radiation effect similar to that of the multilayer ceramic capacitor 50 is achieved by directly and efficiently transmitting the heat of the multilayer ceramic capacitor 50-2 to the heat radiation conductor portion 56-1. Can be obtained. In this case, each radiating conductor portion is continuous with one side surface in the yy direction and one side surface in the xx direction of the multilayer chip 51 or one side surface in the yy direction of the multilayer chip 51 and xx. It may be provided continuously on the two side surfaces in the direction.

図53〜図54は第3構造変形例を示すもので、この積層セラミックコンデンサ50−3が前記積層セラミックコンデンサ50と異なるところは、2つの放熱導体部56−2を積層チップ51の上面とy−y方向の1側面に連続し、且つ、第1外部電極54と接続するようにそれぞれ設けた点と、2つの第1外部電極54の間に2つの第2外部電極55を間隔をおいて設けた点にある。製法及び機能は前記積層セラミックコンデンサ10と同様である。   53 to 54 show a third structural modification example. The laminated ceramic capacitor 50-3 is different from the laminated ceramic capacitor 50 in that two heat radiating conductor portions 56-2 are connected to the upper surface of the laminated chip 51 and y. Two second external electrodes 55 are spaced between two first external electrodes 54 and a point provided so as to be connected to the first external electrode 54 continuously on one side surface in the −y direction. It is in the point provided. The manufacturing method and function are the same as those of the multilayer ceramic capacitor 10.

この積層セラミックコンデンサ50−3によれば、積層セラミックコンデンサ50−3の熱を直接的に、且つ、高効率で放熱導体部56−2に伝えることにより、前記積層セラミックコンデンサ50と同様の放熱効果を得ることができる。この場合の各放熱導体部は、積層チップ51の上面とy−y方向の1側面とx−x方向の1側面に連続して、または、積層チップ51の上面とy−y方向の1側面とx−x方向の2側面に連続して設けられていてもよい。   According to the multilayer ceramic capacitor 50-3, the heat dissipation effect similar to that of the multilayer ceramic capacitor 50 is achieved by directly and efficiently transmitting the heat of the multilayer ceramic capacitor 50-3 to the heat radiating conductor portion 56-2. Can be obtained. In this case, each radiating conductor portion is continuous with the upper surface of the multilayer chip 51, one side surface in the yy direction, and one side surface in the xx direction, or the upper surface of the multilayer chip 51 and one side surface in the yy direction. And may be provided continuously on two side surfaces in the xx direction.

図55は第4構造変形例を示すもので、この積層セラミックコンデンサ50−4が前記積層セラミックコンデンサ50と異なるところは、2つの放熱導体部56−2を積層チップ51の上面とy−y方向の1側面に連続し、且つ、第1外部電極54と接続するようにそれぞれ設けると共に、一方の第1内部電極52−1としてその上縁が積層チップ51の上面から離れた内側位置にあり、且つ、その側縁が積層チップ51のy−y方向の1側面に露出したものを採用して、該第1内部電極52−1の側縁を一方の放熱導体部56−2に接続し、さらに、他方の第1内部電極52−2としてその上縁が積層チップ51の上面から離れた内側位置にあり、且つ、その側縁が積層チップ51のy−y方向の1側面に露出したものを採用して、該第1内部電極52−2の側縁を他方の放熱導体部56−2に接続した点と、2つの第1外部電極54の間に2つの第2外部電極55を間隔をおいて設けた点にある。製法及び機能は前記積層セラミックコンデンサ50と同様である。   FIG. 55 shows a fourth structural modification example. This multilayer ceramic capacitor 50-4 is different from the multilayer ceramic capacitor 50 in that two radiating conductor portions 56-2 are arranged on the top surface of the multilayer chip 51 in the yy direction. Are provided so as to be connected to the first external electrode 54 and to be connected to the first external electrode 54, and the upper edge of the first internal electrode 52-1 is located at an inner position away from the upper surface of the multilayer chip 51, In addition, the one whose side edge is exposed on one side surface in the y-y direction of the multilayer chip 51 is adopted, and the side edge of the first internal electrode 52-1 is connected to one heat radiation conductor part 56-2, Furthermore, as the other first internal electrode 52-2, the upper edge is at an inner position away from the upper surface of the multilayer chip 51, and the side edge is exposed on one side surface of the multilayer chip 51 in the yy direction. Adopting the first The side edge of the partial electrode 52-2 is connected to the other heat radiating conductor portion 56-2, and two second external electrodes 55 are provided between the two first external electrodes 54 with a space therebetween. . The manufacturing method and function are the same as those of the multilayer ceramic capacitor 50.

この積層セラミックコンデンサ50−4によれば、積層セラミックコンデンサ50−4の熱を直接的に、且つ、高効率で放熱導体部56−2に伝えることにより、前記積層セラミックコンデンサ50と同様の放熱効果を得ることができる。この場合の各放熱導体部は、積層チップ51の上面とy−y方向の1側面とx−x方向の1側面に連続して、または、積層チップ51の上面とy−y方向の1側面とx−x方向の2側面に連続して設けられていてもよい。   According to the multilayer ceramic capacitor 50-4, the heat dissipation effect similar to that of the multilayer ceramic capacitor 50 can be obtained by directly and efficiently transmitting the heat of the multilayer ceramic capacitor 50-4 to the heat radiating conductor 56-2. Can be obtained. In this case, each radiating conductor portion is continuous with the upper surface of the multilayer chip 51, one side surface in the yy direction, and one side surface in the xx direction, or the upper surface of the multilayer chip 51 and one side surface in the yy direction. And may be provided continuously on two side surfaces in the xx direction.

図56は第5構造変形例を示すもので、この積層セラミックコンデンサ50−5が前記積層セラミックコンデンサ50と異なるところは、2つの放熱導体部56−2を積層チップ51の上面とy−y方向の1側面に連続し、且つ、第1外部電極54と接続するようにそれぞれ設けると共に、一方の第1内部電極52−3としてその上縁が積層チップ51の上面から離れた内側位置にあり、且つ、その側縁が積層チップ51のy−y方向の1側面から離れた内側位置にあるものを採用し、さらに、他方の第1内部電極52−4としてその上縁が積層チップ51の上面から離れた内側位置にあり、且つ、その側縁が積層チップ51のy−y方向の1側面から離れた内側位置にあるものを採用した点と、2つの第1外部電極54の間に2つの第2外部電極55を間隔をおいて設けた点にある。製法及び機能は前記積層セラミックコンデンサ50と同様である。   FIG. 56 shows a fifth structural modification example. This multilayer ceramic capacitor 50-5 is different from the multilayer ceramic capacitor 50 in that two heat radiating conductor portions 56-2 are arranged on the top surface of the multilayer chip 51 in the yy direction. Are provided so as to be connected to the first external electrode 54 and connected to the first external electrode 54, and the upper edge of the first internal electrode 52-3 is located at an inner position away from the upper surface of the multilayer chip 51, In addition, the one whose side edge is at the inner position away from one side surface in the y-y direction of the multilayer chip 51 is adopted, and the upper edge is the upper surface of the multilayer chip 51 as the other first internal electrode 52-4. 2 between the two first external electrodes 54 and the point that the side edge is located at the inner position away from one side surface of the laminated chip 51 in the y-y direction. Second outside There electrodes 55 in that spaced apart. The manufacturing method and function are the same as those of the multilayer ceramic capacitor 50.

この積層セラミックコンデンサ50−5によれば、積層セラミックコンデンサ50−5の熱を直接的に、且つ、高効率で放熱導体部56−2に伝えることにより、前記積層セラミックコンデンサ50と同様の放熱効果を得ることができる。この場合の各放熱導体部は、積層チップ51の上面とy−y方向の1側面とx−x方向の1側面に連続して、または、積層チップ51の上面とy−y方向の1側面とx−x方向の2側面に連続して設けられていてもよい。   According to the multilayer ceramic capacitor 50-5, the heat radiation effect similar to that of the multilayer ceramic capacitor 50 is achieved by directly and efficiently transmitting the heat of the multilayer ceramic capacitor 50-5 to the heat radiation conductor 56-2. Can be obtained. In this case, each radiating conductor portion is continuous with the upper surface of the multilayer chip 51, one side surface in the yy direction, and one side surface in the xx direction, or the upper surface of the multilayer chip 51 and one side surface in the yy direction. And may be provided continuously on two side surfaces in the xx direction.

[第6実施形態]
図57〜図59は本発明の第6実施形態を示す。図57は積層セラミックコンデンサの上面側から見た斜視図、図58(A)及び図58(B)は図57に示した積層セラミックコンデンサをy−y方向と平行で位置が異なる2つのラインで切断した縦断面図、図59(A)〜図59(C)は図57に示した積層セラミックコンデンサの製法説明図である。
[Sixth Embodiment]
57 to 59 show a sixth embodiment of the present invention. 57 is a perspective view of the multilayer ceramic capacitor as viewed from the upper surface side, and FIGS. 58A and 58B are views of the multilayer ceramic capacitor shown in FIG. 57 in two lines parallel to the y-y direction and having different positions. FIG. 59 (A) to FIG. 59 (C) are sectional views for explaining a method of manufacturing the multilayer ceramic capacitor shown in FIG.

第5実施形態の積層セラミックコンデンサ60は、直方体形状を成す積層チップ61を備える。この積層チップ61は、同一層に存する2つの第1内部電極62A,62Bと、第1内部電極62A,62Bが存する層とは異なる層に存する2つの第2内部電極63A,63Bとが、セラミック層(符号無し)を介して交互に、且つ、対向して配された構成を有する。第1内部電極62A,62Bが存する層の数と第2内部電極63A,63Bが存する層の数は必要とする静電容量に応じて任意に設定される。   A multilayer ceramic capacitor 60 according to the fifth embodiment includes a multilayer chip 61 having a rectangular parallelepiped shape. The multilayer chip 61 includes two first internal electrodes 62A and 62B in the same layer, and two second internal electrodes 63A and 63B in a different layer from the layer in which the first internal electrodes 62A and 62B exist. It has a configuration in which layers are arranged alternately and opposed to each other through layers (no reference). The number of layers in which the first internal electrodes 62A and 62B exist and the number of layers in which the second internal electrodes 63A and 63B exist are arbitrarily set according to the required capacitance.

図58(A)に示すように、2つの第1内部電極62A,62Bはそれぞれ縦長長方形を成し、両者間には所定の間隙が設けられている。一方の第1内部電極62Aはその下端一側に所定幅の引出部62Aaを有し、該引出部62Aaの下縁は積層チップ61の下面に露出している。また、一方の第1内部電極62Aの上縁は積層チップ61の上面から離れた内側位置にあり、側縁は積層チップ61のy−y方向の1側面から離れた内側位置にある。他方の第1内部電極62Bはその下端一側に所定幅の引出部62Baを有し、該引出部62Baの下縁は積層チップ61の下面に露出している。また、他方の第1内部電極62Bの上縁は積層チップ61の上面から離れた内側位置にあり、側縁は積層チップ61のy−y方向の1側面から離れた内側位置にある。   As shown in FIG. 58 (A), the two first internal electrodes 62A and 62B each have a vertically long rectangle, and a predetermined gap is provided between them. One first internal electrode 62 </ b> A has a lead portion 62 </ b> Aa having a predetermined width on one lower end side, and the lower edge of the lead portion 62 </ b> Aa is exposed on the lower surface of the multilayer chip 61. The upper edge of one first internal electrode 62A is at an inner position away from the upper surface of the multilayer chip 61, and the side edge is at an inner position away from one side surface of the multilayer chip 61 in the yy direction. The other first internal electrode 62 </ b> B has a lead portion 62 </ b> Ba having a predetermined width on one lower end side, and the lower edge of the lead portion 62 </ b> Ba is exposed on the lower surface of the multilayer chip 61. The upper edge of the other first internal electrode 62B is at an inner position away from the upper surface of the multilayer chip 61, and the side edge is at an inner position away from one side surface of the multilayer chip 61 in the yy direction.

図59(B)に示すように、2つの第2内部電極63A,63Bはそれぞれ縦長長方形を成し、両者間には所定の間隙が設けられている。一方の第2内部電極63Aはその下端一側に所定幅の引出部63Aaを有し、該引出部63Aaの下縁は積層チップ61の下面に露出している。また、一方の第2内部電極63Aの上縁は積層チップ61の上面に露出しており、側縁は積層チップ61のy−y方向の1側面から離れた内側位置にある。他方の第2内部電極63Bはその下端一側に所定幅の引出部63Baを有し、該引出部63Baの下縁は積層チップ61の下面に露出している。また、他方の第2内部電極63Bの上縁は積層チップ61の上面に露出しており、側縁は積層チップ61のy−y方向の1側面から離れた内側位置にある。   As shown in FIG. 59 (B), the two second internal electrodes 63A and 63B each have a vertically long rectangle, and a predetermined gap is provided between them. One second internal electrode 63 </ b> A has a lead portion 63 </ b> Aa having a predetermined width on one lower end side, and the lower edge of the lead portion 63 </ b> Aa is exposed on the lower surface of the multilayer chip 61. The upper edge of one second internal electrode 63A is exposed on the upper surface of the multilayer chip 61, and the side edge is at an inner position away from one side surface of the multilayer chip 61 in the yy direction. The other second internal electrode 63 </ b> B has a lead portion 63 </ b> Ba having a predetermined width on one lower end side, and the lower edge of the lead portion 63 </ b> Ba is exposed on the lower surface of the multilayer chip 61. Further, the upper edge of the other second internal electrode 63B is exposed on the upper surface of the multilayer chip 61, and the side edge is at an inner position away from one side surface of the multilayer chip 61 in the yy direction.

積層チップ61の下面両側には2つの第1外部電極64がx−x方向に帯状に設けられ、第1外部電極64の間に2つの第2外部電極65が第1外部電極64と間隔をおいてx−x方向に帯状に設けられている。図58(A)から分かるように一方の第1内部電極62Aの引出部62Aaの下縁は一方の第1外部電極64に接続し、他方の第1内部電極62Bの引出部62Baの下縁は他方の第1外部電極64に接続している。図58(B)から分かるように一方の第2内部電極63Aの引出部63Aaの下縁は一方の第2外部電極65に接続し、他方の第2内部電極63Bの引出部63Baの下縁は他方の第2外部電極65に接続している。   Two first external electrodes 64 are provided in strips in the xx direction on both sides of the lower surface of the multilayer chip 61, and the two second external electrodes 65 are spaced from the first external electrode 64 between the first external electrodes 64. In the xx direction. 58A, the lower edge of the lead portion 62Aa of one first internal electrode 62A is connected to one first external electrode 64, and the lower edge of the lead portion 62Ba of the other first internal electrode 62B is The other first external electrode 64 is connected. 58B, the lower edge of the lead portion 63Aa of one second internal electrode 63A is connected to one second external electrode 65, and the lower edge of the lead portion 63Ba of the other second internal electrode 63B is The other second external electrode 65 is connected.

また、積層チップ61の上面には2つの放熱導体部66が離隔して設けられ、積層チップ61のy−y方向の2側面には2つの放熱導体部67が第1外部電極64と接続するようにそれぞれ設けられている。図58(B)から分かるように一方の第2内部電極63Aの上縁は上面側の一方の放熱導体部66に接続し、他方の第2内部電極63Bの上縁は上面側の他方の放熱導体部66に接続している。この場合の上面側の各放熱導体部66は、積層チップ61の上面とx−x方向の1側面に連続して、または、積層チップ61の上面とx−x方向の2側面に連続して設けられていてもよく、一方、側面側の各放熱導体部67は、積層チップ61のy−y方向の1側面とx−x方向の1側面に連続して、または、積層チップ61のy−y方向の1側面とx−x方向の2側面に連続して設けられていてもよい。   In addition, two heat radiating conductor portions 66 are provided on the upper surface of the multilayer chip 61 so as to be separated from each other, and two heat radiating conductor portions 67 are connected to the first external electrode 64 on two side surfaces in the yy direction of the multilayer chip 61. Are provided respectively. As can be seen from FIG. 58 (B), the upper edge of one second internal electrode 63A is connected to one heat radiation conductor 66 on the upper surface side, and the upper edge of the other second internal electrode 63B is the other heat radiation on the upper surface side. The conductor part 66 is connected. In this case, each radiating conductor 66 on the upper surface side is continuous with the upper surface of the multilayer chip 61 and one side surface in the xx direction, or continuously with the upper surface of the multilayer chip 61 and two side surfaces in the xx direction. On the other hand, each of the heat radiation conductors 67 on the side surface side may be continuous with one side surface in the yy direction and one side surface in the xx direction of the multilayer chip 61, or y of the multilayer chip 61. It may be provided continuously on one side surface in the −y direction and two side surfaces in the xx direction.

前記積層セラミックコンデンサ60を製造するに際しては、まず、チタン酸バリウム等の誘電体粉末を含有した未焼成セラミックシートの一面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して第1内部電極62A,62B用の2つの未焼成内部電極C61a,C61Bを形成した第1シートS61(図59(A)参照)と、未焼成セラミックシートの一面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して第2内部電極63A,63B用の2つの未焼成内部電極C62A,C62Bを形成した第2シートS62(図59(B)参照)とを交互に所定枚数積み重ねて、未焼成内部電極を形成していない未焼成セラミックシートから成るダミーシートS63(図59(C)参照)をその両側に重ね合わせて全体を熱圧着し、これを焼成する。図59には1部品に対応した大きさの未焼成セラミックシートを示したが、実際上は多数個取りを可能とした大きさの未焼成セラミックシートを用いて積層圧着後にこれを部品寸法に切断して焼成することで積層チップ61を得る。   In manufacturing the multilayer ceramic capacitor 60, first, a conductor paste containing a metal powder such as silver or nickel is printed on one surface of an unfired ceramic sheet containing a dielectric powder such as barium titanate. A first sheet S61 (see FIG. 59A) on which two unfired internal electrodes C61a and C61B for the electrodes 62A and 62B are formed, and a conductor containing a metal powder such as silver or nickel on one surface of the unfired ceramic sheet A predetermined number of second sheets S62 (see FIG. 59B) on which paste is printed to form the two unfired internal electrodes C62A and C62B for the second internal electrodes 63A and 63B are alternately stacked, and the unfired interior A dummy sheet S63 (see FIG. 59 (C)) made of an unfired ceramic sheet on which no electrode is formed is superposed on both sides, and the whole is heated and pressed. And, I fired it. 59 shows an unfired ceramic sheet of a size corresponding to one part, but in actuality, an unfired ceramic sheet of a size that can be picked up in large numbers is used, and this is cut into part dimensions after laminating and pressing. Then, the laminated chip 61 is obtained by firing.

次に、焼成により得られた積層チップ61の上面及びy−y方向の2側面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して2つの上面側の未焼成放熱導体部(図示省略)と2つの側面側の未焼成放熱導体部(図示省略)を形成し、且つ、積層チップ61の下面に銀やニッケル等の金属粉末を含有した導体ペーストを印刷して2つの未焼成第1外部電極(図示省略)と2つの未焼成第2外部電極(図示省略)を形成し、これらに焼き付け処理を施す。勿論、未焼成放熱導体部,未焼成第1外部電極及び未焼成第2外部電極の焼き付け処理は積層チップの焼成処理と同時に行うこともできる。   Next, a conductive paste containing metal powder such as silver or nickel is printed on the upper surface and two side surfaces in the y-y direction of the laminated chip 61 obtained by firing, and two unfired heat radiation conductor portions (illustrated on the upper surface side) (Not shown) and two unfired heat-radiating conductor portions (not shown) on the side surfaces are formed, and a conductor paste containing a metal powder such as silver or nickel is printed on the lower surface of the laminated chip 61 to obtain two unfired conductive parts. One external electrode (not shown) and two unfired second external electrodes (not shown) are formed and subjected to a baking process. Of course, the baking process of the unsintered heat radiation conductor part, the unsintered first external electrode and the unsintered second external electrode can be performed simultaneously with the firing process of the laminated chip.

第6実施形態の積層セラミックコンデンサ60は、一方の第1外部電極64と一方の第2外部電極65との間に一方の第1内部電極62Aと一方の第2内部電極63Aとの対向面積及び積層数に準じた所定の静電容量を得ることができ、他方の第1外部電極64と他方の第2外部電極65との間に他方の第1内部電極62Bと他方の第2内部電極63Bとの対向面積及び積層数に準じた所定の静電容量を得ることができる。つまり、積層セラミックコンデンサ60を2つのコンデンサが組み合わされたコンデンサアレイとして使用することができる。勿論、2つのコンデンサの静電容量の和に等しい静電容量を2つの第1外部電極64と2つの第2外部電極65との間で得ることも可能である。   The multilayer ceramic capacitor 60 of the sixth embodiment includes an opposing area between one first internal electrode 62A and one second internal electrode 63A between one first external electrode 64 and one second external electrode 65, and A predetermined capacitance according to the number of layers can be obtained, and the other first internal electrode 62B and the other second internal electrode 63B are provided between the other first external electrode 64 and the other second external electrode 65. A predetermined capacitance according to the facing area and the number of stacked layers can be obtained. That is, the multilayer ceramic capacitor 60 can be used as a capacitor array in which two capacitors are combined. Of course, a capacitance equal to the sum of the capacitances of the two capacitors can be obtained between the two first external electrodes 64 and the two second external electrodes 65.

この積層セラミックコンデンサ60にあっては、2つの第1内部電極62A,62Bと2つの第2内部電極63A,63Bとの間に不要な導体層が存しないため、つまり、図1〜図3に示した従来の積層セラミックコンデンサのように隣接する内部電極1間それぞれに内部電極1とは別の放熱用内部電極5が存しないため、一方の第1外部電極64と一方の第2外部電極65との間と、他方の第1外部電極64と他方の第2外部電極65との間に、所期の静電容量を安定して確保することができる。   In the multilayer ceramic capacitor 60, an unnecessary conductor layer does not exist between the two first internal electrodes 62A and 62B and the two second internal electrodes 63A and 63B. That is, in FIGS. Unlike the conventional multilayer ceramic capacitor shown, there is no internal heat dissipating electrode 5 different from the internal electrode 1 between the adjacent internal electrodes 1, so one first external electrode 64 and one second external electrode 65. , And between the other first external electrode 64 and the other second external electrode 65, a desired electrostatic capacity can be stably secured.

また、この積層セラミックコンデンサ60にあっては、実装後の積層セラミックコンデンサ60への電圧印加時に各内部電極62A,62B,63A,63Bで熱が発生すると、また、実装基板からの熱が各外部電極64,65から各内部電極62A,62B,63A,63Bに伝わると、この熱は各第1内部電極62A,62Bから側面側の放熱導体部67に直接的に伝わると共に各第2内部電極63A,63Bから上面側の放熱導体部66に直接的に伝わって該放熱導体部66,67から外部に放出される。要するに、積層セラミックコンデンサ60を熱を直接的に、且つ、高効率で放熱導体部66,67に伝えることにより、コンデンサ自体の熱を効果的に外部に放出してその温度上昇を確実に抑制することができる。しかも、放熱導体部66,67に十分な面積が確保できるので前記の熱放出をより効果的に行うことができる。   Further, in this multilayer ceramic capacitor 60, when heat is generated in each of the internal electrodes 62A, 62B, 63A, 63B when a voltage is applied to the multilayer ceramic capacitor 60 after mounting, the heat from the mounting board is also transferred to each external electrode. When the heat is transmitted from the electrodes 64, 65 to the internal electrodes 62A, 62B, 63A, 63B, the heat is directly transmitted from the first internal electrodes 62A, 62B to the heat-radiating conductor 67 on the side surface and the second internal electrodes 63A. , 63B is directly transmitted to the heat radiating conductor portion 66 on the upper surface side, and is emitted to the outside from the heat radiating conductor portions 66, 67. In short, by directly transferring heat to the multilayer ceramic capacitor 60 to the heat radiating conductors 66 and 67 with high efficiency, the heat of the capacitor itself is effectively released to the outside and the temperature rise is reliably suppressed. be able to. In addition, since a sufficient area can be secured for the heat radiating conductor portions 66 and 67, the heat release can be performed more effectively.

尚、図57〜図59には同一層に2つの第1内部電極62A,62Bを設け、これとは異なる層に2つの第2内部電極63A,63Bを設けたものを示したが、同一層に3以上の第1内部電極を設け、これとは異なる層に3以上の第2内部電極を各第1内部電極と対向するように設ければ、3以上のコンデンサが組み合わされたコンデンサアレイとして構成することもできる。第1内部電極及び第2内部電極を3以上設ける場合には第1内部電極及び第2内部電極の数に応じて外部電極の数は増加することになる。   In FIGS. 57 to 59, two first internal electrodes 62A and 62B are provided in the same layer, and two second internal electrodes 63A and 63B are provided in a different layer. If three or more first internal electrodes are provided on the same layer, and three or more second internal electrodes are provided on a different layer so as to face each first internal electrode, a capacitor array in which three or more capacitors are combined. It can also be configured. When three or more first internal electrodes and second internal electrodes are provided, the number of external electrodes increases according to the number of first internal electrodes and second internal electrodes.

また、図57〜図59には一方の第1内部電極62Aと一方の第2内部電極63Aとを対向させ、且つ、他方の第1内部電極62Bと他方の第2内部電極63Bとを対向させたものを示したが、例えば図60に示した積層セラミックコンデンサ60’のように一方の第1内部電極62A’の幅を小さくし他方の第1内部電極62B’の幅を大きくして他方の第1内部電極62B’が2つの第2内部電極63A,63Bと向き合うように構成すれば、一方の第1外部電極64と一方の第2外部電極65との間で得られる静電容量と、他方の第1外部電極64と他方の第2外部電極65との間で得られる静電容量を変化させることもできる。   57 to 59, one first internal electrode 62A and one second internal electrode 63A are opposed to each other, and the other first internal electrode 62B and the other second internal electrode 63B are opposed to each other. For example, like the multilayer ceramic capacitor 60 ′ shown in FIG. 60, the width of one first internal electrode 62A ′ is reduced and the width of the other first internal electrode 62B ′ is increased. If the first internal electrode 62B ′ is configured to face the two second internal electrodes 63A and 63B, a capacitance obtained between one first external electrode 64 and one second external electrode 65; The capacitance obtained between the other first external electrode 64 and the other second external electrode 65 can also be changed.

以下に、前記第6実施形態の構造変形例を図61〜図62を引用して説明する。   Hereinafter, structural modifications of the sixth embodiment will be described with reference to FIGS.

図61〜図62は第1構造変形例を示すもので、この積層セラミックコンデンサ60−1が前記積層セラミックコンデンサ60と異なるところは、側面側の2つの放熱導体部67−1を積層チップ51のy−y方向の2側面に第1外部電極64と非接続でそれぞれ設けると共に、各第1内部電極62A−1,62B−1としてその上縁が積層チップ51の上面に露出したものを採用して、各第1内部電極62A−1,62B−1の上縁を上面側の放熱導体部66にそれぞれ接続し、また、各第2内部電極63A−1,63B−1としてその上縁が積層チップ61の上面から離れた内側位置にあり、且つ、その側縁が積層チップ61のy−y方向の1側面にそれぞれ露出したものを採用して、各第2内部電極63A−1,63B−1の側縁を側面側の放熱導体部67−1にそれぞれ接続した点にある。   61 to 62 show a first structural modification example. This multilayer ceramic capacitor 60-1 is different from the multilayer ceramic capacitor 60 in that the two radiating conductor portions 67-1 on the side surface side of the multilayer chip 51 are arranged. The first external electrodes 64 are provided on the two side surfaces in the y-y direction so as not to be connected to each other, and the first inner electrodes 62A-1 and 62B-1 have their upper edges exposed on the upper surface of the multilayer chip 51. The upper edges of the first internal electrodes 62A-1 and 62B-1 are connected to the heat radiating conductor 66 on the upper surface side, and the upper edges are laminated as the second internal electrodes 63A-1 and 63B-1. The second internal electrodes 63A-1 and 63B- are employed by adopting the inner side of the chip 61 that is away from the upper surface and the side edges of which are exposed on one side surface of the laminated chip 61 in the yy direction. 1 side edge Lies in that connected to the side of the heat conductor portion 67-1.

この積層セラミックコンデンサ60−1によれば、積層セラミックコンデンサ60−1の熱を直接的に、且つ、高効率で放熱導体部66,67−1に伝えることにより、前記積層セラミックコンデンサ60と同様の放熱効果を得ることができる。この場合の上面側の各放熱導体部66は、積層チップ61の上面とx−x方向の1側面に連続して、または、積層チップ61の上面とx−x方向の2側面に連続して設けられていてもよく、一方、側面側の各放熱導体部67−1は、積層チップ61のy−y方向の1側面とx−x方向の1側面に連続して、または、積層チップ61のy−y方向の1側面とx−x方向の2側面に連続して設けられていてもよい。   According to the multilayer ceramic capacitor 60-1, the heat of the multilayer ceramic capacitor 60-1 is directly and highly efficiently transmitted to the heat radiating conductors 66 and 67-1, thereby being the same as the multilayer ceramic capacitor 60. A heat dissipation effect can be obtained. In this case, each radiating conductor 66 on the upper surface side is continuous with the upper surface of the multilayer chip 61 and one side surface in the xx direction, or continuously with the upper surface of the multilayer chip 61 and two side surfaces in the xx direction. On the other hand, each of the heat radiation conductors 67-1 on the side surface side may be continuous with one side surface in the yy direction and one side surface in the xx direction of the multilayer chip 61, or the multilayer chip 61. May be provided continuously on one side surface in the y-y direction and two side surfaces in the xx direction.

従来の積層セラミックコンデンサの斜視図である。It is a perspective view of the conventional multilayer ceramic capacitor. 図1のa1−a1線断面図である。It is the a1-a1 sectional view taken on the line of FIG. 図1のa2−a2線断面図である。FIG. 2 is a cross-sectional view taken along line a2-a2 of FIG. 本発明の第1実施形態を示す積層セラミックコンデンサの上面側から見た斜視図である。It is the perspective view seen from the upper surface side of the multilayer ceramic capacitor which shows 1st Embodiment of this invention. 図4の積層セラミックコンデンサの下面側から見た斜視図である。It is the perspective view seen from the lower surface side of the multilayer ceramic capacitor of FIG. 図4に示した積層セラミックコンデンサをy−y方向と平行で位置が異なる2つのラインで切断した縦断面図である。FIG. 5 is a longitudinal sectional view of the multilayer ceramic capacitor shown in FIG. 4 cut along two lines that are parallel to the y-y direction and have different positions. 図4に示した積層コンデンサをx−x方向と平行で位置が異なる2つのラインで切断した縦断面図である。FIG. 5 is a longitudinal sectional view of the multilayer capacitor shown in FIG. 4 cut along two lines parallel to the xx direction and having different positions. 図4に示した積層セラミックコンデンサの製法説明図である。FIG. 5 is an explanatory diagram of a method for manufacturing the multilayer ceramic capacitor shown in FIG. 4. 図4に示した積層セラミックコンデンサの製法説明図である。FIG. 5 is an explanatory diagram of a method for manufacturing the multilayer ceramic capacitor shown in FIG. 4. 図4に示した積層セラミックコンデンサの外部電極数を増加した例を示す縦断面図である。FIG. 5 is a longitudinal sectional view showing an example in which the number of external electrodes of the multilayer ceramic capacitor shown in FIG. 4 is increased. 第1実施形態の第1構造変形例を示す積層セラミックコンデンサの上面側から見た斜視図である。It is the perspective view seen from the upper surface side of the multilayer ceramic capacitor which shows the 1st structural modification of 1st Embodiment. 図11に示した積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。FIG. 12 is a longitudinal sectional view of the multilayer ceramic capacitor shown in FIG. 11 cut along a line parallel to the yy direction. 第1実施形態の第2構造変形例を示す積層セラミックコンデンサの上面側から見た斜視図である。It is the perspective view seen from the upper surface side of the multilayer ceramic capacitor which shows the 2nd structural modification of 1st Embodiment. 図13に示した積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。It is the longitudinal cross-sectional view which cut | disconnected the multilayer ceramic capacitor shown in FIG. 13 by the line parallel to yy direction. 第1実施形態の第3構造変形例を示す積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。It is the longitudinal cross-sectional view which cut | disconnected the multilayer ceramic capacitor which shows the 3rd structural modification of 1st Embodiment by the line parallel to a yy direction. 第1実施形態の第4構造変形例を示す積層セラミックコンデンサの上面側から見た斜視図である。It is the perspective view seen from the upper surface side of the multilayer ceramic capacitor which shows the 4th structural modification of 1st Embodiment. 図16に示した積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。FIG. 17 is a longitudinal sectional view of the multilayer ceramic capacitor shown in FIG. 16 cut along a line parallel to the yy direction. 本発明の第2実施形態を示す積層セラミックコンデンサの上面側から見た斜視図である。It is the perspective view seen from the upper surface side of the multilayer ceramic capacitor which shows 2nd Embodiment of this invention. 図18に示した積層セラミックコンデンサをy−y方向と平行で位置が異なる2つのラインで切断した縦断面図である。It is the longitudinal cross-sectional view which cut | disconnected the multilayer ceramic capacitor shown in FIG. 18 by two lines which differ in a position in parallel with a yy direction. 図18に示した積層セラミックコンデンサの製法説明図である。It is manufacturing method explanatory drawing of the multilayer ceramic capacitor shown in FIG. 図18に示した積層セラミックコンデンサの外部電極数を増加した例を示す縦断面図である。FIG. 19 is a longitudinal sectional view showing an example in which the number of external electrodes of the multilayer ceramic capacitor shown in FIG. 18 is increased. 第2実施形態の第1構造変形例を示す積層セラミックコンデンサの上面側から見た斜視図である。It is the perspective view seen from the upper surface side of the multilayer ceramic capacitor which shows the 1st structural modification of 2nd Embodiment. 図22に示した積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。FIG. 23 is a longitudinal sectional view of the multilayer ceramic capacitor shown in FIG. 22 cut along a line parallel to the yy direction. 第2実施形態の第2構造変形例を示す積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。It is the longitudinal cross-sectional view which cut | disconnected the multilayer ceramic capacitor which shows the 2nd structural modification of 2nd Embodiment by the line parallel to a yy direction. 第2実施形態の第3構造変形例を示す積層セラミックコンデンサの上面側から見た斜視図である。It is the perspective view seen from the upper surface side of the multilayer ceramic capacitor which shows the 3rd structural modification of 2nd Embodiment. 図25に示した積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。FIG. 26 is a longitudinal sectional view of the multilayer ceramic capacitor shown in FIG. 25 cut along a line parallel to the yy direction. 第2実施形態の第4構造変形例を示す積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。It is the longitudinal cross-sectional view which cut | disconnected the multilayer ceramic capacitor which shows the 4th structural modification of 2nd Embodiment by the line parallel to a yy direction. 第2実施形態の第5構造変形例を示す積層セラミックコンデンサの上面側から見た斜視図である。It is the perspective view seen from the upper surface side of the multilayer ceramic capacitor which shows the 5th structural modification of 2nd Embodiment. 図28に示した積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。FIG. 29 is a longitudinal sectional view of the multilayer ceramic capacitor shown in FIG. 28 cut along a line parallel to the yy direction. 本発明の第3実施形態を示す積層セラミックコンデンサの上面側から見た斜視図である。It is the perspective view seen from the upper surface side of the multilayer ceramic capacitor which shows 3rd Embodiment of this invention. 図30に示した積層セラミックコンデンサをy−y方向と平行で位置が異なる2つのラインで切断した縦断面図である。FIG. 31 is a longitudinal sectional view of the multilayer ceramic capacitor shown in FIG. 30 cut along two lines that are parallel to the y-y direction and have different positions. 図30に示した積層セラミックコンデンサの製法説明図である。FIG. 31 is an explanatory diagram of a manufacturing method for the multilayer ceramic capacitor shown in FIG. 30. 図30に示した積層セラミックコンデンサの外部電極数を増加した例を示す縦断面図である。FIG. 31 is a longitudinal sectional view showing an example in which the number of external electrodes of the multilayer ceramic capacitor shown in FIG. 30 is increased. 第3実施形態の第1構造変形例を示す積層セラミックコンデンサの上面側から見た斜視図である。It is the perspective view seen from the upper surface side of the multilayer ceramic capacitor which shows the 1st structural modification of 3rd Embodiment. 図34に示した積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。FIG. 35 is a longitudinal sectional view of the multilayer ceramic capacitor shown in FIG. 34 cut along a line parallel to the yy direction. 第3実施形態の第2構造変形例を示す積層セラミックコンデンサの上面側から見た斜視図である。It is the perspective view seen from the upper surface side of the multilayer ceramic capacitor which shows the 2nd structural modification of 3rd Embodiment. 図36に示した積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。FIG. 37 is a longitudinal sectional view of the multilayer ceramic capacitor shown in FIG. 36 cut along a line parallel to the yy direction. 本発明の第4実施形態を示す積層セラミックコンデンサの上面側から見た斜視図である。It is the perspective view seen from the upper surface side of the multilayer ceramic capacitor which shows 4th Embodiment of this invention. 図38に示した積層セラミックコンデンサをy−y方向と平行で位置が異なる2つのラインで切断した縦断面図である。FIG. 39 is a longitudinal sectional view of the multilayer ceramic capacitor shown in FIG. 38 cut along two lines that are parallel to the y-y direction and have different positions. 図38に示した積層セラミックコンデンサの製法説明図である。FIG. 39 is an explanatory diagram of a production method for the multilayer ceramic capacitor shown in FIG. 38. 図38に示した積層セラミックコンデンサの内部電極形状を変えた例を示す縦断面図である。It is a longitudinal cross-sectional view which shows the example which changed the internal electrode shape of the multilayer ceramic capacitor shown in FIG. 第4実施形態の第1構造変形例を示す積層セラミックコンデンサの上面側から見た斜視図である。It is the perspective view seen from the upper surface side of the multilayer ceramic capacitor which shows the 1st structure modification of 4th Embodiment. 図42に示した積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。FIG. 43 is a longitudinal sectional view of the multilayer ceramic capacitor shown in FIG. 42 cut along a line parallel to the yy direction. 第4実施形態の第2構造変形例を示す積層セラミックコンデンサの上面側から見た斜視図である。It is the perspective view seen from the upper surface side of the multilayer ceramic capacitor which shows the 2nd structural modification of 4th Embodiment. 図44に示した積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。FIG. 45 is a longitudinal sectional view of the multilayer ceramic capacitor shown in FIG. 44 cut along a line parallel to the yy direction. 第4実施形態の第3構造変形例を示す積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。It is the longitudinal cross-sectional view which cut | disconnected the multilayer ceramic capacitor which shows the 3rd structural modification of 4th Embodiment by the line parallel to a yy direction. 本発明の第5実施形態を示す積層セラミックコンデンサの上面側から見た斜視図である。It is the perspective view seen from the upper surface side of the multilayer ceramic capacitor which shows 5th Embodiment of this invention. 図47に示した積層セラミックコンデンサをy−y方向と平行で位置が異なる2つのラインで切断した縦断面図である。FIG. 48 is a longitudinal sectional view of the multilayer ceramic capacitor shown in FIG. 47 cut along two lines that are parallel to the y-y direction and have different positions. 図47に示した積層セラミックコンデンサの製法説明図である。FIG. 48 is an explanatory diagram of a manufacturing method for the multilayer ceramic capacitor shown in FIG. 47. 第5実施形態の第1構造変形例を示す積層セラミックコンデンサの上面側から見た斜視図である。It is the perspective view seen from the upper surface side of the multilayer ceramic capacitor which shows the 1st structural modification of 5th Embodiment. 図50に示した積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。It is the longitudinal cross-sectional view which cut | disconnected the multilayer ceramic capacitor shown in FIG. 50 by the line parallel to yy direction. 第5実施形態の第2構造変形例を示す積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。It is the longitudinal cross-sectional view which cut | disconnected the multilayer ceramic capacitor which shows the 2nd structural modification of 5th Embodiment by the line parallel to a yy direction. 第5実施形態の第3構造変形例を示す積層セラミックコンデンサの上面側から見た斜視図である。It is the perspective view seen from the upper surface side of the multilayer ceramic capacitor which shows the 3rd structural modification of 5th Embodiment. 図53に示した積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。FIG. 54 is a longitudinal sectional view of the multilayer ceramic capacitor shown in FIG. 53 cut along a line parallel to the yy direction. 第5実施形態の第4構造変形例を示す積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。It is the longitudinal cross-sectional view which cut | disconnected the multilayer ceramic capacitor which shows the 4th structural modification of 5th Embodiment by the line parallel to a yy direction. 第5実施形態の第5構造変形例を示す積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。It is the longitudinal cross-sectional view which cut | disconnected the multilayer ceramic capacitor which shows the 5th structural modification of 5th Embodiment by the line parallel to a yy direction. 本発明の第6実施形態を示す積層セラミックコンデンサの上面側から見た斜視図である。It is the perspective view seen from the upper surface side of the multilayer ceramic capacitor which shows 6th Embodiment of this invention. 図57に示した積層セラミックコンデンサをy−y方向と平行で位置が異なる2つのラインで切断した縦断面図である。FIG. 58 is a longitudinal sectional view of the multilayer ceramic capacitor shown in FIG. 57 cut along two lines that are parallel to the y-y direction and have different positions. 図57に示した積層セラミックコンデンサの製法説明図である。FIG. 58 is an explanatory diagram of a manufacturing method of the multilayer ceramic capacitor shown in FIG. 57. 図57に示した積層セラミックコンデンサの内部電極形状を変えた例を示す縦断面図である。FIG. 58 is a longitudinal sectional view showing an example in which the internal electrode shape of the multilayer ceramic capacitor shown in FIG. 57 is changed. 第6実施形態の第1構造変形例を示す積層セラミックコンデンサの上面側から見た斜視図である。It is the perspective view seen from the upper surface side of the multilayer ceramic capacitor which shows the 1st structure modification of 6th Embodiment. 図61に示した積層セラミックコンデンサをy−y方向と平行なラインで切断した縦断面図である。FIG. 62 is a longitudinal sectional view of the multilayer ceramic capacitor shown in FIG. 61 cut along a line parallel to the yy direction.

符号の説明Explanation of symbols

10,10’,10−1,10−2,10−3,10−4…積層セラミックコンデンサ、11…積層チップ、12,12’…第1内部電極、13,13’,13−1,13−2…第2内部電極、14…第1外部電極、15…第2外部電極、16,16−1,16−2,16−3,16−4…放熱導体部、20,20’,20−1,20−2,20−3,20−4,20−5…積層セラミックコンデンサ、21…積層チップ、22A,22A’,22A−1,22A−2,22A−3,22A−4,22B,22B’,22B−1,22B−2…第1外部内部電極、23,23’…第2内部電極、24…第1外部電極、25…第2外部電極、26,26−1,26−2,26−3,26−4…放熱導体部、30,30’,30−1,30−2…積層セラミックコンデンサ、31…積層チップ、32A,32A’,32A−1,32B,32B’,22B−1…第1外部内部電極、33,33’,33−1,33−2…第2内部電極、34…第1外部電極、35…第2外部電極、36,36−1,37,37−1…放熱導体部、40,40’,40−1,40−2,40−3…積層セラミックコンデンサ、41…積層チップ、42A,42A’,42A−1,42A−2,42B,42B’…第1外部内部電極、43…第2内部電極、44…第1外部電極、45…第2外部電極、46,46’,46−1,46−2…放熱導体部、50,50−1,50−2,50−3,50−4,50−5…積層セラミックコンデンサ、51…積層チップ、52,52−1,52−2,52−3,52−4…第1外部内部電極、53,53−1…第2内部電極、54…第1外部電極、55…第2外部電極、56,56−1,56−2…放熱導体部、60,60’,60−1…積層セラミックコンデンサ、61…積層チップ、62A,62A’,62A−1,62B,62B’,62B−1…第1外部内部電極、63A,63A−1,63B,63B−1…第2内部電極、64…第1外部電極、65…第2外部電極、66,67,67−1…放熱導体部。   DESCRIPTION OF SYMBOLS 10,10 ', 10-1,10-2,10-3,10-4 ... Multilayer ceramic capacitor, 11 ... Multilayer chip, 12, 12' ... 1st internal electrode, 13, 13 ', 13-1, 13 -2 ... 2nd internal electrode, 14 ... 1st external electrode, 15 ... 2nd external electrode, 16, 16-1, 16-2, 16-3, 16-4 ... Radiation conductor part, 20, 20 ', 20 -1, 20-2, 20-3, 20-4, 20-5 ... multilayer ceramic capacitor, 21 ... multilayer chip, 22A, 22A ', 22A-1, 22A-2, 22A-3, 22A-4, 22B , 22B ', 22B-1, 22B-2 ... first external internal electrode, 23, 23' ... second internal electrode, 24 ... first external electrode, 25 ... second external electrode, 26, 26-1, 26- 2, 26-3, 26-4 ... Radiating conductor part, 30, 30 ', 30-1, 30-2 ... Layer ceramic capacitor, 31 ... multilayer chip, 32A, 32A ', 32A-1, 32B, 32B', 22B-1 ... first external internal electrode, 33, 33 ', 33-1, 33-2 ... second internal electrode 34 ... 1st external electrode, 35 ... 2nd external electrode, 36, 36-1, 37, 37-1 ... Radiation conductor part, 40, 40 ', 40-1, 40-2, 40-3 ... Multilayer ceramic Capacitor 41 ... Multilayer chip, 42A, 42A ', 42A-1, 42A-2, 42B, 42B' ... First external internal electrode, 43 ... Second internal electrode, 44 ... First external electrode, 45 ... Second external Electrode, 46, 46 ', 46-1, 46-2 ... Radiation conductor, 50, 50-1, 50-2, 50-3, 50-4, 50-5 ... Multilayer ceramic capacitor, 51 ... Multilayer chip, 52, 52-1, 52-2, 52-3, 52 4 ... 1st external internal electrode, 53, 53-1, 2nd internal electrode, 54 ... 1st external electrode, 55 ... 2nd external electrode, 56, 56-1, 56-2 ... Radiation conductor part, 60, 60 ', 60-1 ... Multilayer ceramic capacitor, 61 ... Multilayer chip, 62A, 62A', 62A-1, 62B, 62B ', 62B-1 ... First external internal electrode, 63A, 63A-1, 63B, 63B-1 ... 2nd internal electrode, 64 ... 1st external electrode, 65 ... 2nd external electrode, 66, 67, 67-1 ... Radiation conductor part.

Claims (15)

同一層に存する2以上の第1内部電極と、第1内部電極が存する層とは異なる層に存する共通内部電極とが、セラミック層を介して交互に、且つ、対向して配された直方体形状の積層チップと、
積層チップの1つの面に設けられ、各第1内部電極と導通する2以上の第1外部電極と、
積層チップの前記1つの面に第1外部電極と非接触で設けられ、共通内部電極と導通する少なくとも1つの第2外部電極と、
積層チップの前記1つの面とは異なる少なくとも1つの面に設けられ、2以上の第1内部電極の少なくとも1つ、または、共通内部電極と導通する少なくとも1つの放熱導体部とを備える、
ことを特徴とする積層セラミックコンデンサ。
A rectangular parallelepiped shape in which two or more first internal electrodes in the same layer and a common internal electrode in a layer different from the layer in which the first internal electrode exists are arranged alternately and facing each other through the ceramic layer A laminated chip of
Two or more first external electrodes provided on one surface of the multilayer chip and electrically connected to each first internal electrode;
At least one second external electrode provided in contact with the first external electrode on the one surface of the multilayer chip and electrically connected to the common internal electrode;
Provided on at least one surface different from the one surface of the multilayer chip, comprising at least one of two or more first internal electrodes, or at least one heat radiating conductor portion conducting to the common internal electrode,
A multilayer ceramic capacitor characterized by that.
放熱導体部は、積層チップの前記1つの面と対向する面に設けられている、
ことを特徴とする請求項1に記載の積層セラミックコンデンサ。
The heat dissipating conductor is provided on the surface facing the one surface of the multilayer chip.
The multilayer ceramic capacitor according to claim 1.
放熱導体部は、積層チップの前記1つの面と隣り合う少なくとも1つの面に設けられている、
ことを特徴とする請求項1に記載の積層セラミックコンデンサ。
The heat dissipation conductor portion is provided on at least one surface adjacent to the one surface of the multilayer chip.
The multilayer ceramic capacitor according to claim 1.
放熱導体部は、積層チップの前記1つの面と対向する面とこの面と隣り合う少なくとも1つの面に設けられている、
ことを特徴とする請求項1に記載の積層セラミックコンデンサ。
The heat dissipating conductor portion is provided on a surface facing the one surface of the multilayer chip and at least one surface adjacent to the surface.
The multilayer ceramic capacitor according to claim 1.
第1内部電極の少なくとも1つが放熱導体部と導通している、
ことを特徴とする請求項1〜4の何れか1項に記載の積層セラミックコンデンサ。
At least one of the first internal electrodes is in conduction with the heat dissipating conductor,
The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the multilayer ceramic capacitor is any one of the above.
共通内部電極が放熱導体部と導通している、
ことを特徴とする請求項1〜4の何れか1項に記載の積層セラミックコンデンサ。
The common internal electrode is connected to the heat dissipation conductor,
The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the multilayer ceramic capacitor is any one of the above.
第1内部電極の少なくとも1つと共通内部電極が別々の放熱導体部に導通している、
ことを特徴とする請求項1〜4の何れか1項に記載の積層セラミックコンデンサ。
At least one of the first internal electrodes and the common internal electrode are electrically connected to different heat conductor portions,
The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the multilayer ceramic capacitor is any one of the above.
同一層に存する2以上の第1内部電極と、第1内部電極が存する層とは異なる層に存する2以上の第2内部電極とが、セラミック層を介して交互に、且つ、対向して配された直方体形状の積層チップと、
積層チップの1つの面に設けられ、各第1内部電極と導通する2以上の第1外部電極と、
積層チップの1つの面に第1外部電極と非接触で設けられ、各第2内部電極と導通する2以上の第2外部電極と、
積層チップの前記1つの面とは異なる少なくとも1つの面に設けられ、2以上の第1内部電極の少なくとも1つ、または、2以上の第2内部電極の少なくとも1つと導通する少なくとも1つの放熱導体部とを備える、
ことを特徴とする積層セラミックコンデンサ。
Two or more first internal electrodes in the same layer and two or more second internal electrodes in a layer different from the layer in which the first internal electrode exists are alternately arranged opposite to each other via the ceramic layer. A rectangular parallelepiped laminated chip,
Two or more first external electrodes provided on one surface of the multilayer chip and electrically connected to each first internal electrode;
Two or more second external electrodes provided on one surface of the multilayer chip in a non-contact manner with the first external electrodes and electrically connected to the respective second internal electrodes;
At least one heat radiating conductor provided on at least one surface different from the one surface of the multilayer chip and conducting with at least one of the two or more first internal electrodes or at least one of the two or more second internal electrodes. Comprising a part,
A multilayer ceramic capacitor characterized by that.
放熱導体部は、積層チップの前記1つの面と対向する面に設けられている、
ことを特徴とする請求項8に記載の積層セラミックコンデンサ。
The heat dissipating conductor is provided on the surface facing the one surface of the multilayer chip.
The multilayer ceramic capacitor according to claim 8.
放熱導体部は、積層チップの前記1つの面と隣り合う少なくとも1つの面に設けられている、
ことを特徴とする請求項8に記載の積層セラミックコンデンサ。
The heat dissipation conductor portion is provided on at least one surface adjacent to the one surface of the multilayer chip.
The multilayer ceramic capacitor according to claim 8.
放熱導体部は、積層チップの前記1つの面と対向する面とこの面と隣り合う少なくとも1つの面に設けられている、
ことを特徴とする請求項8に記載の積層セラミックコンデンサ。
The heat dissipating conductor portion is provided on a surface facing the one surface of the multilayer chip and at least one surface adjacent to the surface.
The multilayer ceramic capacitor according to claim 8.
第1内部電極の少なくとも1つが放熱導体部と導通している、
ことを特徴とする請求項8〜11の何れか1項に記載の積層セラミックコンデンサ。
At least one of the first internal electrodes is in conduction with the heat dissipating conductor,
The multilayer ceramic capacitor according to claim 8, wherein the multilayer ceramic capacitor is any one of claims 8 to 11.
第2内部電極の少なくとも1つが放熱導体部と導通している、
ことを特徴とする請求項8〜11の何れか1項に記載の積層セラミックコンデンサ。
At least one of the second internal electrodes is in conduction with the heat dissipating conductor,
The multilayer ceramic capacitor according to claim 8, wherein the multilayer ceramic capacitor is any one of claims 8 to 11.
第1内部電極の少なくとも1つと第2内部電極の少なくとも1つが別々の放熱導体部に導通している、
ことを特徴とする請求項8〜11の何れか1項に記載の積層セラミックコンデンサ。
At least one of the first internal electrodes and at least one of the second internal electrodes are electrically connected to separate heat-radiating conductor portions,
The multilayer ceramic capacitor according to claim 8, wherein the multilayer ceramic capacitor is any one of claims 8 to 11.
第1内部電極と第2内部電極と放熱導体部の数はそれぞれ2以上であり、それぞれの放熱導体部には、第1内部電極または第2内部電極の何れかが導通している、
ことを特徴とする請求項8〜11の何れか1項に記載の積層セラミックコンデンサ。
The number of the first internal electrode, the second internal electrode, and the heat radiating conductor portion is 2 or more, and either the first internal electrode or the second internal electrode is electrically connected to each of the heat radiating conductor portions.
The multilayer ceramic capacitor according to claim 8, wherein the multilayer ceramic capacitor is any one of claims 8 to 11.
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