JP2005340479A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small semiconductor device capable of keeping operation in the state of no power supply from outside in various kinds of situations, and to provide a manufacturing method thereof. <P>SOLUTION: The device is provided with a circuit layer 102 with an integrated circuit formed on a semiconductor substrate 101, and provided with respectively different kinds of a power generation element 103 and a power generation element 104 on the circuit layer 102. The power generation element 103 and the power generation element 104 are connected with the integrated circuit at the circuit layer 102 by prescribed wiring. It is also possible to provide a circuit area 102a with the integrated circuit formed therein on the semiconductor substrate 101, and to provide the respectively different kinds of the power generation element 103 and the power generation element 104 in the other area of the semiconductor substrate 101. In this case, the power generation element 103 and the power generation element 104 are also connected with the integrated circuit in the circuit area 102a by the wiring. In the constitution, for example, the power generation element 103 is a thermoelectricity generation element, and the power generation element 104 is an oscillation power generating element. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device in which a thermoelectric power generation element and a vibration power generation element are monolithically provided on the same semiconductor substrate, and a manufacturing method thereof.

  Technological development is progressing on power supply for portable devices and micro sensors. Conventional small batteries such as button batteries are larger than the required dimensions and are not suitable for downsizing, so the use of a small power source utilizing changes in the environment is being studied. For example, a power source that uses a physical quantity such as vibration, heat, and weight as energy and converts it into electricity has been studied. Such a power generation element makes it possible to construct a network environment using a very small ubiquitous device.

  As the above-described small power source (power generation element), a vibration power generation element that uses vibration as energy for the first time has been proposed (see Non-Patent Document 1). As shown in FIG. 17, the vibration power generation element proposed in Non-Patent Document 1 includes an overlapping spring 1701, a spring 1702, a magnet 1703, and a coil 1704, which are accommodated in a cylindrical container 1705. . By combining this vibration power generation element with an LSI composed of a switch, a regulator, and a DSP, about 400 mW can be generated.

  As another vibration power generation element, a combination of a variable capacitance element and an LC circuit and a timing circuit has been proposed (see Non-Patent Document 2). The variable capacitor is composed of a weight attached to the tip of a leaf spring and a fixed counter electrode, and enables power generation by changing the distance from the counter electrode by shaking the leaf spring due to vibration. This power generation element is formed in a size of 2.5 cm × 7 cm and can generate power of 120 nW. In addition, as a similar vibration power generation element, there is one that can generate 100 μW of power by applying 1.2 kHz vibration (see Non-Patent Document 3).

  As the small power generation element described above, a thermoelectric power generation element 1801 as shown in FIG. 18 has been proposed (see Non-Patent Document 4). The thermoelectric generator 1801 includes about 100 pairs of thermocouples 210 made of n-BiTe and p-BiTe formed on a prism having a bottom surface of 80 μm × 80 μm and a height of 600 μm. In FIG. 18, the wiring is omitted. The thermoelectric power generation element 1801 can generate an electromotive force of 20 mV with a temperature difference of 1 ° C. due to the Seebeck effect generated at the contact point between n-BiTe and p-BiTe. The thermoelectric power generation element is incorporated in, for example, a wristwatch, and an example of operating with body temperature as an energy source is realized.

  As another thermoelectric power generation element, an element that forms a tantalum pattern and a polysilicon pattern on a semiconductor substrate and generates electric power using the Seebeck effect generated at the contact point of the two patterns has been proposed (Patent Document 1). reference). There has also been proposed a thermoelectric power generation element in which a thermocouple made of polysilicon and gold is formed on a silicon substrate and one of the contacts is separated from the substrate (see Non-Patent Document 5).

  As the small power generation element described above, a power generation element using ultrasonic waves as an energy source has also been proposed (see Patent Document 2). This is provided with a diaphragm, a coil, and a film magnet, and generates electricity using the displacement of the diaphragm caused by ultrasonic waves as an energy source.

The applicant has not yet found prior art documents related to the present invention by the time of filing other than the prior art documents specified by the prior art document information described in this specification.
JP-A-5-167105 JP-A-7-170713 R. Amirtharajah et al., "Self-powered signal processing using vibration-based power generation", IEEE J. Solid-state Circuits, vol.33, No.5, pp.687-695, 1998. M.Miyazaki et al., "Electric-energy generation using variable-capacitive resonator for power-free LSI: efficiency analysis and fundamental experiment", IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp.193-198, 2003 . T. Sterken et al., "Power extraction from ambient vibration", Workshop on Semiconductor Sensors (SeSens), pp. 680-683, 2002. M. Kishi et al ,. "Micro-thermoelectric modules and their application to wristwatches as an energy source", IEEE International Conference on Thermoelectrics (ICT), pp. 301-307, 1997. T. Toriyama et al., "Thermoelectric micro power generator utilizing self-standing polysilicon-metal thermopile", IEEE International Conference on MicroElectro Mechanical Systems (MEMS), pp. 562-565, 2001.

  However, since each of the conventional power generation elements described above uses only a single power generation method, the usable environment and situation are limited. For example, in order for a vibration power generation element to continuously generate power, it is necessary to always provide vibration, but the environment in which vibration always exists is very limited. Further, in the case of a thermoelectric power generation element, a temperature difference is generated inside the thermoelectric power generation element. Therefore, an environment in which there is always a heat flow and the temperature difference is refined is necessary to continue power generation. Similarly, for elements using ultrasonic power generation, a special environment in which an ultrasonic source is nearby is required.

  Furthermore, since the generated voltage / current signals are not constant because they are directly affected by the external environment and situation, a circuit for rectifying and amplifying the generated voltage and charge / discharge 2 A secondary battery is required. However, these circuits and secondary batteries are not formed integrally with the power generation element, and the conventional form has a problem that the size increases. For example, a module in which a control circuit and a secondary battery are combined with a conventional vibration power generation element has a large size, and it is difficult to arrange a large number as ultra-small ubiquitous devices. Moreover, the parasitic capacitance and resistance of the wiring connecting the power generation element and the circuit are large, and the power generation efficiency is lowered in the conventional form.

As described above, in the conventional technology, a single power generation method is used, and a device including a circuit becomes large. Thus, there is a problem in that the efficiency and the use environment and the situation are limited. there were. As a result, it has been difficult to realize a non-powered ultra-small ubiquitous device with the conventional technology.
The present invention has been made in order to solve the above-described problems, and it is possible to realize a smaller semiconductor device capable of maintaining an operation in a state where no power is supplied from the outside in various situations. With the goal.

A semiconductor device according to the present invention includes an integrated circuit layer formed on a semiconductor substrate, a thermoelectric power generation element that generates power by heat provided on the semiconductor substrate, and power generation by vibration provided on the semiconductor substrate. And a vibration power generation element that performs the above.
The semiconductor device may include a charge holding mechanism that is disposed on the semiconductor substrate and holds charges. For example, the charge holding mechanism may be constituted by a thin film battery that can be charged and discharged, and the charge holding mechanism may be constituted by a capacity in which an insulating film is sandwiched between two electrodes.

In the semiconductor device, the electric charge generated by the thermoelectric power generation element may be used for the vibration power generation element.
In the semiconductor device, the semiconductor substrate may include an insulating layer and a silicon layer made of single crystal silicon formed thereon.

  In addition, a method for manufacturing a semiconductor device according to the present invention includes a base region, an insulating layer formed thereon, and a partial region on a semiconductor substrate including a silicon layer made of single crystal silicon formed thereon. A step of forming an integrated circuit, a step of forming a first wiring pattern made of a silicon layer in the first power generation element region on the semiconductor substrate, and a part of the first wiring pattern in contact with the first wiring pattern Forming a second wiring pattern made of metal and forming a movable electrode made of metal and a capacitor electrode made of metal in the second power generation element region on the semiconductor substrate; and forming the movable electrode Removing a portion of the insulating layer, forming a space between the movable electrode and the base portion, and forming a support column for supporting the movable electrode on the base portion. Equipped with semiconductor substrate In the first power generation element region, a thermoelectric power generation element composed of a plurality of thermocouples composed of a first wiring pattern and a second wiring pattern is formed, and a movable electrode is formed in the second power generation element region of the semiconductor substrate. A vibration power generation element composed of a variable capacitor and a fixed electrode made of a capacitor electrode is formed.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a part on a semiconductor substrate including a base portion, an insulating layer formed thereon, and a silicon layer made of single crystal silicon formed thereon. A step of forming an integrated circuit in the region, a step of forming a first wiring pattern made of a silicon layer in the first power generation element region on the semiconductor substrate, and a second on the semiconductor substrate. A step of forming a movable electrode and a capacitor electrode made of a silicon layer in the power generation element region; a step of forming a second wiring pattern made of metal partially contacting the first wiring pattern; The insulating layer in a part of the region where the movable electrode is formed is removed, a space is formed between the movable electrode and the base portion, and a support column for supporting the movable electrode on the base portion is formed. Comprising the steps of: In a state where a thermoelectric power generation element composed of a plurality of thermocouples composed of a first wiring pattern and a second wiring pattern is formed in the first power generation element region of the conductor substrate, A vibration power generation element composed of a variable capacitor composed of a movable electrode and a fixed electrode composed of a capacitor electrode is formed.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a part on a semiconductor substrate including a base portion, an insulating layer formed thereon, and a silicon layer made of single crystal silicon formed thereon. A step in which an integrated circuit is formed in the region; a state in which a first wiring pattern made of a silicon layer is formed in the first power generation element region on the semiconductor substrate; and a second power generation on the semiconductor substrate. A step of forming two opposing walls made of a silicon layer in the element region, a second wiring pattern made of metal partially contacting the first wiring pattern, and the two walls A step of forming a support pillar made of metal disposed between and a vibrator made of metal disposed between two walls supported by the support pillar. 1 Power generation element area A thermoelectric power generation element composed of a plurality of thermocouples composed of a first wiring pattern and a second wiring pattern is formed, and in the second power generation element region of the semiconductor substrate, two walls and in the direction of the wall A vibration power generation element composed of a vibrating vibrator and a vibrator is formed.

  Further, another method of manufacturing a semiconductor device according to the present invention includes a step of forming an LSI in a partial region of an SOI layer on an SOI substrate, and a first resist having a first opening on the SOI layer. Forming a pattern, anisotropically etching the SOI layer through the first opening to expose the buried oxide layer, forming a silicon pattern, removing the first resist pattern, and an SOI substrate Forming a metal film on the metal film; forming a second resist pattern having a second opening on the metal film; and etching the metal film through the second opening to form the first metal film Forming a pattern, a second metal film pattern, and a third metal film pattern, a thermocouple comprising a silicon pattern and a first metal film pattern, a third metal film pattern, a buried oxide layer, and a silicon substrate below the buried oxide layer Forming a capacitor comprising: a step of removing the second resist pattern; and forming a third resist pattern having a third opening exposing a portion of the second metal film pattern on the SOI substrate. And a step of isotropically etching a part of the buried oxide layer under the second metal film pattern through the third opening to form a movable part made of the second metal film pattern and a part of the buried oxide layer. A step of forming a support portion and a step of removing the third resist pattern are provided.

  Further, another method of manufacturing a semiconductor device according to the present invention includes a step of forming an LSI in a partial region of an SOI layer on an SOI substrate, and a first resist having a first opening on the SOI layer. A step of forming a pattern, a step of anisotropically etching the SOI layer to a predetermined depth through the first opening to form an SOI pattern, a step of removing the first resist pattern, an SOI pattern and an SOI layer Forming a second resist pattern having a second opening exposing a part of the first SOI pattern, and anisotropically etching the SOI layer until the oxide layer is exposed through the second opening to expose the first SOI pattern. Forming a second SOI pattern and a third SOI pattern, forming a capacitor comprising the third SOI pattern, the buried oxide layer, and the silicon base portion below the second SOI pattern; and removing the second resist pattern. A step of forming a first metal film on the SOI substrate, a step of forming a third resist pattern having a third opening exposing a part of the first SOI pattern, and a third opening Forming a first metal pattern by plating, removing the third resist pattern, etching the first metal film using the first metal pattern as a mask, and an upper portion of the first SOI pattern and the first metal pattern Forming an insulating film having a fourth opening that exposes the upper portion of the second SOI pattern and the periphery of the second SOI pattern, a step of forming a second metal film, and an upper portion of the first SOI pattern and the first metal pattern Forming a fourth resist pattern having a fifth opening exposing the second metal pattern, forming a second metal pattern in the fifth opening by plating, and masking the second metal pattern. Etching the second metal film to form a first SOI pattern, a thermocouple composed of the first metal pattern and the second metal pattern, and a buried oxide layer under the second SOI pattern through the fourth opening. And a step of forming a support part made of a part of the buried oxide layer and a movable part made of the second SOI pattern by isotropically etching the part. Note that the insulating film may be removed.

  Further, another method of manufacturing a semiconductor device according to the present invention includes a step of forming an LSI in a partial region of an SOI layer on an SOI substrate, and a first resist having a first opening on the SOI layer. A step of forming a pattern, a step of anisotropically etching the SOI layer to a predetermined depth through the first opening to form an SOI pattern, a step of removing the first resist pattern, an SOI pattern and an SOI layer Forming a second resist pattern having a second opening exposing a part of the first SOI pattern, and anisotropically etching the SOI layer until the oxide layer is exposed through the second opening to expose the first SOI pattern. Forming a second SOI pattern and a third SOI pattern; removing a second resist pattern; and a third SOI pattern in a region around the second SOI pattern and the third SOI pattern. Forming a first insulating film so that the upper portion is exposed; forming a first metal film on the SOI substrate; exposing a part of the first SOI pattern, the third SOI pattern, and the upper portion of the first insulating film; Forming a third resist pattern having a third opening, forming a first metal pattern and a second metal pattern in the third opening by plating, and removing the third resist pattern. Etching the first metal film using the first metal pattern and the second metal pattern as a mask; and a second insulating film exposing an upper portion of the first SOI pattern, the second SOI pattern, the first metal pattern, and the second metal pattern Forming a second metal film on the SOI substrate, and a fourth opening exposing the first SOI pattern, the first metal pattern, and the second metal pattern. Forming a fourth resist pattern, forming a third metal pattern on the first SOI pattern and the first metal pattern in the fourth opening by plating, and forming a fourth metal pattern on the second metal pattern. Forming a thermocouple comprising the first SOI pattern, the first metal pattern, and the third metal pattern, etching the second metal pattern using the third metal pattern and the fourth metal pattern as a mask, And removing the first insulating film and the second insulating film to form a movable part composed of the third SOI pattern, the second metal pattern, and the fourth metal pattern, and forming a capacitor composed of the movable part and the second SOI pattern. It is a thing.

  Further, another method of manufacturing a semiconductor device according to the present invention includes a step of forming an LSI in a partial region of an SOI layer on an SOI substrate, and a first resist having a first opening on the SOI layer. A step of forming a pattern, a step of anisotropically etching the SOI layer to a predetermined depth through the first opening to form an SOI pattern, a step of removing the first resist pattern, an SOI pattern and an SOI layer Forming a second resist pattern having a second opening in which a part of the first SOI pattern is exposed, and embedding the SOI layer through the second opening and performing anisotropic etching until the oxide layer is exposed to form a first SOI pattern Forming a second SOI pattern and a third SOI pattern; removing a second resist pattern; and a third SOI pattern in a region around the second SOI pattern and the third SOI pattern. Forming a first insulating film so that the upper portion is exposed; forming a first metal film on the SOI substrate; exposing a part of the first SOI pattern, the third SOI pattern, and the upper portion of the first insulating film; Forming a third resist pattern having a third opening, forming a first metal pattern and a second metal pattern in the third opening by plating, and removing the third resist pattern. Etching the first metal film using the first metal pattern and the second metal pattern as a mask; and a second insulating film exposing the first SOI pattern, the second SOI pattern, the first metal pattern, and the upper part of the second metal pattern. A step of forming, a step of forming a second metal film on the SOI substrate, and a fourth opening for exposing the first SOI pattern, the first metal pattern, and the upper portion of the second metal pattern. Forming a fourth resist pattern, forming a third metal pattern on the first SOI pattern and the first metal pattern in the fourth opening by plating, and forming a fourth metal on the second metal pattern. Forming a pattern, etching the second metal film using the third metal pattern and the fourth metal pattern as a mask, and forming a thermocouple including the first SOI pattern, the first metal pattern, and the third metal pattern; Forming a third insulating film so as to cover the fourth metal pattern; forming a third metal film on the SOI substrate; and a fifth resist including a fifth opening on the third metal film. A step of forming a pattern, a step of forming a fifth metal pattern by plating in the fifth opening, a step of removing the fifth resist pattern, and a third metal film using the fifth metal pattern as a mask. Etching to form a protective film made of the fifth metal pattern on the third insulating film; and isotropically etching the first insulating film, the second insulating film, and the third insulating film to form the third SOI pattern and the first insulating film. Forming a movable part composed of the second metal pattern and the fourth metal pattern, and forming a capacitor composed of the movable part and the second SOI pattern. Note that a film may be formed on the protective film by being attached by the STP method.

  Further, another method of manufacturing a semiconductor device according to the present invention includes a step of forming an LSI in a partial region of an SOI layer on an SOI substrate, and a first resist having a first opening on the SOI layer. A step of forming a pattern, a step of anisotropically etching the SOI layer to a predetermined depth through the first opening to form an SOI pattern, a step of removing the first resist pattern, an SOI pattern and an SOI layer Forming a second resist pattern having a second opening in which a part of the first SOI pattern is exposed, and embedding the SOI layer through the second opening and performing anisotropic etching until the oxide layer is exposed to form a first SOI pattern A process of forming a second SOI pattern, a third SOI pattern, and a fourth SOI pattern, and forming a capacitor comprising the fourth SOI pattern, a buried oxide layer, and a silicon base portion under the buried oxide layer. A step of removing the second resist pattern, a step of forming a first insulating film that covers only the third SOI pattern in a region around the second SOI pattern and the third SOI pattern, and a first metal film on the SOI substrate. Forming a third resist pattern having a third opening exposing a part of the first SOI pattern and an upper portion of the first insulating film; and plating the first metal pattern on the third opening by plating. Forming a second metal pattern, removing the third resist pattern, etching the first metal film using the first metal pattern and the second metal pattern as a mask, and a first SOI pattern and a second SOI pattern. Forming a second insulating film exposing the top of the first metal pattern and the second metal pattern, forming a second metal film on the SOI substrate, Forming a fourth resist pattern having a fourth opening through which an upper portion of the SOI pattern, the second SOI pattern, the first metal pattern, and the second metal pattern is exposed; and a first SOI pattern of the fourth opening by plating. Forming a third metal pattern on the first metal pattern, forming a fourth metal pattern on the second SOI pattern and the second metal pattern, and using the third metal pattern and the fourth metal pattern as a mask. Etching the two metal films to form a first SOI pattern, a thermocouple composed of the first metal pattern and the third metal pattern, removing the first insulating film and the second insulating film, and removing the second SOI pattern and the second metal film; Forming a movable part composed of the pattern and the fourth metal pattern, and forming a capacitor composed of the movable part and the third SOI pattern. The

As described above, according to the present invention, since the power generation elements of different forms are provided on the same substrate, it is possible to maintain a non-powered operation from the outside in various situations. An excellent effect that a semiconductor device can be realized is obtained.
According to the present invention, for example, vibration power generation is performed when vibration is applied from the outside, and thermoelectric power generation can be performed in a situation where heat is applied. Further, since the integrated circuit is formed on the same substrate, it is possible to electrically connect a plurality of power generating elements to improve control efficiency.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a perspective view schematically showing a configuration example of a semiconductor device according to an embodiment of the present invention. The semiconductor device illustrated in FIG. 1A includes a circuit layer 102 in which an integrated circuit is formed over a semiconductor substrate 101, and includes different types of power generation elements 103 and 104 on the circuit layer 102. . The power generation element 103 and the power generation element 104 are connected to the integrated circuit of the circuit layer 102 by wiring (not shown).

  In addition, the semiconductor device illustrated in FIG. 1B includes a circuit region 102a in which an integrated circuit is formed over a semiconductor substrate 101, and different types of power generation elements 103 and power generation units in other regions of the semiconductor substrate 101. Element 104. The power generation element 103 and the power generation element 104 are connected to the integrated circuit in the circuit region 102a by wiring (not shown). In these configurations, for example, the power generation element 103 is a thermoelectric power generation element, and the power generation element 104 is a vibration power generation element.

  Hereinafter, the semiconductor device illustrated in FIG. 1B will be described in more detail with reference to FIG. FIG. 2 is a cross-sectional view (a) and a plan view (b) schematically showing a more specific example of the semiconductor device shown in FIG. As shown in FIG. 2, the semiconductor substrate 101 is an SOI substrate composed of a silicon base portion 105, a buried oxide layer 106, and an SOI (Silicon on Insulator) layer 107 made of p-type single crystal silicon. 2 illustrates an example in which the circuit region 102a, the power generation element 103, and the power generation element 104 are linearly arranged, and the arrangement is different from the example of FIG. 1B.

  The power generation element 103 is a thermoelectric power generation element including a plurality of thermocouples 113. The thermocouple 113 includes a wiring pattern (first wiring pattern) 114 made of p-type silicon single crystal and a wiring pattern (first wiring pattern) made of chromium. 2 wiring patterns) 115. The wiring pattern 114 is formed by processing the SOI layer 107. For example, the contact between the wiring pattern 114 and one wiring pattern 115 is set to a low temperature state, and the contact between the wiring pattern 114 and the other wiring pattern 115 is set to a high temperature state. Electric power is obtained.

  The power generation element 104 is a vibration power generation element including a variable capacitor 119 and a fixed capacitor (charge holding mechanism) 120. The variable capacitor 119 includes a movable electrode 122 that is partially supported by a support column 123 made of an insulating material, and a silicon base portion 105 in a region below the movable electrode 122. The movable electrode 122 is formed, for example, in a rectangular shape in plan view, and is supported by the support pillar 123 at a portion close to the right side of the drawing in FIG. 2B, and is movable from the support beam area to the lower portion of the left side of the drawing. Provide space. As shown in FIG. 2B, the movable electrode 122 includes a plurality of through holes 121. The through holes 121 are used to form a lower space, as will be described in the subsequent manufacturing method. .

The fixed capacitor 120 includes a capacitor electrode 124, a buried oxide layer 106 in a region below the capacitor electrode 124, and a silicon base portion 105 in the region below the capacitor electrode 124. The silicon substrate 105 is connected to the ground.
The power generation element 103 and the power generation element 104 (the variable capacitor 119 and the fixed capacitor 120) are connected to a predetermined circuit (element) constituting the circuit region 102a by the wiring 126. The circuit region 102a is provided with a pad terminal 112 for inputting / outputting signals to / from the outside.

  Next, an equivalent circuit configuration example of the semiconductor device illustrated in FIG. 2 will be described with reference to FIG. In the circuit example shown in FIG. 3A, the circuit constituting the circuit region 102a includes three switch elements 130, 131, and 132. The electromotive force of the power generating element 103 can be taken out by turning on the switch element 130 and turning off the switch element 131 and the switch element 132. Further, the power generated by the power generation element 104 can be taken out by turning off the switch element 130 and turning on the switch element 131 and the switch element 132.

  In the circuit example shown in FIG. 3B, the charge generated in the power generation element 103 is used for the power generation element 104. The switch element 133 and the switch element 134 are turned on while the power generation element 103 is generating electricity, and the charge generated in the power generation element 103 is moved to the variable capacitor 119. Note that, when an external load is connected, the charge moves to the fixed capacitor 120 through the external load.

  As described above, after the charge generated by the Seebeck effect is moved, when the switch element 133 is turned off and vibration is applied, the charged charge moves in accordance with the capacitance change of the variable capacitor 119 to generate a current. . As described above, according to the circuit example shown in FIG. 3B, it is not necessary to apply an electric charge from the outside in order to make the power generation element 104 which is a vibration power generation element function.

  The circuit example shown in FIG. 3C is obtained by adding a capacitor element 135 and switch elements 136 and 137 to the circuit example shown in FIG. When the switch element 133 is turned off, the switch element 136 and the switch element 137 are turned on, and the power generation element 103 generates an electromotive force, electric charge is accumulated (charged) in the capacitor 135. After this state, when the switch element 137 is turned off and the switch element 133 and the switch element 134 are turned on, charge is accumulated in the variable capacitor 119. In the circuit example shown in FIG. 3C, more charges can be stored in the variable capacitor 119 than in the circuit example shown in FIG.

  After the electric charge is accumulated in the variable capacitor 119, when the power generation element 104 is caused to function by turning off the switch element 133, a current is generated as described above. According to the circuit example shown in FIG. 3C, as described above, a larger amount of charge can be accumulated by the variable capacitor 119, and therefore, more than the circuit example shown in FIG. 3B. It becomes possible to generate electric power. Note that the above-described switch element can be formed of a well-known transistor such as a MOS transistor, for example.

Next, an example of a method for manufacturing the semiconductor device shown in FIG. 2 will be described.
First, as shown in FIG. 4A, an SOI substrate (semiconductor substrate 101) including a silicon base portion 105, a buried oxide layer 106, and an SOI layer 107 is prepared, and a circuit region 102a is formed by a well-known LSI process. Form. For example, the buried oxide layer 106 has a thickness of 0.5 μm, and the SOI layer 107 has a thickness of 20 μm.

  Next, the SOI layer 107 is finely processed by a known photolithography technique and etching technique, and as shown in FIG. 4B, a wiring pattern 114 made of p-type silicon single crystal constituting the SOI layer 107 is formed. Is formed. For example, a resist pattern (not shown) that protects the circuit region 102a and leaves the wiring pattern 114 is formed, and the SOI layer 107 is selectively etched by anisotropic dry etching using the formed resist pattern as a mask. Thus, the wiring pattern 114 can be formed.

Next, after removing the resist pattern described above, as shown in FIG. 4C, a metal film 108 made of Cr is formed by vapor deposition or the like.
Next, the metal film 108 is processed by a known photolithography technique and etching technique, and as shown in FIG. 4D, the pad terminal 112, the wiring pattern 115, the movable electrode 122, and the capacitor electrode 124 are formed. To do.

  Through the above-described steps, the power generation element 103 including the plurality of thermocouples 113 shown in FIG. 2 is formed from the wiring pattern 114 and the wiring pattern 115. In the region of the capacitor electrode 124, the fixed capacitor 120 shown in FIG. 2 is formed from the buried oxide layer 106 in the lower region and the silicon base portion 105 in the lower region. Although not shown, each wiring 126 shown in FIG. 2 is also formed at the same time. 3 is used, a metal pattern similar to that of the capacitor electrode 124 may be formed in other regions not shown in FIG.

  Next, a resist pattern 140 having an open region for forming the variable capacitor 119 shown in FIG. 2 is formed (FIG. 4E), and the buried oxide layer 106 is etched using the resist pattern 140 as a mask. For example, the buried oxide layer 106 is etched by wet etching so that the bottom of the movable electrode 122 is etched.

  At this time, as shown in FIG. 2A, since the movable electrode 122 includes the through hole 121, the buried oxide layer 106 in the region under the through hole 121 is removed earlier. As a result, as shown in FIG. 4F, a state is obtained in which the support pillar 123 that supports the end of the movable electrode 122 is formed below the movable electrode 122. The movable electrode 122 constitutes the variable capacitor 119 shown in FIG. FIG. 4F shows a state after the resist pattern 140 is removed.

  In other regions not shown, a metal pattern similar to the capacitor electrode 124 is formed on the buried oxide layer 106, an insulating film is formed on the formed metal pattern, and a new metal is formed on the insulating film. Patterns may be formed to form the capacitor 135 shown in FIG. The fixed capacitance by the capacitance electrode 124 is a MIS (Metal-Insulator-Semiconductor) capacitance, but the capacitance according to the above-described configuration is a MIM (Metal-Insulator-Metal) capacitance. The fixed capacitor may be a structure in which an insulating film is sandwiched between two electrodes.

  Next, another configuration example of the semiconductor device according to the embodiment of the present invention will be described together with a manufacturing method example. FIG. 5 is a plan view illustrating a configuration of the semiconductor device in this embodiment. The semiconductor device illustrated in FIG. 5 includes a circuit region 102a, a power generation element 503 using thermoelectric power generation, and power generation using vibration power generation on the same substrate. And an element 504. The power generation element 503 and the power generation element 504 are connected to the integrated circuit in the circuit region 102 a by a wiring 526.

  The power generation element 503 is a thermoelectric power generation element composed of a plurality of thermocouples 513, and the thermocouple 513 is composed of a wiring pattern 514 made of p-type silicon single crystal and a wiring pattern 515 made of gold (Au). ing. For example, the contact of the wiring pattern 514 with one wiring pattern 515 is set to a low temperature state, and the contact of the wiring pattern 514 with the other wiring pattern 515 is set to a high temperature state, so that a voltage of about 0.45 mV / K is generated by the Seebeck effect. Electric power is obtained.

  The power generation element 504 is a vibration power generation element configured with a variable capacity and a fixed capacity. The variable capacitance of the power generation element 504 is composed of a movable electrode 522 that is partially supported by a support column 523 made of an insulating material, and a silicon base portion 105 in a region below the movable electrode 522. The movable electrode 522 is made of p-type silicon single crystal, for example, is formed in a rectangular shape in plan view, and is supported by the support column 523 at a portion close to the right side of the drawing in FIG. A space for movement is provided at the bottom. As shown in FIG. 5, the movable electrode 522 includes a plurality of through holes 521, and the through holes 521 are used to form a lower space as will be described later in the manufacturing method.

  The fixed capacity of the power generation element 504 is composed of a capacity electrode 524, a buried oxide layer 106 in a region below the capacitor electrode 524, and a silicon base portion 105 in the region below. In the semiconductor device shown in FIG. 5, the capacitor electrode 524 is made of p-type silicon single crystal, like the movable electrode 522. The silicon substrate 105 is connected to the ground.

  The power generation element 503 and the power generation element 504 (variable capacity, fixed capacity) are connected to a predetermined circuit (element) constituting the circuit region 102a by a wiring 526. The circuit region 102a is provided with a pad terminal 112 for inputting / outputting signals to / from the outside. The connection relationship between the power generation element 503 and the power generation element 504 and the integrated circuit forming the circuit region 102a is the same as that of the semiconductor device illustrated in FIG.

Next, an example of a method for manufacturing the semiconductor device shown in FIG. 5 will be described.
First, as shown in FIG. 6A, a semiconductor substrate 101 having an SOI structure including a silicon base portion 105, a buried oxide layer 106, and an SOI layer 107 is prepared, and a circuit region 102a is formed by a well-known LSI process. To do.

Next, as shown in FIG. 6B, a resist pattern 601 is formed on the SOI layer 107 by a known photolithography technique. Next, using the resist pattern 601 as a mask, the SOI layer 107 is etched to a thickness of about 0.5 μm to form a pattern. For example, the etching may be performed by dry etching using a mixed gas of CF ₄ and O ₂ .

  Next, after removing the resist pattern 601, as shown in FIG. 6C, the resist pattern 602 is formed on the SOI layer 107 on which the pattern is formed by a known photolithography technique. Next, using the resist pattern 602 as a mask, the SOI layer 107 is etched up to the buried oxide layer 106 to form a wiring pattern 514, a movable electrode 522, and a capacitor electrode 524.

  Thus, in this configuration example, the movable electrode 522 and the capacitor electrode 524 are made of single crystal silicon which is a semiconductor. Further, the wiring pattern 514 is formed in an L shape in cross section by the etching process using the resist pattern 601 and the etching process using the resist pattern 602.

  Next, after removing the resist pattern 602, a seed layer (not shown) is formed on the substrate surface including the exposed region of the buried oxide layer 106, the wiring pattern 514, the movable electrode 522, and the capacitor electrode 524. . The seed layer includes a titanium layer having a thickness of 0.1 μm and a gold layer having a thickness of 0.1 μm, and each may be formed by vapor deposition. After the seed layer is formed in this way, a resist pattern 603 is formed as shown in FIG. The resist pattern 603 is a mask pattern having an opening above the end of the thin portion of the wiring pattern 514.

  Next, an Au pattern was formed by gold plating on a seed layer (not shown) exposed at the bottom of the opening of the resist pattern 603, and a metal pattern 701 was formed as shown in FIG. State. The metal pattern 701 is formed so that the height of the upper surface is equal to the height of the upper surface of the thick part of the wiring pattern 514. Next, after removing the resist pattern 603, the seed layer is etched away using the metal pattern 701 as a mask.

  Next, as shown in FIG. 7F, an insulating layer 702 is formed in which a region where the variable capacitor formed of the movable electrode 522 shown in FIG. 5 is formed is opened. The insulating layer 702 is formed so that the upper surface of the thick portion of the wiring pattern 514 and the upper surface of the metal pattern 701 are exposed.

  The formation example of the insulating layer 702 will be described in detail. First, a coating resin is formed by spin-coating a photosensitive resin based on polybenzoxazole. Next, a latent image is formed by selectively exposing the upper surface of the thick portion of the wiring pattern 514, the upper surface of the metal pattern 701, and the region to be the opening by a known photolithography technique. Next, the insulating layer 702 can be formed by removing the portion of the latent image by development processing and heat-curing the pattern formed by the development processing.

  Next, a seed layer (not shown) is formed on the insulating layer 702 including the upper surface of the thick part of the wiring pattern 514 and the upper surface of the metal pattern 701. The seed layer includes a titanium layer having a thickness of 0.1 μm and a gold layer having a thickness of 0.1 μm, and each may be formed by vapor deposition. Next, a resist pattern is formed on the seed layer, and an Au pattern is formed by plating on the seed layer exposed at the bottom of the opening of the resist pattern, as shown in FIG. It is assumed that the pad terminal 112 and the wiring pattern 515 made of gold (Au) are formed.

Through the above-described steps, the power generation element 503 including the plurality of thermocouples 513 illustrated in FIG. 5 is formed from the wiring pattern 514 and the wiring pattern 515.
FIG. 7G shows a state after the resist pattern is removed and an unnecessary seed layer is removed by etching using the pad terminal 112 and the wiring pattern 515 as a mask.

Next, using the insulating layer 702 as a mask, a part of the buried oxide layer 106 is removed from the opening of the insulating layer 702 by, for example, wet etching. In this etching, the buried oxide layer 106 is etched and removed to the lower part of the movable electrode 522.
At this time, as shown in FIG. 5, since the movable electrode 522 includes the through hole 521, the buried oxide layer 106 in the region under the through hole 521 is removed earlier.

As a result, as shown in FIG. 7H, a state is obtained in which the support pillar 523 that supports the end of the movable electrode 522 is formed below the movable electrode 522. The movable electrode 522 constitutes a variable capacitor of the power generation element 504 shown in FIG.
As shown in FIG. 7I, the insulating layer 702 may be removed by a dry etching method or the like so that a space is formed below the wiring pattern 515 constituting the thermocouple 513. By forming the space, heat conduction in the vicinity of the wiring pattern 515 can be suppressed, and the temperature difference for obtaining the Seebeck effect can be further increased.

  Next, another configuration example of the semiconductor device according to the embodiment of the present invention will be described with reference to FIGS. FIG. 8 is a plan view illustrating a configuration of the semiconductor device in this embodiment. The semiconductor device illustrated in FIG. 8 includes a circuit region 102a, a power generation element 503 using thermoelectric power generation, and power generation using vibration power generation on the same substrate. An element 804. The power generation element 503 and the power generation element 804 are connected to the integrated circuit in the circuit region 102 a by a wiring 526. The semiconductor device shown in FIG. 8 is obtained by changing the power generation element 504 of the semiconductor device shown in FIG.

  The power generation element 804 is a vibration power generation element that includes a vibrator 841 and two walls 843 and 844 arranged on both sides of the vibrator 841. The vibrator 841 is supported by the support pillar 842 on the buried oxide layer 106 in the region where the buried oxide layer 106 is exposed. The vibrator 841 vibrates so as to be displaced toward the wall 843 or the wall 844 by an external force. The vibrator 841 is supported by the support column 824 at the center, and includes a weight structure 841a at the lower part (on the buried oxide layer 106 side) on both sides of the support column 814.

When the vibrator 841 is displaced toward the wall 843, the vibrator 841 and the wall 843 come close to each other, and the vibrator 841 and the wall 844 are separated from each other. At this time, the capacitance between the transducer 841 and the wall 843 increases, and the capacitance between the transducer 841 and the wall 844 decreases.
On the other hand, when the vibrator 841 is displaced toward the wall 844, the vibrator 841 and the wall 844 are brought closer, and the vibrator 841 and the wall 843 are separated. At this time, the capacity between the vibrator 841 and the wall 844 increases, and the capacity between the vibrator 841 and the wall 843 decreases.
In this way, the electric charges move when the vibrator 841 vibrates.

  Accordingly, when the capacitance between the vibrator 841 and the walls 843 and 844 is connected via an external load and the electric charge is given to the vibrator 841, the vibrator 841 vibrates to move the electric charge, thereby causing the external load to move. A current starts to flow through. Thus, the power generation element 804 is a vibration power generation element that converts vibration into electric power.

  Note that the power generation element 503 and the power generation element 804 are connected to a predetermined circuit (element) constituting the circuit region 102 a by a wiring 826. The circuit region 102a is provided with a pad terminal 112 for inputting / outputting signals to / from the outside. The connection relationship between the power generation element 503 and the power generation element 804 and the integrated circuit forming the circuit region 102a is the same as that of the semiconductor device illustrated in FIG.

Next, an example of a method for manufacturing the semiconductor device shown in FIG. 8 will be described.
First, as shown in FIG. 9A, an SOI structure semiconductor substrate 101 including a silicon base portion 105, a buried oxide layer 106, and an SOI layer 107 is prepared, and a circuit region 102a is formed by a well-known LSI process. To do. Further, a pattern having a depth of about 0.5 μm is formed on the SOI layer 107 by a known photolithography technique.

  Next, the SOI layer 107 is etched to the buried oxide layer 106 using a predetermined mask pattern, and as shown in FIG. 9B, a wiring pattern 514, walls 843, 844, and a column lower portion 842a are formed. And Therefore, the wiring pattern 514, the walls 843, 844, and the column lower portion 842a are made of single crystal silicon which is a semiconductor. Further, the wiring pattern 514 and the walls 843 and 844 are formed at a height of about 20 μm, which is equal to the thickness of the SOI layer 107. Up to this point, the process is the same as the formation of the wiring pattern 514 in FIGS. 6A to 6C.

  Next, a photosensitive organic resin based on polybenzoxazole is used and processed by a photolithography technique to form an insulating layer 901 as shown in FIG. 9C. The insulating layer 901 is formed to have the same thickness as the column lower portion 842a, and is formed so as to fill between the column lower portion 842a and the walls 843, 844.

  Next, a seed layer (not shown) is formed on the surface of the substrate including the exposed region of the buried oxide layer 106, the wiring pattern 514, the walls 843, 844, the column lower portion 842a, and the insulating layer 901. The seed layer includes a titanium layer having a thickness of 0.1 μm and a gold layer having a thickness of 0.1 μm, and each may be formed by vapor deposition.

  After the seed layer is formed in this way, a seed layer (not shown) exposed at the bottom of the opening is formed using a resist pattern in which the regions where the support pillars 842 and the weight structures 841a are formed are opened as shown in FIG. 9), an Au pattern is formed by gold plating, and as shown in FIG. 9D, the metal pattern 701, the support column 842, and the weight structure 841a are formed. The metal pattern 701 is formed so that the height of the upper surface is equal to the height of the upper surface of the thick part of the wiring pattern 514. Thus, the support pillar 842 and the weight structure 841a are metal structures made of gold.

  Next, using the gold plating pattern formed as described above as a mask, the unnecessary seed layer is removed by etching, and then an insulating layer 1001 is formed as shown in FIG. The insulating layer 1001 is such that the upper surface of the thick portion of the wiring pattern 514, the upper surface of the metal pattern 701, the upper surfaces of the thick portions of the two walls 843 and 844, and the upper surface of the weight structure 841a are exposed. Form.

  The formation example of the insulating layer 1001 will be described in detail. First, a photosensitive resin based on polybenzoxazole is spin-coated to form a coating film. Next, a latent image is formed by selectively exposing the above-described upper surface region to be exposed by a known photolithography technique. Next, the insulating layer 1001 can be formed by removing the portion of the latent image by the development process, and heat-curing the pattern formed by the development process.

  Next, a seed layer (not shown) is formed on the insulating layer 1001. The seed layer includes a titanium layer having a thickness of 0.1 μm and a gold layer having a thickness of 0.1 μm, and each may be formed by vapor deposition. Next, a resist pattern is formed on the seed layer, and an Au pattern is formed by plating on the seed layer exposed at the bottom of the opening of the resist pattern, as shown in FIG. It is assumed that the pad terminal 112, the wiring pattern 515 made of gold (Au), and the vibrator 841 are formed. Thereafter, the excess seed layer is removed by etching using the plating pattern as a mask.

Through the above-described steps, the power generation element 503 including the plurality of thermocouples 513 illustrated in FIG. 8 is formed from the wiring pattern 514 and the wiring pattern 515.
FIG. 10F shows a state after the resist pattern is removed.
Thereafter, by removing the insulating layer 901 and the insulating layer 1001 by dry etching, as shown in FIG. 10G, the transducer 841 provided with the weight structure 841a and the buried oxide layer 106 or between the thermoelectric elements 106 A space is formed below the wiring pattern 515 constituting the pair 513.

By the way, as shown in the plan view of FIG. 11, a protective layer 846 may be provided on the upper surface of the vibrator 841.
Hereinafter, the formation of the protective layer 846 will be described. First, in the same manner as described with reference to FIGS. 9A to 10F, as shown in FIG. 112, a wiring pattern 515 made of gold (Au), a vibrator 841, and the like are formed. However, in this case, the walls 843 and 844 are formed to extend so as to cover the periphery of the vibrator 841. Further, the metal pattern 1201 is also formed on the upper end of the thick portion of the walls 843, 844.

Next, as illustrated in FIG. 13A, the insulating layer 1301 that covers the vibrator 841 is formed by using a photosensitive organic resin.
Next, a seed layer composed of a titanium layer with a thickness of 0.1 μm and a gold layer with a thickness of 0.1 μm is formed over the entire area of the substrate, a resist pattern in which a predetermined region is opened is formed, and an open portion is formed. By performing gold plating, the metal pattern 1302 and the metal pattern 1303 are formed as shown in FIG. The metal pattern 1303 is partially provided with a through hole.

  Thereafter, the insulating layer 901, the insulating layer 1001, and the insulating layer 1301 are removed by dry etching, for example, and as shown in FIG. 13D, the vibrator 841 including the weight structure 841a and the buried oxide layer 106 are separated. It is assumed that a space is formed between and under the wiring pattern 515 constituting the thermocouple 513. In the region of the vibrator 841, the insulating layer 1301, the insulating layer 1001, and the insulating layer 901 are removed through the through hole of the metal pattern 1302.

  Through the above-described steps, the vibrator 841 is stored in the internal space of the container having the metal pattern 1302 as an upper wall and the metal pattern 1201 and the walls 843 and 844 as side walls. The metal pattern 1302 serving as the upper wall becomes the protective layer 846 shown in FIG. Further, for example, as shown in FIG. 13D, an insulating protective film 1310 may be formed by STP (Spin-coating film Transfer and hot-Pressing) to close the opening of the metal pattern 1302. .

  Next, another configuration example of the semiconductor device according to the embodiment of the present invention will be described with reference to FIGS. FIG. 14 is a plan view illustrating a configuration of the semiconductor device in this embodiment. The semiconductor device illustrated in FIG. 14 includes a circuit region 102a, a power generation element 503 using thermoelectric power generation, and power generation using vibration power generation on the same substrate. And an element 1404. The power generation element 503 and the power generation element 1404 are connected to the integrated circuit in the circuit region 102 a by a wiring 826. The semiconductor device shown in FIG. 14 is obtained by changing the power generation element 804 of the semiconductor device shown in FIG.

  The power generation element 1404 includes a diaphragm-shaped movable flat plate 1441 that vibrates in the normal direction of the substrate plane, a weight structure 1445 provided below the movable flat plate 1441, support columns 1443 and 1444 that support both ends of the movable flat plate 1441, And a variable capacitor by the fixed electrode 1446 and a fixed capacitor by the capacitor electrode 1447. Due to an external force, the movable flat plate 1441 vibrates in the normal direction of the substrate plane.

  In a state where the fixed capacitor and the variable capacitor are connected via an external load and the movable plate 1441 is charged, the movable plate 1441 vibrates and the capacitance of the variable capacitor changes to move the charge. Current will flow. Thus, the power generation element 1404 is a vibration power generation element that converts vibration into electric power.

Next, an example of a method for manufacturing the semiconductor device shown in FIG. 14 will be described.
First, as shown in FIG. 15A, a semiconductor substrate 101 having an SOI structure including a silicon base portion 105, a buried oxide layer 106, and an SOI layer 107 is prepared, and a circuit region 102a is formed by a well-known LSI process. To do. Further, a pattern having a depth of about 0.5 μm is formed on the SOI layer 107 by a known photolithography technique.

  Next, the SOI layer 107 is etched up to the buried oxide layer 106 using a predetermined mask pattern, and as shown in FIG. 15B, a wiring pattern 514, support pillars 1443 and 1444, a fixed electrode 1446, and a capacitor electrode 1447 are obtained. Is formed. Therefore, the wiring pattern 514, the support pillars 1443 and 1444, the fixed electrode 1446, and the capacitor electrode 1447 are made of single crystal silicon which is a semiconductor. Further, the wiring pattern 514 and the support pillars 1443 and 1444 are formed to a height of about 20 μm, which is equal to the thickness of the SOI layer 107. Up to this point, the process is the same as the formation of the wiring pattern 514 in FIGS. 6A to 6C.

  Next, a photosensitive organic resin based on polybenzoxazole is used and processed by a photolithography technique to form an insulating layer 1501 as shown in FIG. 15C. The insulating layer 1501 is formed so as to cover the fixed electrode 1446 and is formed so as to fill a space between the support column 1443 and the support column 1444.

  Next, a seed layer (not shown) is formed on the substrate surface including the exposed region of the buried oxide layer 106, the wiring pattern 514, the support pillars 1443 and 1444, the fixed electrode 1446, the capacitor electrode 1447 and the insulating layer 1501. And The seed layer includes a titanium layer having a thickness of 0.1 μm and a gold layer having a thickness of 0.1 μm, and each may be formed by vapor deposition.

  After the seed layer is formed in this way, a resist pattern in which a region where the weight structure 1445 is formed shown in FIG. 14 is opened is used to form a seed layer (not shown) exposed at the bottom of the opening. Then, an Au pattern is formed by gold plating, and the metal pattern 701 and the weight structure 1445 are formed as shown in FIG. Thus, the weight structure 1445 is a metal structure made of gold. The metal pattern 701 is formed so that the height of the upper surface is equal to the height of the upper surface of the thick portion of the wiring pattern 514.

  Next, using the gold plating pattern formed as described above as a mask, an unnecessary seed layer is removed by etching, and then an insulating layer 1502 is formed as shown in FIG. The insulating layer 1502 is formed in a state in which the upper surface of the thick portion of the wiring pattern 514, the upper surface of the metal pattern 701, the upper surfaces of the thick portions of the support pillars 1443 and 1444, and the upper surface of the weight structure 1445 are exposed. To do.

  The formation example of the insulating layer 1502 will be described in detail. First, a photosensitive resin based on polybenzoxazole is spin-coated to form a coating film. Next, a latent image is formed by selectively exposing the above-described upper surface region to be exposed by a known photolithography technique. Next, the insulating layer 1502 can be formed by removing a portion of the latent image by development processing, and heat-curing the pattern formed by the development processing.

  Next, a seed layer (not shown) is formed on the insulating layer 1502. The seed layer includes a titanium layer having a thickness of 0.1 μm and a gold layer having a thickness of 0.1 μm, and each may be formed by vapor deposition. Next, a resist pattern is formed on the seed layer, and an Au pattern is formed by plating on the seed layer exposed at the bottom of the opening of the resist pattern, as shown in FIG. The pad terminal 112, the wiring pattern 515 made of gold (Au), and the movable flat plate 1441 are formed. Thereafter, the excess seed layer is removed by etching using the plating pattern as a mask.

Through the above-described steps, the power generation element 503 including the plurality of thermocouples 513 illustrated in FIG. 14 is formed from the wiring pattern 514 and the wiring pattern 515. FIG. 15F shows a state after the resist pattern is removed.
Thereafter, the insulating layer 1501 and the insulating layer 1502 are removed by dry etching, so that the movable plate 1441 provided with the weight structure 1445 and the buried oxide layer 106 can be connected to each other as shown in FIG. A space is formed below the wiring pattern 515 constituting the pair 513.

  Next, another configuration example of the semiconductor device according to the embodiment of the present invention will be described with reference to FIG. FIG. 16 is a perspective view (a), (b) and a schematic cross-sectional view (c) showing the configuration of the semiconductor device according to the present embodiment. A semiconductor device illustrated in FIG. 16A includes a circuit layer 102 in which an integrated circuit is formed over a semiconductor substrate 101, and includes different types of power generation elements 103 and 104 on the circuit layer 102. .

  The power generation element 103 and the power generation element 104 are connected to the integrated circuit of the circuit layer 102 by wiring (not shown). In addition, the semiconductor device illustrated in FIG. 16A includes a thin film battery (thin film battery) 1601 under the semiconductor substrate 101. The thin film battery 1601 is a chargeable / dischargeable secondary battery, and supplies power by connecting to the circuit layer 102 through a through electrode formed in the semiconductor substrate 101. The thin film battery 1601 is, for example, a charge holding mechanism, similar to the fixed capacity 120 shown in FIG.

  In addition, the semiconductor device illustrated in FIG. 16B includes a circuit region 102 a in which an integrated circuit is formed over a semiconductor substrate 101, and different types of power generation elements 103 and power generation units in other regions of the semiconductor substrate 101. Element 104. The power generation element 103 and the power generation element 104 are connected to the integrated circuit in the circuit region 102a by wiring (not shown).

  In these configurations, for example, the power generation element 103 is a thermoelectric power generation element, and the power generation element 104 is a vibration power generation element. In addition, the semiconductor device illustrated in FIG. 16B includes a thin film battery 1601 a in another region of the semiconductor substrate 101. The thin film battery 1601a can be formed by providing a mask layer covering another element in a state where the other element is formed, and then depositing a predetermined film by a sputtering film forming method or the like.

  The semiconductor device shown in FIG. 16C includes a bump 1602 on a substrate 1630 on which an integrated circuit is formed, and a thermoelectric power generation element 1611 and a thin film battery 1610 are flip-chip connected to the substrate 1630 by the bump 1602. It has a laminated structure.

1 is a perspective view schematically showing a configuration example of a semiconductor device in an embodiment of the present invention. 2A and 2B are a cross-sectional view and a plan view schematically showing a more specific example of the semiconductor device shown in FIG. FIG. 3 is a circuit diagram for explaining an equivalent circuit configuration example of the semiconductor device shown in FIG. 2. FIG. 3 is a process diagram for describing an example of a method for manufacturing the semiconductor device shown in FIG. 2. It is a top view which shows the structure of the other semiconductor device in embodiment of this invention. FIG. 6 is a process diagram for describing the manufacturing method example of the semiconductor device shown in FIG. 5. FIG. 6 is a process diagram for describing the manufacturing method example of the semiconductor device shown in FIG. 5. It is a top view which shows the structure of the other semiconductor device in embodiment of this invention. FIG. 9 is a process diagram for describing the manufacturing method example of the semiconductor device shown in FIG. 8. FIG. 9 is a process diagram for describing the manufacturing method example of the semiconductor device shown in FIG. 8. It is a top view which shows the structure at the time of adding a protective layer to the semiconductor device shown in FIG. FIG. 12 is a process diagram for describing an example of a method for manufacturing the semiconductor device shown in FIG. 11. FIG. 12 is a process diagram for describing an example of a method for manufacturing the semiconductor device shown in FIG. 11. It is a top view which shows the structure of the other semiconductor device in embodiment of this invention. FIG. 15 is a process diagram for describing the manufacturing method example of the semiconductor device shown in FIG. 14. It is the perspective views (a) and (b) which show the structure of the other semiconductor device in embodiment of this invention, and typical sectional drawing (c). It is a perspective view which shows the structure of the conventional vibration electric power generation element. It is a perspective view which shows the structure of the conventional thermoelectric power generation element.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 ... Semiconductor substrate, 102 ... Circuit layer, 102a ... Circuit area | region, 103 ... Power generation element, 104 ... Power generation element, 105 ... Silicon base | substrate part, 106 ... Embedded oxide layer, 107 ... SOI layer, 112 ... Pad terminal, 113 ... Thermoelectric Pair 114, wiring pattern, 115 wiring pattern, 119 variable capacitance, 120 fixed capacitance, 121 through-hole, 122 movable electrode, 123 support pillar, 124 capacitive electrode, 126 wiring.

Claims (16)

An integrated circuit layer formed on a semiconductor substrate;
A thermoelectric power generation element for generating power by heat provided on the semiconductor substrate;
And a vibration power generation element that generates power by vibration provided on the semiconductor substrate. The semiconductor device according to claim 1,
A semiconductor device comprising a charge holding mechanism arranged on the semiconductor substrate for holding charges. The semiconductor device according to claim 2,
The semiconductor device according to claim 1, wherein the charge holding mechanism is configured by a chargeable / dischargeable thin film battery. The semiconductor device according to claim 2,
2. The semiconductor device according to claim 1, wherein the charge holding mechanism includes a capacitor in which an insulating film is sandwiched between two electrodes. The semiconductor device according to any one of claims 1 to 4,
The electric charge generated by the thermoelectric power generation element is used for the vibration power generation element. The semiconductor device according to any one of claims 1 to 5,
The semiconductor substrate includes an insulating layer and a silicon layer made of single crystal silicon formed thereon. A step of forming an integrated circuit in a partial region on a semiconductor substrate including a base portion, an insulating layer formed thereon, and a silicon layer made of single crystal silicon formed thereon;
A step of forming a first wiring pattern made of the silicon layer in a first power generation element region on the semiconductor substrate;
A second wiring pattern made of metal partially contacting the first wiring pattern is formed, and a movable electrode made of the metal and a capacitor electrode made of the metal are formed in a second power generation element region on the semiconductor substrate. A step of forming a state;
A support column that removes the insulating layer in a part of the region where the movable electrode is formed, forms a space between the movable electrode and the base portion, and supports the movable electrode on the base portion. And a step of forming a state where
In the first power generation element region of the semiconductor substrate, a thermoelectric power generation element composed of a plurality of thermocouples composed of the first wiring pattern and the second wiring pattern is formed,
A vibration power generation element composed of a variable capacitor composed of the movable electrode and a fixed electrode composed of the capacitor electrode is formed in the second power generation element region of the semiconductor substrate. Production method. A step of forming an integrated circuit in a partial region on a semiconductor substrate including a base portion, an insulating layer formed thereon, and a silicon layer made of single crystal silicon formed thereon;
A step of forming a first wiring pattern made of the silicon layer in a first power generation element region on the semiconductor substrate;
A state in which a movable electrode and a capacitor electrode made of the silicon layer are formed in a second power generation element region on the semiconductor substrate;
A step of forming a second wiring pattern made of a metal partly in contact with the first wiring pattern;
A support column that removes the insulating layer in a part of the region where the movable electrode is formed, forms a space between the movable electrode and the base portion, and supports the movable electrode on the base portion. And a step of forming a state where
In the first power generation element region of the semiconductor substrate, a thermoelectric power generation element composed of a plurality of thermocouples composed of the first wiring pattern and the second wiring pattern is formed,
A vibration power generation element composed of a variable capacitor composed of the movable electrode and a fixed electrode composed of the capacitor electrode is formed in the second power generation element region of the semiconductor substrate. Production method. A step of forming an integrated circuit in a partial region on a semiconductor substrate including a base portion, an insulating layer formed thereon, and a silicon layer made of single crystal silicon formed thereon;
The first wiring pattern made of the silicon layer is formed in the first power generating element region on the semiconductor substrate, and the second power generating element region on the semiconductor substrate is arranged to face the silicon power layer. A process of forming two walls, and
A second wiring pattern made of a metal partially contacting the first wiring pattern is formed, and a support pillar made of the metal disposed between the two walls and two supported by the support pillar And a step of forming a vibrator made of the metal disposed between the walls,
In the first power generation element region of the semiconductor substrate, a thermoelectric power generation element composed of a plurality of thermocouples composed of the first wiring pattern and the second wiring pattern is formed,
A vibration power generation element including two walls and the vibrator that vibrates in the direction of the wall is formed in the second power generation element region of the semiconductor substrate. Manufacturing method. Forming an LSI in a partial region of the SOI layer on the SOI substrate;
Forming a first resist pattern having a first opening on the SOI layer;
Forming a silicon pattern by anisotropically etching the SOI layer through the first opening to expose a buried oxide layer;
Removing the first resist pattern;
Forming a metal film on the SOI substrate;
Forming a second resist pattern having a second opening on the metal film;
The metal film is etched through the second opening to form a first metal film pattern, a second metal film pattern, and a third metal film pattern, and a thermocouple comprising the silicon pattern and the first metal film pattern Forming a capacitor comprising the third metal film pattern, the buried oxide layer, and a silicon base portion below the buried oxide layer;
Removing the second resist pattern;
Forming a third resist pattern having a third opening exposing a part of the second metal film pattern on the SOI substrate;
A portion of the buried oxide layer under the second metal film pattern is isotropically etched through the third opening from a movable portion made of the second metal film pattern and a portion of the buried oxide layer. Forming a support portion comprising:
And a step of removing the third resist pattern. Forming an LSI in a partial region of the SOI layer on the SOI substrate;
Forming a first resist pattern having a first opening on the SOI layer;
Forming an SOI pattern by anisotropically etching the SOI layer to a predetermined depth through the first opening;
Removing the first resist pattern;
Forming a second resist pattern having a second opening exposing the SOI pattern and a portion of the SOI layer;
The SOI layer is anisotropically etched through the second opening until the buried oxide layer is exposed to form a first SOI pattern, a second SOI pattern, and a third SOI pattern, and the third SOI pattern, the buried oxide layer, Forming a capacitor composed of the lower silicon substrate portion;
Removing the second resist pattern;
Forming a first metal film on the SOI substrate;
Forming a third resist pattern having a third opening exposing a portion of the first SOI pattern;
Forming a first metal pattern in the third opening by a plating method;
Removing the third resist pattern;
Etching the first metal film using the first metal pattern as a mask;
Forming an insulating film having a fourth opening exposing the top of the first SOI pattern and the first metal pattern and exposing the top and the periphery of the second SOI pattern;
Forming a second metal film;
Forming a fourth resist pattern having a fifth opening exposing an upper portion of the first SOI pattern and the first metal pattern;
Forming a second metal pattern by a plating method in the fifth opening;
Etching the second metal film using the second metal pattern as a mask to form a thermocouple including the first SOI pattern, the first metal pattern, and the second metal pattern;
A part of the buried oxide layer under the second SOI pattern is isotropically etched through the fourth opening to form a movable part made of the second SOI pattern and a support part made of a part of the buried oxide layer. A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 11.
A method of manufacturing a semiconductor device, comprising the step of removing the insulating film. Forming an LSI in a partial region of the SOI layer on the SOI substrate;
Forming a first resist pattern having a first opening on the SOI layer;
Forming an SOI pattern by anisotropically etching the SOI layer to a predetermined depth through the first opening;
Removing the first resist pattern;
Forming a second resist pattern having a second opening exposing the SOI pattern and a portion of the SOI layer;
Forming a first SOI pattern, a second SOI pattern, and a third SOI pattern by anisotropically etching the SOI layer through the second opening until the oxide layer is exposed;
Removing the second resist pattern;
Forming a first insulating film so that an upper portion of the third SOI pattern is exposed in a region around the second SOI pattern and the third SOI pattern;
Forming a first metal film on the SOI substrate;
Forming a third resist pattern having a third opening exposing a part of the first SOI pattern, the third SOI pattern, and an upper portion of the first insulating film;
Forming a first metal pattern and a second metal pattern in the third opening by a plating method;
Removing the third resist pattern;
Etching the first metal film using the first metal pattern and the second metal pattern as a mask;
Forming a second insulating film exposing an upper portion of the first SOI pattern, the second SOI pattern, the first metal pattern, and the second metal pattern;
Forming a second metal film on the SOI substrate;
Forming a fourth resist pattern having a fourth opening exposing an upper portion of the first SOI pattern, the first metal pattern, and the second metal pattern;
Forming a third metal pattern on the first SOI pattern and the first metal pattern in the fourth opening by plating, and forming a fourth metal pattern on the second metal pattern;
Etching the second metal pattern using the third metal pattern and the fourth metal pattern as a mask to form a thermocouple including the first SOI pattern, the first metal pattern, and the third metal pattern;
The first insulating film and the second insulating film are removed to form a movable part composed of the third SOI pattern, the second metal pattern, and the fourth metal pattern, and a capacitance composed of the movable part and the second SOI pattern. And a step of forming the semiconductor device. Forming an LSI in a partial region of the SOI layer on the SOI substrate;
Forming a first resist pattern having a first opening on the SOI layer;
Forming an SOI pattern by anisotropically etching the SOI layer to a predetermined depth through the first opening;
Removing the first resist pattern;
Forming a second resist pattern having a second opening exposing the SOI pattern and a portion of the SOI layer;
Forming a first SOI pattern, a second SOI pattern, and a third SOI pattern by anisotropically etching the SOI layer through the second opening until the oxide layer is exposed;
Removing the second resist pattern;
Forming a first insulating film so that an upper portion of the third SOI pattern is exposed in a region around the second SOI pattern and the third SOI pattern;
Forming a first metal film on the SOI substrate;
Forming a third resist pattern having a third opening exposing a part of the first SOI pattern, the third SOI pattern, and an upper portion of the first insulating film;
Forming a first metal pattern and a second metal pattern in the third opening by a plating method;
Removing the third resist pattern;
Etching the first metal film using the first metal pattern and the second metal pattern as a mask;
Forming a second insulating film exposing an upper portion of the first SOI pattern, the second SOI pattern, the first metal pattern, and the second metal pattern;
Forming a second metal film on the SOI substrate;
Forming a fourth resist pattern having a fourth opening exposing an upper portion of the first SOI pattern, the first metal pattern, and the second metal pattern;
Forming a third metal pattern on the first SOI pattern and the first metal pattern in the fourth opening by plating, and forming a fourth metal pattern on the second metal pattern;
Etching the second metal film using the third metal pattern and the fourth metal pattern as a mask to form a thermocouple including the first SOI pattern, the first metal pattern, and the third metal pattern;
Forming a third insulating film so as to cover the fourth metal pattern;
Forming a third metal film on the SOI substrate;
Forming a fifth resist pattern having a fifth opening on the third metal film;
Forming a fifth metal pattern by a plating method in the fifth opening;
Removing the fifth resist pattern;
Etching the third metal film using the fifth metal pattern as a mask to form a protective film made of the fifth metal pattern on the third insulating film;
Forming a movable part including the third SOI pattern, the second metal pattern, and the fourth metal pattern by isotropically etching the first insulating film, the second insulating film, and the third insulating film; A method of manufacturing a semiconductor device, comprising: a step of forming a movable part and a capacitor formed of the second SOI pattern. 15. The method of manufacturing a semiconductor device according to claim 14,
A method of manufacturing a semiconductor device, wherein a film is formed on the protective film by being attached by an STP method. Forming an LSI in a partial region of the SOI layer on the SOI substrate;
Forming a first resist pattern having a first opening on the SOI layer;
Forming an SOI pattern by anisotropically etching the SOI layer to a predetermined depth through the first opening;
Removing the first resist pattern;
Forming a second resist pattern having a second opening exposing the SOI pattern and a portion of the SOI layer;
The first SOI pattern, the second SOI pattern, the third SOI pattern, and the fourth SOI pattern are formed by anisotropic etching until the oxide layer is exposed through the second opening and the oxide layer is exposed, and the fourth SOI pattern and the fourth SOI pattern are formed. Forming a capacitor comprising a buried oxide layer and a silicon substrate portion under the buried oxide layer;
Removing the second resist pattern;
Forming a first insulating film covering only the third SOI pattern in a region around the second SOI pattern and the third SOI pattern;
Forming a first metal film on the SOI substrate;
Forming a third resist pattern having a third opening exposing a part of the first SOI pattern and an upper portion of the first insulating film;
Forming a first metal pattern and a second metal pattern by plating in the third opening;
Removing the third resist pattern;
Etching the first metal film using the first metal pattern and the second metal pattern as a mask;
Forming a second insulating film exposing an upper portion of the first SOI pattern, the second SOI pattern, the first metal pattern, and the second metal pattern;
Forming a second metal film on the SOI substrate;
Forming a fourth resist pattern having a fourth opening in which an upper portion of the first SOI pattern, the second SOI pattern, the first metal pattern, and the second metal pattern is exposed;
A third metal pattern is formed on the first opening and the first metal pattern in the fourth opening by plating, and a fourth metal pattern is formed on the second SOI pattern and the second metal pattern. Process,
Etching the second metal film using the third metal pattern and the fourth metal pattern as a mask to form a thermocouple including the first SOI pattern, the first metal pattern, and the third metal pattern;
The first insulating film and the second insulating film are removed to form a movable part composed of the second SOI pattern, the second metal pattern, and the fourth metal pattern, and the movable part and the third SOI pattern. And a step of forming a capacitor. A method of manufacturing a semiconductor device, comprising:

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