JP2003179082A - High electron mobility transistor - Google Patents
High electron mobility transistorInfo
- Publication number
- JP2003179082A JP2003179082A JP2002323750A JP2002323750A JP2003179082A JP 2003179082 A JP2003179082 A JP 2003179082A JP 2002323750 A JP2002323750 A JP 2002323750A JP 2002323750 A JP2002323750 A JP 2002323750A JP 2003179082 A JP2003179082 A JP 2003179082A
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- Prior art keywords
- layer
- gan
- electron
- electron mobility
- high electron
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Junction Field-Effect Transistors (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、電子移動度を高め
た高電子移動度トランジスタ(High Electron Mobility
Transistor:HEMT)に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high electron mobility transistor (High Electron Mobility) having enhanced electron mobility.
Transistor: HEMT).
【0002】[0002]
【従来の技術】高電子移動度トランジスタ(以下、HE
MTと称す)は、低雑音の高出力マイクロ波素子とし
て、衛星放送受信機などに用いられている。この素子を
作製するためのHEMT用エピタキシャルウェハとして
は、AlGaAs/GaAs系のものが主に用いられて
きた。ところで、最近になり、GaAsよりも高温動作
が可能で、耐放射線性に優れるGaN系のエピタキシャ
ルウェハが注目されている。このGaN系のHEMT
は、例えば図2に示すように、半絶縁性のサファイア基
板1上にAlNバッファ層2、電子走行層となるノンド
ープGaN層3、電子供給層となるn−AlGaN層4
を順次積層したものである。なお、5、6、7はそれぞ
れ、ソース電極、ゲート電極およびドレイン電極であ
る。上記構造のHEMTにおいて、電子供給層となるn
−AlGaN層4は電子走行層となるノンドープGaN
層3に電子を供給し、供給された電子はGaN層3の最
上層部3a(n−AlGaN層4に接する領域)を高移
動度で走行する。従って、GaN層3は高い電子移動度
を保つために、高純度で、結晶欠陥が少ないことが要求
される。このHEMTは以下のようにして作製する。即
ち、先ず有機金属気相成長法を用いて、サファイア基板
1上にAlNバッファ層2、ノンドープGaN層3、n
−AlGaN層4を順次積層する。次いで、プラズマC
VD装置を用いてSiO 2 膜を堆積させ、フォトレジス
トおよび化学エッチングによりパターニングする。その
後、AuGe/Niなどの金属を蒸着してソース電極
5、ゲート電極6およびドレイン電極7を形成する。2. Description of the Related Art High electron mobility transistors (hereinafter referred to as HE
MT) is a low-noise high-power microwave device.
It is used in satellite broadcasting receivers. This element
As an HEMT epitaxial wafer for fabrication
AlGaAs / GaAs type is mainly used for
Came. By the way, recently, it operates at higher temperature than GaAs.
GaN-based epitaxy that is capable of
Luwafer is drawing attention. This GaN HEMT
Is a semi-insulating sapphire group, for example, as shown in FIG.
An AlN buffer layer 2 on the plate 1 and a non-electrode which becomes an electron transit layer.
GaN layer 3, n-AlGaN layer 4 serving as an electron supply layer
Are sequentially laminated. In addition, 5, 6 and 7 are each
The source electrode, the gate electrode and the drain electrode.
It In the HEMT having the above structure, n serving as an electron supply layer
-AlGaN layer 4 is non-doped GaN that serves as an electron transit layer
The electrons are supplied to the layer 3, and the supplied electrons are the maximum of the GaN layer 3.
The upper layer portion 3a (a region in contact with the n-AlGaN layer 4) is highly transferred.
Drive with mobility. Therefore, the GaN layer 3 has a high electron mobility.
High purity and few crystal defects are required to maintain
To be done. This HEMT is manufactured as follows. Immediately
Then, first, using a metalorganic vapor phase epitaxy method, a sapphire substrate
AlN buffer layer 2, non-doped GaN layer 3, n
-The AlGaN layer 4 is sequentially laminated. Then plasma C
SiO using VD equipment 2 Film deposition, photoresist
And patterning by chemical etching. That
After that, a metal such as AuGe / Ni is vapor-deposited to form a source electrode.
5, the gate electrode 6 and the drain electrode 7 are formed.
【0003】[0003]
【発明が解決しようとする課題】しかしながら、GaN
層を気相成長させると、成長結晶中に窒素Nが入りにく
く、Nの欠如による格子欠陥が生ずる。従って、上述の
HEMTには、電子走行層となるGaN層に、おもにN
の空孔に基づく格子欠陥が存在するという問題があっ
た。[Problems to be Solved by the Invention] However, GaN
When the layer is vapor-deposited, it is difficult for nitrogen N to enter the grown crystal, and a lattice defect due to the lack of N occurs. Therefore, in the HEMT described above, the GaN layer serving as the electron transit layer is mainly composed of N.
However, there is a problem that there are lattice defects due to the vacancy.
【0004】[0004]
【課題を解決するための手段】本発明は上記問題点を解
決すべくなされたもので、電子走行層がGaN系化合物
半導体層からなり、電子供給層が前記電子走行層よりバ
ンドギャップエネルギーの大きいGaN系化合物半導体
層からなる高電子移動度トランジスタであって、前記電
子走行層はIn、AsまたはPを1×1019cm-3以
上、5×1020cm -3以下含むことを特徴する高電子移
動度トランジスタである。The present invention solves the above problems.
The electron transit layer is a GaN-based compound.
It consists of a semiconductor layer, and the electron supply layer is
GaN-based compound semiconductor with large band gap energy
A high electron mobility transistor comprising layers,
In the running layer, In, As or P is 1 × 1019cm-3Since
Top 5 × 1020cm -3High electron transfer characterized by including
It is a mobility transistor.
【0005】本発明は、新しい実験的知見に基づくもの
である。即ち、本発明者はGaNにInを添加すると、
Inの濃度が1×1019cm-3以上、5×1020cm-3
以下の範囲において、フォトルミネッセンス(PL)強
度で結晶性を比較したところ、GaN中の窒素に基づく
欠陥と思われるPL強度が著しく小さくなることを見出
した。GaNのバンド端のPL強度IB (波長:約36
5nm)と、窒素の欠陥のPL強度IV (波長:約57
5nm)を測定すると、Inを含まない場合では、IV
/IB=0.1〜0.2程度であるのに対し、上記範囲
のInを含むGaNでは、測定限界を越えて、IV /I
B ≒0であった。このことから、GaNに上記範囲のI
nを添加することにより、GaNの窒素に基づく欠陥は
減少することがわかる。従って、このようなGaNで電
子走行層を構成すると、電子走行層は高い電子移動度を
示すことが期待できる。なお、GaNにInを添加する
代わりに、As或いはPを1019cm-3以上、5×10
20cm-3以下の範囲で添加しても同様の結果を得ること
ができる。また、電子走行層にAlGaNなどの他のG
aN系化合物半導体を用いても、In、As或いはPを
上記範囲で添加し、GaNと同様の結果を得ることがで
きる。The present invention is based on new experimental findings. That is, when the present inventors add In to GaN,
In concentration is 1 × 10 19 cm −3 or more, 5 × 10 20 cm −3
When the crystallinity was compared by the photoluminescence (PL) intensity in the following range, it was found that the PL intensity, which is considered to be a defect due to nitrogen in GaN, was significantly reduced. PL intensity I B at the band edge of GaN (wavelength: about 36
5 nm) and PL intensity of nitrogen defects I V (wavelength: about 57
5 nm), I V
/ I B = 0.1 to 0.2, while GaN containing In in the above range exceeds I V / I beyond the measurement limit.
B ≈ 0. From this fact, GaN has an I content within the above range.
It can be seen that the nitrogen-based defects in GaN are reduced by adding n. Therefore, when the electron transit layer is made of such GaN, it can be expected that the electron transit layer exhibits high electron mobility. Instead of adding In to GaN, As or P was 10 19 cm −3 or more, 5 × 10 5 or more.
Similar results can be obtained even when added in the range of 20 cm -3 or less. In addition, other G such as AlGaN is formed in the electron transit layer.
Even if an aN-based compound semiconductor is used, In, As or P can be added within the above range to obtain the same result as GaN.
【0006】[0006]
【発明の実施の形態】以下、図面に基づいて本発明の実
施の形態を詳細に説明する。図1は、本発明にかかるH
EMTの一実施形態の断面図である。図中、11は半絶
縁性シリコン基板、12はGaNバッファ層、13は電
子走行層となるInドープGaN層、14は電子供給層
となるn−AlGaN層、15、16、17はそれぞ
れ、ソース、ゲート、ドレインの各電極である。このH
EMTは、以下のような工程で作製した。即ち、1)成
長室とパターニング室を有する超高真空装置を用いて、
分子線エピタキシャル成長法で以下のようなエピタキシ
ャルウェハを作製した。半絶縁性シリコン基板11上
に、ジメチルヒドラジン(5×10-5Torr)とGa
(5×10-7Torr)を用いて、成長温度640℃で
50Åの厚さのGaNバッファ層12を積層する。次い
で、GaNバッファ層12の上に、アンモニア(5×1
0-5Torr)、Ga(5×10-7Torr)、および
In(約10-9Torr)を用いて、成長温度780℃
で500Åの厚さのInドープGaN層13を積層す
る。次いで、InドープGaN層13上に、アンモニア
(5×10-5Torr)、Ga(5×10-7Tor
r)、Al(1×10-7Torr)およびSi(5×1
0-9Torr)を用いて、成長温度850℃で250Å
の厚さのn−AlGaN層14を積層する。2)次い
で、プラズマCVD装置を用いて、上記エピタキシャル
ウェハ上にSiO2を堆積させた後、フォトリソグラフ
ィと化学エッチングを用いてゲート部をマスクし、ソー
ス、ドレインとなる部分に開口部を開ける。その開口部
にAlを蒸着し、ソース電極15、ドレイン電極17を
形成する。次いで、前記マスクを除去し、逆に、ソース
電極15、ドレイン電極17の上を覆い、ゲートとなる
部分に開口部を設けたSiO2マスクを形成し、Auを
蒸着してゲート電極16を形成する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows the H according to the present invention.
FIG. 3 is a cross-sectional view of one embodiment of EMT. In the figure, 11 is a semi-insulating silicon substrate, 12 is a GaN buffer layer, 13 is an In-doped GaN layer that serves as an electron transit layer, 14 is an n-AlGaN layer that serves as an electron supply layer, and 15, 16 and 17 are sources, respectively. , Gate and drain electrodes. This H
The EMT was manufactured by the following steps. That is, 1) using an ultra-high vacuum device having a growth chamber and a patterning chamber,
The following epitaxial wafer was produced by the molecular beam epitaxial growth method. On the semi-insulating silicon substrate 11, dimethylhydrazine (5 × 10 −5 Torr) and Ga
Using (5 × 10 −7 Torr), a GaN buffer layer 12 having a thickness of 50 Å is stacked at a growth temperature of 640 ° C. Then, on the GaN buffer layer 12, ammonia (5 × 1
0 -5 Torr), Ga (5 x 10 -7 Torr), and In (about 10 -9 Torr) at a growth temperature of 780 ° C.
Then, an In-doped GaN layer 13 having a thickness of 500 Å is laminated. Then, on the In-doped GaN layer 13, ammonia (5 × 10 −5 Torr) and Ga (5 × 10 −7 Tor) are formed.
r), Al (1 × 10 −7 Torr) and Si (5 × 1)
0 -9 Torr) at a growth temperature of 850 ° C and 250 Å
The n-AlGaN layer 14 having a thickness of 1 is stacked. 2) Next, using a plasma CVD apparatus, after depositing SiO 2 on the epitaxial wafer, the gate portion is masked by using photolithography and chemical etching, and openings are formed in the portions to be the source and drain. Al is vapor-deposited in the opening to form the source electrode 15 and the drain electrode 17. Then, the mask is removed, and conversely, a SiO 2 mask is formed which covers the source electrode 15 and the drain electrode 17 and has an opening at a portion to be a gate, and Au is vapor-deposited to form the gate electrode 16. To do.
【0007】上述のHEMTにおいて、InドープGa
N層13のIn添加量を変化させて、電子走行層となる
InドープGaN層13の電子移動度を温度77Kで測
定した。その結果を表1に示す。表1からわかるよう
に、Inの添加量が1×1019cm-3以上、5×1020
cm-3以下の範囲で、電子移動度は5500以上であ
り、Inを添加しない場合の2倍以上となって、高い電
子移動度を示した。In the HEMT described above, In-doped Ga
The electron mobility of the In-doped GaN layer 13 serving as the electron transit layer was measured at a temperature of 77K by changing the amount of In added to the N layer 13. The results are shown in Table 1. As can be seen from Table 1, the amount of In added is 1 × 10 19 cm −3 or more, 5 × 10 20
In the range of cm −3 or less, the electron mobility was 5500 or more, which was more than twice that in the case where In was not added, and high electron mobility was exhibited.
【0008】[0008]
【表1】
注)In添加量:cm-3 電子移動度(77K):cm2/
V-1・S-1 [Table 1] Note) In addition amount: cm -3 Electron mobility (77K): cm 2 /
V -1 / S -1
【0009】なお、本発明は上記実施形態に限定され
ず、電子走行層となるGaN層にはInのかわりにAs
あるいはPを1019cm-3以上、5×1020cm-3以下
添加してもよい。この添加の際には、As源として固体
のAs、アルシン、有機系のAsを用いることができ、
また、P源としては、固体のP、フォスフィン、有機系
のPを用いることができる。また、電子供給層はAlG
aN層のかわりに、GaN層を用いてもよい。但し、こ
の場合にはGaNよりもバンドギャップの小さい材料、
例えばIn1-X GaX N(0.1≦X≦0.3)層を電
子走行層であるInドープGaN層との間に介在させ、
電子供給層と電子走行層の間に電子が閉じ込められるよ
うにすることが望ましい。さらに、上記実施形態はHE
MTの電子走行層に高電子移動度のInドープGaN層
を用いているが、他の電子素子、例えばFETの電子走
行層に高電子移動度のInドープGaN層を用いてもよ
い。The present invention is not limited to the above-described embodiment, and the GaN layer serving as the electron transit layer is replaced by As instead of In.
Alternatively, P may be added at 10 19 cm −3 or more and 5 × 10 20 cm −3 or less. At the time of this addition, solid As, arsine, organic As can be used as an As source,
As the P source, solid P, phosphine, or organic P can be used. The electron supply layer is AlG
A GaN layer may be used instead of the aN layer. However, in this case, a material having a smaller band gap than GaN,
For example, an In 1-X Ga X N (0.1 ≦ X ≦ 0.3) layer is interposed between the In 1 -X Ga X N (0.1 ≦ X ≦ 0.3) layer and an In-doped GaN layer that is an electron transit layer,
It is desirable that electrons are confined between the electron supply layer and the electron transit layer. Further, the above-described embodiment is HE
Although the high electron mobility In-doped GaN layer is used as the electron transit layer of the MT, the high electron mobility In-doped GaN layer may be used as the electron transit layer of another electronic device such as an FET.
【0010】[0010]
【発明の効果】本発明によれば、電子走行層の電子移動
度が高いGaN系の高電子移動度トランジスタが得られ
るという優れた効果がある。According to the present invention, there is an excellent effect that a GaN-based high electron mobility transistor having a high electron mobility in the electron transit layer can be obtained.
【0011】[0011]
【図1】本発明に係るHEMTの一実施形態の断面図で
ある。FIG. 1 is a cross-sectional view of one embodiment of a HEMT according to the present invention.
【図2】HEMTの断面図である。FIG. 2 is a cross-sectional view of a HEMT.
11 半絶縁性シリコン基板 12 GaNバッファ層 13 InドープGaN層 14 n−AlGaN層 15、16、17 電極 11 Semi-insulating silicon substrate 12 GaN buffer layer 13 In-doped GaN layer 14 n-AlGaN layer 15, 16, 17 electrodes
Claims (2)
なり、電子供給層が前記電子走行層よりバンドギャップ
エネルギーの大きいGaN系化合物半導体層からなる高
電子移動度トランジスタであって、前記電子走行層はI
nを1×1019cm-3以上、5×1020cm-3以下含む
ことを特徴する高電子移動度トランジスタ。1. A high electron mobility transistor in which an electron transit layer comprises a GaN-based compound semiconductor layer and an electron supply layer comprises a GaN-based compound semiconductor layer having a bandgap energy larger than that of the electron transit layer. Layer is I
A high electron mobility transistor comprising n of 1 × 10 19 cm −3 or more and 5 × 10 20 cm −3 or less.
なり、電子供給層が前記電子走行層よりバンドギャップ
エネルギーの大きいGaN系化合物半導体層からなる高
電子移動度トランジスタであって、前記電子走行層はA
sまたはPを1×1019cm-3以上、5×1020cm-3
以下含むことを特徴する高電子移動度トランジスタ。2. A high electron mobility transistor comprising an electron transit layer made of a GaN compound semiconductor layer and an electron supply layer comprising a GaN compound semiconductor layer having a bandgap energy larger than that of the electron transit layer. Layer is A
s or P is 1 × 10 19 cm -3 or more, 5 × 10 20 cm -3
A high electron mobility transistor comprising:
Priority Applications (1)
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JP2002323750A JP2003179082A (en) | 2002-11-07 | 2002-11-07 | High electron mobility transistor |
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JP2002323750A JP2003179082A (en) | 2002-11-07 | 2002-11-07 | High electron mobility transistor |
Related Parent Applications (1)
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JP34340596A Division JPH10189944A (en) | 1996-12-24 | 1996-12-24 | High electron-mobility transistor |
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ID=19197631
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012049465A (en) * | 2010-08-30 | 2012-03-08 | Advanced Power Device Research Association | Nitride-based compound semiconductor, nitride-based compound semiconductor element, and method of manufacturing the nitride-based compound semiconductor element |
US8525225B2 (en) | 2005-09-02 | 2013-09-03 | The Furukawa Electric Co., Ltd. | Semiconductor device |
US20160211358A1 (en) * | 2015-01-21 | 2016-07-21 | Kabushiki Kaisha Toshiba | Semiconductor device |
-
2002
- 2002-11-07 JP JP2002323750A patent/JP2003179082A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8525225B2 (en) | 2005-09-02 | 2013-09-03 | The Furukawa Electric Co., Ltd. | Semiconductor device |
JP2012049465A (en) * | 2010-08-30 | 2012-03-08 | Advanced Power Device Research Association | Nitride-based compound semiconductor, nitride-based compound semiconductor element, and method of manufacturing the nitride-based compound semiconductor element |
US20160211358A1 (en) * | 2015-01-21 | 2016-07-21 | Kabushiki Kaisha Toshiba | Semiconductor device |
CN106206709A (en) * | 2015-01-21 | 2016-12-07 | 株式会社东芝 | Semiconductor device |
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