JP2006024927A - Semiconductor device and method for manufacturing the semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stable a surface of a GaN field-effect device, so that the electron density in the channel is increased, and a high-performance device is obtained, as well as a reliable processing, before the surface is contaminated due to exposure to air, and all kinds of damages in a different processing step. <P>SOLUTION: There is provided a new method for manufacturing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET devices or MESFET devices, grown by MOCVD (Metal-Organic Vapor Phase Expitaxy method), having higher performance (power), by covering the surface with a thin SiN layer on the top AlGaN layer, in a reactor where the growth takes place at a high temperature, prior cooling down the structure and loading the sample out of the reactor, as well as a method to produce some HEMT transistors on these heterostructures, by depositing the contact on the surface, without removal of the SiN layer by MOCVD. The semiconductor device is manufactured using this method. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to III-nitride field effect devices and methods for improving surface stability by passivation of the top surface as well as ohmic contact deposition on wide band gap layers.

  A GaN field effect element is a piezoelectric element, that is, one that is charged and separated inside a material by spontaneous polarization and piezoelectric polarization.

  This has the great advantage that it allows the creation of a surface charged layer in the structure at the interface between different material compositions such as, for example, AlGaN and GaN. These surface charged layers are compensated in the AlGaN / GaN junction by forming a two-dimensional electron gas (2DEG) having a high mobility value compared to the bulk material on the opposite side of the interface. If necessary and beneficial to create very high mobility channels in the structure, it will allow demonstration of powerful HEMT elements, but this has the disadvantage of separate charging inside the wurtzite material. It also causes a surface charge layer on the top surface of the structure and increases the importance of surface energy levels compared to zinc blende type structural materials. Since surface energy levels play an important role during device operation, the presence of surface energy levels presents a significant problem in achieving the theoretically predicted high performance for these devices. . Although thermal motion is also a partial cause of the DC current drop, the dc performance drop, the current drop at high drain-source voltage, and the DC-to-RF dispersion phenomenon contribute to surface energy level filling and emptying. Many authors point out that it is directly related.

In order to minimize the effect of these surface energy levels on the top III-N structure, in principle, an ex-situ method is used during transistor processing, for example by SiN, SiO ₂ . Several authors have proposed to passivate the surface between the drain and source. These methods strongly depend on the growth condition of the oxide layer or insulating layer on the top surface as well as the strain state of the heterostructure itself as a strain effect adjusted by the growth conditions, and the two-dimensional electron gas characteristics. Also affects. They are also strongly dependent on the chemical or mechanical state of the surface, depending on the pretreatment steps made on this top surface.

  Patent Document 1 describes an AlGaN / GaN HEMT having a thin AlGaN layer. The source and drain contacts are in contact with the AlGaN layer, but a portion of the AlGaN layer is not covered by the contact. This uncovered portion of the AlGaN layer is covered with an insulating layer and further includes a gate contact on the insulating layer. In one embodiment, the HEMT and insulating layer are made using metal organic chemical vapor deposition. In another embodiment, the insulating layer is sputtered onto the top surface of the HEMT active layer.

  U.S. Patent No. 6,057,036 describes a GaN-based FET using a dielectric passivation layer on the exposed AlGaN or GaN surface of the device above the channel region between the source and drain contacts. This dielectric layer is made of SiN. This layer controls unwanted frequency dependent currents and reduced breakdown voltage.

  Patent Document 3 describes a high electron mobility transistor. This transistor consists of a GaN / AlGaN heterojunction that generates a two-dimensional electron gas. This structure is deposited on the base planar sapphire using low pressure metalorganic chemical vapor deposition.

  Another problem in the development of field effect GaN based transistors is the ohmic contact formation on the III-nitride surface. Ohmic contact formation depends on different factors such as, for example, surface composition, but what is very important is the degree of oxidation of the top surface that has long been underestimated. In order to overcome this problem, different cleaning and metallization techniques have been proposed. If a good ohmic contact is not formed on the top layer, the performance of the device will be severely degraded immediately. In many cases, it has been observed that the maximum current measured under dc conditions is well below the maximum current density value deduced from material considerations, such as carrier density and mobility in the channel. .

  Furthermore, in many cases, the uniformity and reproducibility of device performance of a wafer and from one wafer to another is a problem. Even if record performance is demonstrated with the selected HEMT device, the uniformity and reproducibility of the results remains a difficult problem to solve. It is believed that better results in uniformity and repeatability should be obtained by improving material quality and device processing, but the fundamental problem to overcome is precise control of surface properties .

Finally, the following are other problems frequently encountered by piezoelectric elements such as AlGaN / GaN HEMT elements. There are two possibilities for increasing the current density in the two-dimensional electron gas: either increasing the thickness of the AlGaN layer or increasing the Al content in this top surface. . These two possibilities lead to an increase in carrier density in the channel by increasing the strain in the top AlGaN pseudomorphically grown on the GaN layer. However, if high strain is present in the AlGaN layer, cracks are rapidly induced on this upper surface. These cracks in AlGaN are very detrimental and these cracks destroy the 2DEG at the AlGaN / GaN interface; second, these cracks complicate processing. Therefore, it is important to note the possibility of preventing the occurrence of cracks in the top AlGaN, even with very high strain layers. It should be noted that most of these cracks are believed to occur during cooling of the structure. Also, when growing a III-N device on a Si substrate, the difference in thermal expansion coefficient is larger than that in a SiC or sapphire substrate, so that an effective method for reducing the occurrence of cracks in the III-N device is stronger. It is desired.
US Patent Application Publication No. 2003 / 0020092A1 International Patent Application Publication No. 01/13436 A1 US Pat. No. 5,192,987

  The object of the present invention is to increase the electron density in the channel and obtain high performance devices, as well as reliable processing, before surface contamination due to air exposure and any damage in different processing steps. It is to stabilize the surface of the field effect element.

  A further object is to reduce ohmic contact resistance.

  A further object of the present invention is to reduce the strain-induced changes during cooling and to enable the two-dimensional electron gas by allowing higher strain in the heterostructure without compromising the top surface mechanical properties. To increase and thereby directly improve HEMT performance.

In the first aspect of the invention, a device or device is described. The device includes:
substrate,
A first active layer,
A second active layer on the first active layer, the second active layer has a higher band gap than the first active layer;
A two-dimensional electron gas layer between the first active layer and the second active layer;
A passivation layer on the second active layer;
The source and drain contacts, the source contact and the drain contact are in contact with the passivation layer.

  In the device of the present invention, the passivating layer can be arranged in such a manner that the electron density of the two-dimensional electron gas layer increases.

  In the device of the present invention, the gate contact is preferably in electrical contact with the second active layer.

  In the device of the present invention, the first active layer is preferably made of a group III nitride semiconductor material, more preferably GaN.

  In the device of the present invention, the second active layer is preferably made of a group III nitride semiconductor material, and more preferably made of AlGaN or AlGaInN.

  In the element of the present invention, a spacer layer can be disposed between the first active layer and the second active layer.

  In the device of the present invention, a third layer can be positioned between the second active layer and the passivation layer, and preferably the third layer is formed of a group III nitride material.

  Furthermore, in the device of the present invention, the passivation layer can be arranged in a manner that reduces or eliminates the effect of surface energy levels on the carrier density in the two-dimensional electron gas during device operation. .

  In the device of the present invention, the passivation layer is preferably formed of a material containing at least an electron donor element and nitrogen, and more preferably, silicon nitride.

  In the device of the present invention, the passivating layer may be a multilayer structure comprising a group III nitride material and a material selected from the group consisting of SiN or AlN.

  In the device of the present invention, the thickness of the passivation layer is preferably between 1 nm and 30 nm.

  In the device of the present invention, the substrate is preferably formed of a material selected from the group consisting of silicon, sapphire, SiC, GaN, and AlN.

  In an embodiment of the invention, the source contact and drain contact are deposited on the passivation layer.

  In an embodiment of the present invention, the device described in the preceding embodiment is disclosed further including a gate contact in electrical contact with the second active layer.

  In other embodiments, a portion of the passivation layer is not covered by the source and drain contacts. The gate contact can contact the passivation layer, or the gate contact can be deposited on the second active layer.

  In another embodiment, as described in any of the previous embodiments, a device is disclosed in which the first active layer is formed of a group III nitride semiconductor material.

  In a preferred embodiment, the first active layer is made of GaN.

  In another embodiment, the second active layer is formed of a group III nitride material.

  In a preferred embodiment, the second active layer is made of AlGaN or AlGaInN.

  Between the first active layer and the second active layer (also called an interface), a surface charged layer can be formed in the device. This surface charged layer is compensated by forming a two-dimensional electron gas on the opposite side of the interface, which will result in a higher mobility value compared to the bulk material. This is useful for creating very high mobility channels in the device.

  In another embodiment, there is a spacer layer between the first active layer and the second active layer. The spacer layer is selected in such a way as to increase the interface mobility.

  The spacer layer can be formed of AlM, but is not limited thereto.

  In other embodiments, the second active layer is partially or wholly doped with a donor element such as Si to provide another electron source.

  In another embodiment, the second active layer is covered with a third layer, and the third layer is formed of a III-nitride material such as (but not limited to) GaN. The third layer exists between the second active layer and the passivation layer.

  In other embodiments, the device further includes at least one buffer layer between the substrate and the first active layer. This buffer layer provides a suitable crystal structure transition between the substrate and the remainder of the device. The buffer layer may be a nucleation layer between the substrate and the first active layer. In particular embodiments, the buffer layer is composed of, but is not limited to, AlN, GaN, or AlGaN.

  In one embodiment of the present invention, the passivation layer is arranged in a manner that reduces or eliminates the effect of surface energy levels on the carrier density in the two-dimensional electron gas during device operation.

  In one embodiment of the invention, as described in any of the preceding embodiments, a device is disclosed that includes at least a donor material and nitrogen in the passivation layer.

  In a particular embodiment, the passivating layer is made of silicon nitride.

  In other embodiments, the passivation layer is formed of magnesium nitride.

  In a further embodiment, the passivation layer is a multi-layer structure comprising a III-nitride material and SiN or AlN.

  The passivation layer is arranged in such a way as to reduce the effect of surface energy levels on the carrier density in the two-dimensional electron gas during device operation.

  Although the present invention is not limited to this, a possible explanation for such an effect would be that the SiN layer can provide a charged neutral interface with AlGaN that eliminates 2DEG surface depletion. The presence of high levels of Si, or at least donor type defects in the passivation layer, is beneficial in compensating for surface charging effects. Since the surface energy level plays an important role during the operation of the device, the presence of the surface energy level causes a precise problem for realizing high performance.

  The thickness of the passivation layer is between 1 nm and 100 nm, between 1 nm and 50 nm, between 1 nm and 30 nm, or between 1 nm and 20 nm. Preferably, this thickness is between 1 nm and 30 nm.

  The passivation layer is characterized by an amorphous structure.

  In addition, a thin passivation layer allows the formation of a low resistance ohmic contact.

  Furthermore, the passivation layer contains Si, which can diffuse into AlGaN functioning as a donor.

  By introducing a donor type into the AlGaN layer, it is easy to form an ohmic contact, and as a result, the contact resistance is reduced.

  The first active layer, the second active layer, and the passivating layer are formed in the same reactor without exposing each layer to air.

  The passivation layer is preferably formed by MOVPE (metal organic vapor phase epitaxy) or MBE (molecular beam epitaxy).

  The passivating layer is formed at temperatures between 700 ° C and 1300 ° C, between 700 ° C and 1250 ° C, and between 700 ° C and 1100 ° C.

  In a further embodiment, the second active layer is not covered with an oxide layer. The passivation layer is in direct contact with the second active layer.

  In a further embodiment, an element is disclosed in which the substrate is formed of a material selected from the group consisting of silicon, sapphire, SiC, GaN, and AlN, as described in any of the previous embodiments. ing.

  In other embodiments of the present invention, the device is a field effect transistor, as described in any of the previous embodiments. The field effect transistors are HEMT (High Electron Mobility Transistor), MOSHFET (Metal Oxide Semiconductor Heterostructure Field Effect Transistor), MESFET (Metal Semiconductor Field Effect Transistor), MISFET (Metal Insulator Semiconductor Field Effect Transistor), or MISHFET ( Metal insulator semiconductor heterostructure field effect transistor), but is not limited thereto.

  In a further embodiment, as described in any of the previous embodiments, an element characterized by a higher current density and higher power performance is disclosed compared to prior art elements.

  In other preferred embodiments, the source and drain contacts are formed of an alloy comprising Ti, Al, Ni, Mo, Ta, Pt, Pd, V, Nb, Zr, and / or Au. The contacts are preferably formed of Ti / Al / Ti / Au sequence, Ti / Al / Ni / Au, Ti / Al / Mo / Au, or Ti / Al / Pt / Au.

  When one of the layers is made of Al, the latter can easily form an alloy with nitrogen, AlN, and silicon can function as a dopant in the AlGaN layer. This facilitates ohmic contact formation.

In a second aspect of the present invention, a method for forming a device is described, the method comprising the following steps:
Disposing a substrate in a reaction chamber; forming a first active layer on the substrate; forming a second active layer on the first active layer; wherein the second active layer is formed from the first active layer; Having a high band gap, thereby forming a two-dimensional electron gas layer between the first active layer and the second active layer;
Forming a passivation layer on the second active layer, forming a source contact and a drain contact, wherein the source contact and the drain contact are in contact with the passivation layer; and A portion is not covered by the source and drain contacts.

  The method according to the present invention further comprises forming a gate contact in electrical contact with the second active layer.

  In the method of the present invention, the steps of forming the first active layer, forming the second active layer, and forming the passivation layer are performed in a reaction chamber without exposing the device to air (environment). Is done.

  Furthermore, the reaction chamber may be a MOVPE (metal organic chemical vapor deposition) reaction chamber.

The method of the present invention may further comprise the following steps:
Cooling the reaction chamber;
Removing the device with the deposited layer from the reaction chamber;
The cooling and removal steps are performed after the passivating layer formation step and before the source and drain contact formation steps.

  In the method of the present invention, the passivating layer formation step is preferably carried out at a temperature between 700 ° C and 1300 ° C.

  In the method of the present invention, the steps of forming the source and drain contacts are performed in such a way that there is a direct contact between the passivation layer and the source and drain contacts.

  In the method of the present invention, the first active layer is preferably formed of a group III nitride semiconductor material, and more preferably is formed of GaN.

  In the method of the present invention, the second active layer is preferably formed of a group III nitride semiconductor material, and more preferably is formed of AlGaN or AlGaInN.

  In the method of the present invention, the passivating layer preferably contains an electron donor element and nitrogen, more specifically said passivating layer is made of SiN.

  In an embodiment of the second aspect of the present invention, a method is disclosed that further comprises the step of forming a gate contact in electrical contact with the second active layer, as described in any of the previous embodiments. . The gate contact is formed in an uncovered portion of the passivation layer.

  In an embodiment of the second aspect of the present invention, the steps of forming the first active layer, forming the second active layer, and forming the passivating layer are also referred to as “in-situ” formation for purposes of the present invention. As is done in the reaction chamber without exposing the element to air.

  In a preferred embodiment, the reaction chamber is a MOVPE reaction chamber.

  Oxide formation on the second active layer is substantially avoided. Furthermore, the oxide layer removal step from the upper surface of the second active layer is avoided. This will result in improved ohmic contact formation.

  The prior art has shown that the oxide that forms spontaneously on the top surface of the second active layer is very stable, so that prior to the effective removal of the oxide layer, the high power of plasma etching and / or Long duration is needed.

  In other embodiments of the second aspect of the present invention, the method may further include forming at least one buffer layer between the substrate and the first active layer.

  This step is performed after the substrate placement step in the reaction chamber.

  The buffer layer provides a suitable crystal structure transition between the substrate and the remainder of the device.

  The buffer layer may be a nucleation layer between the substrate and the first active layer.

  In particular embodiments, the buffer layer can be formed of, but not limited to, AlN, GaN, AlGaN, or InN, or a combination thereof.

  In a particular embodiment, the buffer layer is formed at a growth temperature that is lower than the growth temperature of the first active layer.

In another embodiment of the second aspect of the invention, the method further comprises the following steps:
Cooling the reaction chamber;
Removing the element with the deposited layer from the reaction chamber;
The step is performed after the passivating layer forming step and before the source and drain contact forming step.

  In other examples, the passivating layer forming step is performed at a temperature between 700 ° C and 1300 ° C, between 700 ° C and 1250 ° C, or between 700 ° C and 1100 ° C.

  A passivation layer (preferably AlGaN) deposited on the second active layer at least at 700 ° C. results in a reduction of cracks in the second active layer. Cracks occur when the device is cooled from the growth temperature to room temperature. Thus, this increases the thickness of the second active layer and / or the Al content in the second active layer. This results in an increase in carrier density within the channel.

  The step of forming source and drain contacts is performed such that the passivation layer and the source and drain contacts are in direct contact. This means that the passivation layer is not etched before the source and drain contacts are formed.

When referring to SiN, it should be understood to mean a compound consisting of Si and N. SiN can include other formulations of different normal composition ratios or non-normal composition ratios, such as but not limited to Si _x N _y, as well as Si ₃ N ₄ .

In the Si _x N _y formulation, x and y can be defined as real numbers where 0 <x ≦ 100 and 0 <y ≦ 100.

  In an embodiment of the second aspect of the present invention, the step of forming the first active layer includes flowing a source gas adapted to form the first active layer into the reaction chamber. The step of forming the second active layer includes flowing a source gas adapted to form the second active layer into the reaction chamber. The passivating layer forming step includes flowing a source gas adapted to form the passivating layer into the reaction chamber.

  In a further embodiment, the first active layer is formed of a group III nitride semiconductor material. In a preferred embodiment, the first active layer is made of GaN. In another further embodiment, the second active layer is formed of a group III nitride material. In the preferred embodiment, the second active layer is formed of AlGaN.

  In another further embodiment, the passivation layer is formed of silicon nitride.

  The specifications of the different layers formed by the method are similar to those described in the first aspect of the invention.

  While the invention has been described with reference to specific embodiments and with reference to certain drawings, the invention is not limited thereto but only by the claims. The drawings described are only schematic and are not intended to be limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes.

  The present invention describes elements and methods that overcome problems related to surface stability and homogeneity as well as better control of ohmic contact formation.

  The present invention is based on the surprising discovery that ohmic contacts (source and drain contacts) are not disturbed (and vice versa) by the presence of the (immediately below) SiN layer.

Semiconductor devices are provided that include:
substrate,
A first active layer,
The second active layer (on the first active layer), the second active layer has a higher band gap than the first active layer;
A two-dimensional electron gas layer between the first active layer and the second active layer;
A passivation layer (on the second active layer) composed of an electron donor element and nitrogen;
Source and drain contacts deposited directly on the passivation layer.

  In the context of the present invention, the term “on” refers to “directly or immediately above” when referring to the relative position of the two layers, unless otherwise specified. (I.e., there is no intermediate layer) or may mean "with one or more intermediate layers upwards".

  In particular, in semiconductor devices or in the method according to the invention, the source and drain contacts are present directly (deposited) on the passivation layer, i.e. (the source contact (or source electrode)). There is also no intermediate layer between the passivation layer and the passivation layer, nor between the drain contact (or drain electrode) and the passivation layer.

  In the semiconductor device according to the present invention, the electron donor element may be B, Se, C, or Ge, but is preferably Si.

  The electron donor element (especially Si) diffuses in the second active layer and acts as a donor there; furthermore, the introduction of a donor type into the second active layer facilitates the formation of an ohmic contact; As a result, the contact resistance is reduced.

  When one of the layers is made of Al, the latter can easily form an alloy with nitrogen, AlN, and the electron donor element (especially Si) that acts as a dopant in the AlGaN layer. it can. This facilitates ohmic contact formation.

  In the semiconductor device according to the present invention, the passivation layer may include (or consist of) CN, BN, GeN, or SiN. Preferably, the passivating layer contains (or consists of) BN or SiN. More preferably, the passivating layer contains (or consists of) SiN.

  Preferably, the passivation layer has a thickness between (approximately) 1 nm and (approximately) 30 nm.

  Preferably, the first active layer contains (or consists of) a group III nitride semiconductor material, and more preferably contains (or consists of) GaN.

  Preferably, the second active layer contains (or consists of) a group III nitride semiconductor material, and more preferably contains (or consists of) AlGa or AlGaInN.

  The semiconductor device of the present invention may further include a gate contact that is in electrical contact with the second active layer.

  The semiconductor device of the present invention further includes a spacer layer between the first active layer and the second active layer. The spacer layer is intended to increase mobility in the 2DEG layer. For example, the spacer layer may include (or consist of) AlN.

  The semiconductor device of the present invention may further include a third layer between the second active layer and the passivation layer. The third layer is further aimed at supplying electrons to the channel. Preferably, the third layer may include (or consist of) a group III nitride material.

  In the semiconductor device according to the present invention, the substrate may include (or consist of) a material selected from the group consisting of silicon, sapphire, SiC, GaN, and AlN.

The present invention also provides a method for producing a semiconductor device, including the following steps.
Placing a substrate in a reaction chamber;
Depositing a first active layer on the substrate;
A second active layer having a higher band gap than the first active layer is deposited on the first active layer, whereby a two-dimensional electron gas is formed between the first active layer and the second active layer. Forming a layer;
Depositing a passivation layer comprising at least an electron donor element and nitrogen on the second active layer;
Depositing source and drain contacts directly on the passivation layer.

  In the method of the present invention, the step of depositing the first, second active layer, and the passivation layer is performed in the reaction chamber without exposing the layer to air or the environment.

Prior to the step of depositing source and drain contacts, the method of the present invention preferably further comprises the following steps:
Cooling the reaction chamber; and
Removing the element (or structure) from the reaction chamber (with its deposited layer);

  In the method of the present invention, the reaction chamber may be a MOVPE or MBE reaction chamber.

  The method according to the present invention may further comprise forming a gate contact in electrical contact with the second active layer.

  The gate contact can be deposited directly on the passivation layer (ie, without an intermediate layer).

  Alternatively, the passivation layer can etch the channel region, in other words, between the source and drain contacts. The source and drain contacts remain directly on the passivation layer. Accordingly, the method of the present invention includes the source and drain contacts and the passivation after the step of directly depositing the source and drain contacts on the passivation layer and before the step of forming a gate contact. The method may further include etching between the layers.

  In the method of the present invention, the step of depositing the passivation layer is preferably carried out at a temperature between (approximately) 700 ° C. and (approximately) 1300 ° C.

  The passivation layer may include (or consist of) CN, BN, GeN, or SiN. Preferably, the passivating layer contains (or consists of) BN or SiN. More preferably, the passivating layer contains (or consists of) SiN.

  Preferably, the passivation layer is deposited to a thickness between (approximately) 1 nm and (approximately) 30 nm.

  In the method of the present invention, preferably, the first active layer contains (or consists of) a group III nitride semiconductor material, and more preferably contains (or consists of) GaN. ing).

  In the method of the present invention, preferably, the second active layer includes (or consists of) a group III nitride semiconductor material, and more preferably includes AlGaN or AlGaInN. It is configured).

  The method of the present invention may further include depositing a spacer layer between the first active layer and the second active layer. More specifically, the spacer layer is intended to increase the mobility in the two-dimensional electron gas layer. Preferably, the spacer layer contains (or consists of) AlN.

  The method of the present invention may further include depositing a third layer between the second active layer and the passivation layer. The third layer can be used for doping purposes or to increase the carrier density in the channel. Preferably, the third layer contains (or consists of) a group III nitride semiconductor material, and more preferably contains (or consists of) GaN.

  The method of the present invention may further include depositing a buffer layer between the substrate and the first active layer. The buffer layer is intended to provide an appropriate crystal structure transition between the substrate and another layer. Preferably, the buffer layer includes (or consists of) a group III nitride semiconductor material, and more preferably includes AlN, GaN, AlGaN, InGaN, and / or AlInGaN (or Is composed of).

  Preferably, in the method of the invention, the substrate comprises (or consists of) a material selected from the group comprising silicon, sapphire, SiC, GaN and AlN.

  The method according to the present invention can be used to create a group III-N field effect device, and more specifically, can be used to create a HEMT, MOSHFET, MESFET, MISFET, or MISHFET device.

  The invention further provides a semiconductor device obtainable by the method according to the invention.

FIG. 1 shows a HEMT device according to the present invention. The HEMT device (10) includes:
Substrate (11),
First active layer (12),
The second active layer (13) on the first active layer, the second active layer has a higher band gap than the first active layer;
A two-dimensional electron gas layer between the first active layer and the second active layer;
A passivating layer (14) on the second active layer,
The source contact (15) and drain contact (16), the source contact and drain contact are in contact with the passivation layer.

  The device can further include a gate (17) contact in electrical contact with the second active layer.

  In the present invention, the passivation layer is deposited on the second active layer in-situ at a high temperature in a MOCVD reaction chamber prior to cooling the structure and exposing the top surface to air contamination. Thereafter, transistor formation, particularly contact deposition, is performed significantly for ohmic contact without any significant removal of the passivation layer prior to contact deposition.

  MOVPE growth of such heterostructures will make the transistor performance better, and then the techniques shown will prepare high electron mobility transistors on these heterostructures: higher compared to: Current density, higher power performance: (a) a transistor made without any passivation, (b) a transistor made by in-situ passivation, or ex-situ between drain and source (C) Transistor made by in situ passivation and removal of the passivation layer below the ohmic contact. As an example, this is a transistor prepared with the ex situ deposition technique of the passivation layer between the drain and source, which is currently the most widely used in practice to develop III-nitride devices. The current density can be doubled.

  In-situ passivation prevents any contamination of the surface prior to treatment and no oxidation occurs on the surface of the second active layer.

  Second, because the passivation layer is deposited in-situ due to the high temperature near the growth temperature, the entire structure undergoes the same cooling step before cooling. Therefore, cooling from the growth temperature depends on the presence or absence of the passivating layer. The presence of the passivating layer increases the Al content in the layer without any minor cracking of the wafer. As a result, the 2DEG concentration can be increased.

  Growth of these structures and fabrication of transistors with this technique results in devices having the following characteristics:

  First, improved device ohmic contact quality: matched material properties obtained by Hall measurements showing low contact resistance, very linear IV characteristics, total current capability present in the channel Sheet resistance can be extracted through the contacts. In addition to providing good control of the surface energy levels as well as control of strain in the heterostructure, which is fully controlled during MOVPE growth, by passivating the surface, the deposition of the passivating layer Allows better ohmic contact formation with better control of wafer uniformity and reproducibility from one wafer to another. In other words, the uniformity and reproducibility of the ohmic contact is improved.

  Second, better transistor performance, such as higher current density in DC mode due to passivation of surface energy levels.

  Third, a reduction in the appearance of cracks when cooling the heterostructure from the growth temperature to room temperature due to the passivation layer being deposited at a high temperature on the second active layer. Accordingly, this can increase the thickness of the second active layer. If the second active layer is AlGaN, increasing its thickness can increase the Al content in the top layer and consequently increase the carrier density in the channel. Prior to cooling, the passivation layer is deposited at a higher temperature, thus reducing the formation of cracks, resulting in higher Al content and higher current density.

  FIG. 2 represents an AlGaN / GaN based HEMT (20) according to the present invention. The HEMT includes a substrate (21). This substrate may be sapphire, Sic, Si, or GaN.

  The substrate can include a nucleation layer on the substrate to accommodate changes in crystal parameters between the substrate and the layer.

  A buffer layer can also be included on the substrate to provide an appropriate crystal structure transition between the substrate and the remainder of the HEMT.

  The HEMT (20) includes a GaN (22) layer on the substrate, and an AlGaN (23) layer on the GaN layer, with the GaN layer being sandwiched between the substrate and the AlGaN layer.

  The GaN layer is typically between 1000 and 3000 nm thick and between 2000 and 3000 nm thick, while the AlGaN layer is between 10 nm and 50 nm thick, or between 10 nm and 40 nm thick.

  This top structure can be n-type doped or undoped, a single AlGaN layer, or a set of different layers doped or doped to increase confinement to the two-dimensional electron gas. It can be created with a layer that is not.

  The Al content can vary between 10% and 100%.

  The GaN layer and the AlGaN layer are usually formed by MOCVD.

  The HEMT (20) further includes a passivation layer (24) on the AlGaN layer. The passivation layer may cover the entire AlGaN layer or may partially cover the AlGaN layer. At least the region where the source and drain contacts are to be formed must be covered with a passivation layer.

  The passivation layer contains at least an electron donor element and nitrogen. In particular, the passivation layer can be made of SiN or AlN, or a combination comprising a multilayer film of SiN and AlN.

  The AlGaN layer has a higher band gap than the GaN layer.

  The surface charging layer can be formed in the device between the AlGaN layer and the GaN layer. This surface charged layer is compensated by forming a two-dimensional electron gas on the opposite side of the interface, which will result in a higher mobility value compared to the bulk material. This is useful for creating very high electron mobility channels in the device.

  The HEMT further includes a source contact (25) and a drain contact (26) on the passivation layer. The source and drain contacts are made of a metal, preferably an alloy of different metals, which is deposited as a layer and then annealed. The metal can be selected from the group consisting of Ti, Al, Ni, Mo, Ta, Pt, Pd, V, Nb, Zr, and / or Au.

  The gate contact (27) is preferably formed of a material selected from the group consisting of Ti, Pt, Cr, Ni, Mo, Co, Au, and Pd, combinations thereof, and alloys thereof.

  During operation of the HEMT, the drain contact is biased at a predetermined potential while the source contact is grounded. As a result, current will flow from the source to the channel and the drain in the 2DEG. The current flow is controlled by the bias and potential applied to the gate electrode.

  The presence of passivating layers between the AlGaN layer and the source and drain contacts respectively improves device performance.

  FIG. 3 shows an AlGaN / AlN / GaN based HEMT (30) similar to the HEMT (20) in FIG.

  The HEMT has similar layers including a substrate (31), an AlGaN layer (32), a GaN layer (33), and a passivation layer (34).

  Further, the HEMT includes a source electrode (35), a drain electrode (36), and a gate electrode (37).

  The HEMT (30) further includes an AlN layer (38) deposited on the AlGaN layer between the AlGaN layer and the GaN layer. This AlN layer makes it possible to achieve a narrower 2DEG channel with a high bandgap and thus reduced wave function penetration in the AlGaN layer, resulting in reduced diffusion (reducing the effect of interface roughness), Thereby, mobility increases.

  FIG. 4 shows a GaN / AlGaN / AlN / GaN based HEMT (40) similar to the HEMT (20) in FIG.

  The HEMT has similar layers including a substrate (41), an AlGaN layer (42), a GaN layer (43), and a passivation layer (44).

  The HEMT (40) further includes an AlN layer (48) deposited on the AlGaN layer between the AlGaN layer and the GaN layer.

  The HEMT (40) further includes a GaN layer (49) on top of the AlGaN layer.

  A passivation layer is deposited on the GaN layer. The GaN layer can prevent oxidation of the AlGaN layer.

  FIG. 5 shows an AlGaN / GaN based HEMT (50) similar to the HEMT in FIG.

  The HEMT has similar layers including a substrate (51), an AlGaN layer (52), and a GaN layer (53).

  Furthermore, the HEMT includes a source electrode (55), a drain electrode (56), and a gate electrode (57).

  The gate contact is in direct contact with the AlGaN layer, which means that there is no passivation layer (54) between the gate contact and the AlGaN layer.

FIG. 6 shows a method for forming a HEMT element. The method includes the following steps:
Placing the substrate in the reaction chamber (61);
Forming a first active layer on the substrate (62);
Forming a second active layer on the first active layer, the second active layer having a higher bandgap than the first active layer, whereby the first active layer and the second active layer; A two-dimensional electron gas layer is formed between the two (63),
Forming a passivation layer on the second active layer (64);
Forming a source contact and a drain contact; the source contact and the drain contact are in contact with the passivation layer, and a portion of the passivation layer is covered by the source contact and the drain contact. (65)

  The method may further include the step (66) of forming a gate contact in electrical contact with the second active layer. The gate contact is formed in an uncovered portion of the passivation layer. This step is optional.

  The steps of forming the first active layer, forming the second active layer, and forming the passivation layer are performed in a continuous process in an MOCVD reaction chamber, exposing the device to air. (Also the object of the present invention is called "in situ" formation). Oxide formation on the second active layer is substantially avoided. Furthermore, the step of removing the oxide film from the upper surface of the second active layer is avoided. This results in improved ohmic contact formation. The prior art has shown that the oxide that forms naturally on the top surface of the second active layer is very stable, so that high power and / or long duration prior to effective oxide removal. Plasma etching is required.

Such structural transistor processing consists of:
a. Device isolation by plasma etching or implantation,
b. Deposition of ohmic contacts on the (non-etched) SiN layer. The metal layer is made of a combination of different metal layers selected from the group consisting of Ti, Al, Ni, Mo, Ta, Pt, Pd, V, Nb, Zr, and Au, and alloys thereof.
c. Ohmic contact annealing, gate contact deposition (e-beam or optical gate). The gate is preferably made of a material selected from the group consisting of Ti, Pt, Cr, Ni, Mo, Co, Au, and Pd, and combinations and alloys thereof.
d. Optionally, a second passivating deposition step between the drain and source (which may be PECVD SiN or SiO ₂ ).
e. Any other lithography and metallization steps for alignment purposes or metal layer thickening that can be performed before or after any preceding steps.

  FIG. 7 shows a method for forming an AlGaN / GaN HEMT device according to the present invention.

The AlGaN / GaN structure is grown on a [0001] sapphire substrate by metal organic vapor phase epitaxy (MOVPE). The starting compounds are trimethylgallium (TMGa), trimethylaluminum (TMAl), ammonia (NH ₃ ), and silane (SiH ₄ , 200 ppm hydrogen). The silane introduction line is changed so that the amount of silane introduced into the reactor can be regulated from about 5 nmol / min to about 1 μmol / min.

As a first step (71) in the growth process, the substrate is annealed in H ₂ at 1050 ° C. and 53.33 mbar (40 torr). Thereafter, surface nitridation is performed at 800 ° C. by introducing NH ₃ into the reactor. The substrate is then cooled to 525 ° C. and a thin nucleation layer is grown for 120 seconds at 533.3 millibar (400 torr) by introducing TMGa into the reactor (78). Subsequently, the temperature is increased to 1020 ° C. and GaN is grown to a thickness of 2.6 microns at a pressure of 133.3 mbar (100 torr) (72). Thereafter, the growth is interrupted for 30 seconds while the reactor pressure is reduced to 53.33 mbar (40 torr). An AlN spacer layer is grown for 7-10 seconds (77) followed by a 20-22 nm thick Al _x Ga _1-x N layer (73).

After the last Group III-N layer has been grown at low pressure (below 266.6 mbar (200 torr)) and higher temperature (usually between 950 ° C. and 1200 ° C.), the Group III compound source is turned off. Meanwhile, NH ₃ continues to flow into the reactor and opens the SiH ₄ line, allowing SiN growth at high temperatures (74). After the growth of the thin SiN layer (between 1 nm and 30 nm), the flow of SiH ₄ is stopped, and the structure is cooled to room temperature, while NH ₃ continues to flow to avoid desorption from the top layer. After cooling the structure, the wafer is removed from the reactor. This surface is very well protected by the SiN passivation layer.

  The transistor processing (steps 75 and 76) having such a structure is the same as the above-described processing.

Example 1
AlGaN / GaN HEMT structures are grown at low pressure (133.3 millibar (100 torr)) using metal organic vapor phase epitaxy (MOVPE). As starting compounds, trimethylgallium (TMGa), trimethylaluminum (TMAl), and ammonia (NH ₃ ) are used.

  The organometallic precursor is transported with hydrogen as the carrier gas; the amount is regulated using the mass flow controller and the temperature of the thermostat bath fitted with the organometallic bubbler.

  The ammonia flow is also regulated using a mass flow controller, and traces of water and oxygen are removed by an in-line filter.

Additionally, n-type doping of GaN and (Al, Ga) N layers is achieved by adding silane (SiH ₄ ) during growth.

  All gases are introduced into the reactor via a so-called closed-coupled showerhead.

After degassing the substrate at a high temperature (1100 ° C.), a thin GaN buffer layer is deposited by using NH ₃ and TMGa at a lower temperature.

  Thereafter, the substrate temperature is set to 1020 ° C., and a 2 μm thick semi-insulating GaN layer is grown.

After 2 micrometers, the pressure is lowered to 53.33 millibar (40T), the temperature is raised to 1050 ° C., and the Al flow is contained (included) between 20% and 40% x. for the deposition of al _x Ga _1-x N, it is fed to the reactor. The standard thickness of AlGaN is 25 nm. Thereafter, a source of Ill-type element is sent to the vent, and SiH ₄ is introduced into the reactor simultaneously with NH ₃ under the same pressure and temperature conditions as the growth of AlGaN. SiN grows from NH ₃ and SiH ₄ at a growth rate of approximately 6 nm / h. The SiN layer can also be grown at a growth rate of 0.3 u / h.

Transistors are then fabricated on these structures using standard processing without etching the top SiN layer at all. The Transfer Length Method not only shows a reduction in ohmic contact resistance, but also greatly improves the uniformity of the IV characteristics, giving a sheet resistivity value that is in good agreement with the Hall measurement. A significant improvement in dc characteristics has been observed: drain-source current measurements for a positively biased gate (2V) show a reference sample of 0.5 A / s for a device width of 100 μm and a gate length of 0.2 μm. From mm to 1.2 A / mm with in situ passivation, a greater than factor 2 increase in current density is shown. The RF measurements show a f _{t of} 40 gigahertz and a f _max of 80 gigahertz for the same element shape. This is an increase in current density compared to the results obtained with ex-situ SiN passivation. Furthermore, improvements in DC and RF characteristics have been observed.

Example 2
AlGaN / GaN HEMT structures were grown by MOVPE on [0001] sapphire substrates. The Thomas Swan-Cross-coupled showerhead reactor is used with starting compounds of trimethylgallium (TMGa), trimethylaluminum (TMAl), ammonia (NH ₃ ), and diluted silane (SiH ₄ , 200 ppm in hydrogen). The silane introduction line is changed in such a way that the amount of silane introduced into the reactor can be regulated from the amount necessary for n-type doping of GaN (more than several nmol / min) to about 1 μmol / min. Is done.

After deposition of a thin GaN nucleation layer at low temperature, a 2.6 μm thick GaN layer is grown at 1020 ° C. and a reactor pressure of 133.3 mbar (100 torr). Prior to AlGaN, a thin AlN spacer layer is grown at 53.33 mbar (40 Torr) to improve mobility in 2DEG. Depending on the sample, the top AlGaN layer has a thickness of 22-24 nm and an Al content of 30%, as determined by high resolution X-ray diffraction measurements. After growth of the AlGaN layer, the NH ₃ flow was maintained while the reactor was purged for 10 seconds. Thereafter, silane was introduced. As a result, SiN with a thickness of 3.5-15 nm is presented.

Transistors are processed with these heterostructures. For comparison, a similar structure has been processed using the same technique at the same time without growing the SiN protective layer in situ. After mesa isolation by Cl ₂ based plasma etching, Ti / Al / Pt / Au contacts were deposited on the SiN top layer without any passivation layer etching followed by rapid thermal annealing. Electron beam lithography is used to pattern Ni / Au Schottky contacts to dimensions of 0.2 μm. Here, a second Si ₃ N ₄ passivation layer is deposited by PECVD to protect the transistor.

  To evaluate the ohmic contact characteristics on SiN capped heterostructures, the travel length method (TLM) shown in FIG. 8 was performed for three different annealing temperatures.

  The TLM measurement performed on an uncapped HEMT structure (without a SiN passivation layer) (81 at 820 ° C., 82 at 860 ° C., 83 at 900 ° C.) is the best of 1.49 Ωmm Gives ohmic contact resistance. However, because of the three different annealing temperatures, the slope of the TLM line giving the sheet resistance varies between 395 and 528 Ω / square and varies. These values are much higher than the resistance values determined by holes or by non-contact sheet resistivity measurements (Ω / square). In contrast, TLM measurements performed on a capped SiN epiwafer (with a SiN passivation layer) (84 at 820 ° C., 85 at 860 ° C., 86 at 900 ° C.) show sheet resistance values Displays a single sheet resistance value that is in good agreement with another decision. Furthermore, the ohmic contact resistance is reduced to a value of 0.88 Ωmm for a similar ohmic contact deposition scheme.

  DC drain source current-voltage characteristics for different gate bias voltages are given in FIGS. 9 (a) and 9 (b) with device width of 100 μm and gate length of 0.2 μm; one has a SiN passivation layer. (A), and the other has a SiN passivation layer (also called capped in situ) between the ohmic contact and the AlGaN layer, the passivation layer Is a 7 nm thick SiN layer (b), a similar HEMT structure is processed. For a gate bias voltage of 2V, the measured value shows an improvement greater than factor 2 at a current density of 0.5 A / mm to 1.2 A / mm.

Small signal RF measurements are also being performed on the transistors. Without having a SiN layer in situ, _{f t} and _{f max} are, respectively, 24 GHz and 68 GHz, is what is passivated in situ, _{f t} is 40 GHz, and _{f max} 80 gigahertz.

1 is a diagram representing a HEMT device according to the present invention. FIG. FIG. 2 is a diagram representing an AlGaN / GaN-based HEMT. FIG. 2 is a diagram representing an AlGaN / AlN / GaN based HEMT. 1 is a diagram representing a GaN / AlGaN / AlN / GaN based HEMT. FIG. FIG. 2 is a diagram representing an AlGaN / GaN-based HEMT. It is a figure showing the formation method of a HEMT element. It is a figure showing the formation method of an AlGaN / GaN base HEMT element. FIG. 6 represents travel length measurements for uncapped and capped HEMT structures at three different temperatures. (A) And (b) is a figure showing DC drain-source current-voltage characteristic with respect to different gate bias voltages.

Explanation of symbols

  10 HEMT device, 11 substrate, 12 first active layer, 13 second active layer, 14 passivation layer, 15 source contact, 16 drain contact, 17 gate, 20 HEMT, 21 substrate, 22 GaN layer, 23 AlGaN layer, 24 passivation layer, 25 source contact, 26 drain contact, 27 gate contact, 30 HEMT, 31 substrate, 32 AlGaN layer, 33 GaN layer, 34 passivation layer, 35 source electrode, 36 drain electrode, 37 gate electrode, 40 HEMT, 41 substrate, 42 AlGaN layer, 43 GaN layer, 44 passivation layer, 48 AlN layer, 49 GaN layer, 50 HEMT, 51 substrate, 52 AlGaN layer, 53 GaN layer, 54 passivation layer, 55 source Electrode, 56 drain electrode, 57 gate electrode.

Claims (39)

A substrate,
A first active layer;
A second active layer on the first active layer having a higher band gap than the first active layer;
A two-dimensional electron gas layer between the first active layer and the second active layer;
A passivation layer comprising an electron donor element and nitrogen on the second active layer;
A semiconductor device comprising a direct source contact and a drain contact on the passivation layer.   The semiconductor device according to claim 1, wherein the passivation layer includes SiN.   The semiconductor device according to claim 1, wherein the passivation layer includes BN.   The semiconductor device according to claim 1, wherein the first active layer includes a group III nitride semiconductor material.   The semiconductor device according to claim 4, wherein the first active layer includes GaN.   The semiconductor device according to claim 1, wherein the second active layer includes a group III nitride semiconductor material.   The semiconductor device according to claim 6, wherein the second active layer includes AlGaN, AlInN, or AlInGaN.   The semiconductor device according to claim 1, further comprising a gate contact in electrical contact with the second active layer.   The semiconductor device according to claim 1, further comprising a spacer layer between the first active layer and the second active layer.   The semiconductor device according to claim 9, wherein the spacer layer includes AlN.   The semiconductor device according to claim 1, further comprising a third layer between the second active layer and the passivation layer.   The semiconductor device according to claim 11, wherein the third layer includes a group III nitride material.   The semiconductor device according to claim 1, wherein the passivation layer has a thickness of 1 nm to 30 nm.   The semiconductor device according to claim 1, wherein the substrate includes a material selected from the group consisting of silicon, sapphire, SiC, GaN, and AlN. Placing a substrate in a reaction chamber;
Depositing a first active layer;
A second active layer having a higher band gap than the first active layer is deposited on the first active layer, whereby a two-dimensional electron gas is formed between the first active layer and the second active layer. Forming a layer;
Depositing a passivation layer comprising at least an electron donor element and nitrogen on the second active layer;
Depositing a source contact and a drain contact directly on the passivation layer.   16. The method of fabricating a semiconductor device according to claim 15, wherein the steps of depositing the first and second active layers and the passivation layer are performed in the reaction chamber without exposing the layers to air or the environment. . Before the step of depositing source and drain contacts,
Cooling the reaction chamber;
The method for producing a semiconductor device according to claim 15 or 16, further comprising: removing the device with the deposited layer from the reaction chamber.   The method for producing a semiconductor device according to claim 15, wherein the reaction chamber is a MOVPE or MBE reaction chamber.   The method for producing a semiconductor device according to claim 15, further comprising forming a gate contact that is in electrical contact with the second active layer.   20. The method of making a semiconductor device according to claim 19, wherein the gate contact is directly deposited on the passivation layer.   20. The method further comprises etching the passivation layer between the source and drain contacts after depositing the source and drain contacts and before forming the gate contact. A method for producing the semiconductor device described in 1.   The method for producing a semiconductor device according to claim 15, wherein the step of depositing the passivation layer is performed at a temperature between 700 ° C. and 1300 ° C.   The method for producing a semiconductor device according to claim 15, wherein the passivation layer contains SiN.   The method for producing a semiconductor device according to claim 15, wherein the first active layer includes a group III nitride semiconductor material.   25. The method of manufacturing a semiconductor device according to claim 24, wherein the first active layer includes GaN.   The method for producing a semiconductor device according to claim 15, wherein the second active layer includes a group III nitride semiconductor material.   27. The method of manufacturing a semiconductor device according to claim 26, wherein the second active layer includes AlGaN or AlGaInN.   The method for producing a semiconductor device according to claim 15, wherein the passivation layer is deposited so as to have a thickness of 1 nm to 30 nm.   29. The method of any one of claims 15 to 28, further comprising depositing a spacer layer between the first active layer and the second active layer to increase mobility in the two-dimensional electron gas. A method for producing the semiconductor device described in 1.   30. The method of manufacturing a semiconductor device according to claim 29, wherein the spacer layer includes AlN.   31. The method of claim 15-30, further comprising depositing a third layer between the second active layer and the passivation layer for doping purposes or to increase the carrier density in the channel. The manufacturing method of the semiconductor device as described in any one.   32. The method of manufacturing a semiconductor device according to claim 31, wherein the third layer includes a group III nitride semiconductor material.   The method for producing a semiconductor device according to claim 32, wherein the third layer includes GaN.   34. The method of any of claims 15-33, further comprising depositing a buffer layer between the substrate and the first active layer to provide a suitable crystal structure transition between the substrate and another layer. The manufacturing method of the semiconductor device as described in any one.   35. The method of manufacturing a semiconductor device according to claim 34, wherein the buffer layer includes a group III nitride semiconductor material.   36. The method of manufacturing a semiconductor device according to claim 35, wherein the buffer layer includes AlN, GaN, AlGaN, and / or AlInGaN.   37. The method for manufacturing a semiconductor device according to claim 15, wherein the substrate includes a material selected from the group consisting of silicon, sapphire, SiC, GaN, and AlN.   38. A method of making a HEMT, MOSHFET, MESFET, MISFET, or MISHFET device, comprising the method of any one of claims 15-37. A semiconductor device obtainable by the method according to any one of claims 15 to 38.

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