JP2003100778A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide various types of high performance semiconductor devices such as a field-effect transistor which can operate at high frequency, with high output and high efficiency by realizing a stable, low resistance ohmic contact. SOLUTION: This semiconductor device comprises a first nitride semiconductor layer (11), a second nitride semiconductor layer (12) which is formed on the first layer and has a larger band gap than that of the first layer, and an electrode (18) formed on the second layer. The second nitride semiconductor layer has lattice distortion caused by the difference in lattice constants between the first layer and the second layer, and by tunneling electrons accumulated in the vicinity of the heterointerface (H) of the first nitride semiconductor layer into the n-side electrode, the contact resistance of the n-side electrode can be reduced.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a nitride semiconductor, which is capable of reliably forming an ohmic contact with an electron, and which has a high output and a high frequency when applied to a transistor, for example. The present invention relates to a semiconductor device which operates with high efficiency.

2. Description of the Related Art GaN, which is a nitride semiconductor, has a wide band gap, is easy to form a heterojunction with AlGaN, and its characteristics can be widely controlled by adjusting the Al composition ratio. It is being applied to optical devices and electronic devices. For example, ME using a nitride semiconductor
SFET (Metal-Semiconductor Field Effect Transis
tor) and HEMT (High Electron Mobility Transisto
Field effect transistors such as r) or MODFETs (Modulation-Doped FETs) can operate at high voltage and are expected as high-power power devices. Among them, the HEMT structure is particularly promising because it has the advantage of being capable of accumulating a higher concentration of two-dimensional electrons at the hetero interface as compared with the GaAs HEMT. FIG. 11 shows a conventional Ga
It is a schematic diagram showing the principal part cross-section of N system HEMT. That is, as shown in the figure, in the case of the conventional HEMT, a wurtzite structure GaN layer 111 serving as a channel layer is formed on a sapphire substrate or a SiC substrate (not shown),
On this layer 111, 20
nm~30nm thickness of _{Al x Ga (1-x)} N (0 <
x <1) A layer structure in which the layer 112 is formed is used. The Schottky gate 120, the source electrode 118, and the drain electrode 119 are formed on the Al _x Ga.sub. _(1-x) N layer 112.

By the way, one of the important problems for operating such a transistor with high output, high efficiency and high frequency is to sufficiently lower the contact resistivity in the source / drain electrodes. is there. When the resistivity is high, the parasitic resistance increases, the knee voltage in the drain current characteristic increases, and the transconductance decreases. As a result, there arises a problem that output power, power load efficiency, and operating frequency are lowered. As an ohmic contact for a field effect transistor using a nitride semiconductor, a relatively good ohmic contact can be obtained in a laminated structure of titanium (Ti) / aluminum (Al). However, the characteristics change greatly depending on the film thickness ratio of titanium and aluminum, the annealing temperature, and the time (Kasahara et al., ED99-206, ED99-206.
9) There is a problem that it is very difficult to find good conditions. The same problem occurs not only in transistors but also in various semiconductor devices using nitride semiconductors such as light emitting elements. That is, also in a semiconductor device such as an LED or a semiconductor laser, the contact resistance between the nitride semiconductor and the electrode is a key to determine various important characteristics such as emission intensity and temperature characteristics. Therefore, realization of good ohmic contact is strongly desired over all semiconductor devices using nitride semiconductors. The present invention has been made based on the recognition of such problems. That is, it is an object of the present invention to provide various high-performance semiconductor devices including a field-effect transistor that stably realizes ohmic contact with low resistance and operates at high frequency, high output, and high efficiency.

To achieve the above object, a first semiconductor device of the present invention is provided with a first nitride semiconductor layer and the first nitride semiconductor layer. A second nitride semiconductor layer having a bandgap larger than that of the first nitride semiconductor layer; and an electrode provided on the second nitride semiconductor layer, the second nitride semiconductor layer The layer has a lattice strain due to a difference in lattice constant between the layer and the first nitride semiconductor layer, and electrons accumulated in the vicinity of the hetero interface of the first nitride semiconductor layer are applied to the electrode. The tunneling reduces the contact resistance of the n-side electrode. According to the above configuration, the contact resistivity can be reduced by tunneling the electrons accumulated at the hetero interface to the electrode, and various characteristics of the semiconductor device can be improved. On the other hand, a second semiconductor device according to the present invention has a wurtzite structure, is provided on the first nitride semiconductor layer, and is provided on the first nitride semiconductor layer. A second nitride semiconductor layer having a different lattice constant, a larger bandgap and no lattice relaxation, and an n-side electrode provided on the second nitride semiconductor layer. , The second
The thickness of the nitride semiconductor layer is set in a range in which the contact resistance of the electrode is reduced by a tunnel current component of electrons accumulated near the hetero interface of the first nitride semiconductor layer to the n-side electrode. It is characterized by Also with the above configuration, the contact resistivity can be reduced by tunneling the electrons accumulated at the hetero interface to the electrode, and various characteristics of the semiconductor device can be improved.
Further, a third semiconductor device of the present invention is provided on the first nitride semiconductor layer having a wurtzite structure and the first nitride semiconductor layer, and the first nitride semiconductor layer is provided. And a second nitride semiconductor layer having a larger band gap and no lattice relaxation, and the second
A source electrode and a drain electrode provided on the nitride semiconductor layer, and a Schottky gate electrode provided on the second nitride semiconductor layer. The layer thickness is set in a range in which a contact resistance of the source electrode and the drain electrode is reduced by a tunnel current component of electrons accumulated near the hetero interface of the first nitride semiconductor layer to the source electrode and the drain electrode. It is characterized by According to the above configuration, the contact resistivity of the source electrode and the drain electrode can be reduced by tunneling the electrons accumulated at the hetero interface to the electrode, and various characteristics of the semiconductor device can be improved. Further, a fourth semiconductor device of the present invention is provided with a first nitride semiconductor layer having a wurtzite structure and the first nitride semiconductor layer selectively provided on the first nitride semiconductor layer. A second nitride semiconductor layer having a larger bandgap and a lattice relaxation, which is different from that of the first semiconductor layer, and the first nitride semiconductor layer; A third nitride semiconductor layer having a larger bandgap and a lattice constant different from that of the first nitride semiconductor layer; a source electrode and a drain electrode provided on the second nitride semiconductor layer; A Schottky gate electrode provided on the third nitride semiconductor layer, wherein the layer thickness of the second nitride semiconductor layer is accumulated in the vicinity of the hetero interface of the first nitride semiconductor layer. Electrons to the source and drain electrodes Characterized in that it is a range where lowering of the contact resistance of the source electrode and the drain electrode by tunneling current component is generated. Also with the above configuration, the contact resistivity of the source electrode and the drain electrode can be reduced by tunneling the electrons accumulated at the hetero interface to the electrode, and various characteristics of the semiconductor device can be improved. Here, in the first to fourth semiconductor devices, if the layer thickness of the second nitride semiconductor layer is 6 nm or less, the tunnel current component is significantly increased and the contact resistance is significantly increased. It is possible to lower it. In addition, the surface of the first nitride semiconductor layer on which the second nitride semiconductor layer is laminated is II
If the surface is a group I element, the effect of charge accumulation due to polarization can be remarkably obtained. Further, if the first nitride semiconductor layer is made of GaN and the second nitride semiconductor layer is made of AlGaN, it can be easily applied to many semiconductor devices and the contact resistance can be reduced. The effect is surely obtained. For example, when the present invention is applied to a transistor, the current due to the tunnel phenomenon can be increased between the two-dimensional electrons accumulated at the hetero interface and the metal to be the ohmic electrode, and an ohmic electrode having a low resistivity can be obtained. As a result, the field effect transistor can be operated with high output, high efficiency and high frequency. In the present specification, the term “nitride semiconductor” means B
_{1-x-y-z In} x Al y Ga z N (x ≦ 1, y ≦
In the chemical formula of 1, z ≦ 1, x + y + z ≦ 1), it is assumed that the semiconductors of all the compositions in which the composition ratios x, y, and z are changed within the respective ranges are included. Furthermore, a material obtained by introducing a predetermined n-type or p-type dopant and various impurities such as proton, oxygen (O), iron (Fe), etc., into these is also included in the “nitride semiconductor”.

DETAILED DESCRIPTION OF THE INVENTION The present invention will now be described with reference to the drawings.
The embodiment will be described in detail. FIG. 1 shows the present invention.
FIG. 3 is a schematic diagram showing a cross-sectional structure of a main part of the semiconductor device of FIG. sand
That is, the figure shows the cross-sectional structure of the electrode portion of the semiconductor device S.
It is the conceptual diagram which expanded and displayed. As such a semiconductor device
Including transistors, which will be mentioned later as specific examples.
Light emitting diode, semiconductor laser or other
A class of optical and electronic devices can be mentioned.
These semiconductor devices consist of substrates such as sapphire and SiC.
It may be one formed on the top surface,
It may not be. And according to the present invention,
In the electrode formation portion of these semiconductor devices S, the first
A nitride semiconductor layer 11, a second nitride semiconductor layer 12, and
The electrode 18 and the electrode 18 are laminated in this order. Since
Hereinafter, these components will be described in detail. First,
The first nitride semiconductor layer 11 has a wurtzite structure,
Crystal lattice is not substantially distorted due to external stress
State, that is, the original lattice constant in the free state
The main body of the semiconductor device (not shown)
Is provided in at least a part of the. First nitride semiconductor
A specific example of the body layer 11 is GaN.
You can In addition to GaN, for example, GaN
A group III element other than Ga may be added. Also
Further, the upper surface 11U of the first nitride semiconductor layer is
It must be a (0001) plane and a group III element plane.
And is desirable. For example, if this layer 11 is made of GaN,
In this case, the upper surface 11U has (0001) gallium (G
It is preferably a) surface. Next, the second nitride semiconductor
The body layer 12 has a lattice constant different from that of the first nitride semiconductor layer 11.
Has a larger bandgap and lattice relaxation
I haven't. That is, the second nitride semiconductor layer 12 is
It is said that the crystal lattice is distorted under the general stress.
The factors that cause this "distortion" are typically:
To list the difference in lattice constant from the first nitride semiconductor layer
You can That is, the first nitride semiconductors with different lattice constants
Stacking the second nitride semiconductor layer 12 on the body layer 11;
And the misfit strain is caused by the second nitride semiconductor layer 1
2 can be introduced. Second nitride semiconductor layer 12
As a specific example of, for example, AlGaN can be cited.
it can. That is, the first nitride semiconductor made of GaN or the like
Al having a larger band gap on the body layer 11
GaN is laminated in a lattice-relaxed state. Again
In addition, the second nitride layer 12 has a thickness within a predetermined range.
Is also desirable, and more specifically, the first nitride
The tunnel current component from the semiconductor layer 11 to the electrode 18
It has a range of layer thicknesses substantially obtained. The layer thickness is
It is desirable that the thickness is 6 nm or less. like this
An electrode 18 is provided on the second nitride semiconductor layer 12.
Has been. The electrode 18 is made of an n-type nitride semiconductor.
Appropriately use known materials as ohmic electrode materials
You can For example, titanium (Ti) and aluminum (A
It is possible to use a structure in which
It According to the structure described above, the semiconductor device S on the n-side
Good ohmic contact with reduced contact resistance
You get The reason will be described in detail below. example
For example, Al on GaN_xGa_(1-x)N layers were laminated
In the structure, Al_xGa_(1-x)The N layer relaxes the lattice
If not present, charge due to large piezoelectric and spontaneous polarization
Is known to occur (Ambacher et al., J. App
l. Phys., 85.no.6, p.3222, 1999). Wurtzite structure
As it has the original lattice constant in the free state
First nitride semiconductor layer 11 (for example, GaN) in various states
On the Ga surface of the second nitride semiconductor layer 12 that does not undergo lattice relaxation.
(For example, Al_xGa_(1-x)When N) is laminated,
At the hetero-interface H of the
The charge accumulates, and at the same time, the electron E corresponding to this charge is hetero
It accumulates in the first nitride semiconductor layer 11 near the interface H.
In the structure of the present invention, the first nitride semiconductor layer 11 (for example,
Second nitride semiconductor layer 12 laminated on GaN).
(For example, Al_xGa_(1-x)N) thin
This reduces the distance between the hetero interface H and the electrode 18.
The electrons E accumulated at the hetero interface H flow into the electrode 18.
Make it easy. The electron density at the hetero interface H is
Dependence on Positive Charge Due to Piezoelectric and Spontaneous Polarization
Then, AlGaN is used as the second nitride semiconductor layer 12.
Strongly depends on the molar ratio of aluminum (Al) when
To do. The phenomenon described above is caused by the GaAs heterojunction.
Which is unique to nitride semiconductor heterojunctions.
It is a phenomenon. Figure 2 shows Al on GaN_0.3Ga_0.7
N is formed, and further Al_0.3Ga _0.7Titanium on N
Potent under the conduction band in a structure in which (Ti) is laminated
It is a graph showing the Charl distribution. Ie this graph
Is the result obtained by solving the Poisson equation and
is there. In addition, here, Al_0.3Ga_0.7N is Donna
Concentration is 1 × 10¹⁸cm^-3Of the n-type. Well
Al_0.3Ga_0.7At the interface between N and GaN,
Charge due to piezo polarization and spontaneous polarization corresponding to the junction of
I decided. Furthermore, in this calculation, Al_0.3Ga
_0.7Change the thickness d of N to 2 nm, 10 nm and 20 nm.
And the electrons follow the Fermi-Dirac distribution.
As shown in FIG. 2, in any structure, the hetero
A potential well W is formed near the interface. So
And electrons accumulate in these potential wells W.
It Al_0.3Ga_0.7N is made thinner and the thickness is
Even if the thickness is 2 nm, a potential well W is created.
It can be seen that electrons accumulate at the hetero interface. this
The electrons accumulated in the part are transferred to the metal electrode 18 on the semiconductor surface.
In order to flow by the channel phenomenon, Al_0.3Ga_0.7N is
It is effective to make the potential barrier thinner by making it thinner.
This can be expected to increase the current.
It From the potential distribution illustrated in FIG. 2, the structure of FIG.
At the electrode 18 at the
The balance with the channel current can be calculated. Figure 3
Is the thermionic emission current of the tunnel current in the structure of FIG.
It is a graph showing the ratio to. That is, in the figure
Horizontal axis is Al_0.3Ga_0.7N (second nitride semiconductor layer
12), where the vertical axis represents the flow through this semiconductor layer.
Represents the ratio of the tunneling current to the thermionic emission current.
Also here, Al_0.3Ga_0.7Carrier concentration of N
1 x 10¹⁸cm^-31 x 10¹⁹cm^-35x
10¹⁹cm^-33 levels. From FIG.
Even at a carrier concentration of_0.3Ga_0.7N layer
The ratio of tunnel current tends to increase as the thickness decreases.
Can be seen. Al_0.3Ga_{0 ． 7}N carrier concentration is 1
× 10¹⁸cm^-3In the case of, the film thickness is thinner than about 20 nm.
The tunnel current component starts to increase and the film thickness is about 1
It can be seen that when the thickness becomes thinner than 0 nm, it sharply increases.
In addition, the carrier concentration is 1 × 10¹⁹cm^-3If the membrane
If the thickness is less than about 15 nm, the tunnel current component increases.
When the film thickness becomes thinner than about 8 nm, it increases rapidly
To do. On the other hand, the carrier concentration is 5 × 10¹⁹cm^-3Place
If the film thickness is less than about 8 nm, the tunnel current component
Begins to increase, and suddenly when the film thickness becomes thinner than about 6 nm
Increase to. In this way,
As the thickness gets thinner, the contact resistance decreases significantly due to the tunnel current.
Will be obtained. Tunnel as illustrated in Figure 3
From the current and thermionic emission current data, the contour of the electrode 18
You can calculate the electrical resistivity. FIG. 4 shows the structure of FIG.
6 is a graph showing the contact resistivity of the electrode 18. FIG. same
From the figure, for example, the donor concentration is 1 × 10¹⁸cm^-3Place
If Al_0.3Ga _0.7The thickness of N is 10 nm or less
Then, it can be seen that the contact resistivity drops sharply.
Also, looking at the data of other concentration levels,
_0.3Ga_0.7When the thickness of N is 10 nm or less,
The tact resistivity decreases sharply, and becomes remarkable when the thickness is 6 nm or less.
You can see that it drops to. Here, in FIG. 4, there are three levels.
The change in resistance was shown for each of the donor concentrations of
If the thickness is reduced to 2 nm, the resistivity is almost
It converges to one point without depending on how much. The results shown in Figure 4 are half
Second nitride, which is based on the effective mass approximation of the conductor.
The thinner the semiconductor layer (eg, AlGaN), the lower the resistivity.
It shows that it can be reduced. In fact, the second nitride half
Conductor layer (eg Al_0.3Ga_{0 ． 7}N) has a small thickness
At least it is necessary to be larger than the lattice constant. Professional
Process variation, the thickness of the second nitride semiconductor layer 12
Is required to be at least twice the lattice constant of the c-axis.
When 1xGa (1-x) N is used, its thickness is a lattice constant.
1.2 nm or more, which is twice the number of 0.6 nm
is necessary. By the way, according to the result shown in FIG.
Al like the conventional transistor structure _0.3Ga_0.7
The thickness of N is 20 nm to 30 nm and the donor concentration is 10¹⁸
cm^{− Three}The contact resistivity is 0.1
Ω cm^TwoAbove all, it becomes a very high value. Only
However, in the actual process, before the deposition of the ohmic electrode, R
Performs IE (Reactive Ion Etching) processing, electrodes
After vapor deposition, perform a high temperature anneal at 600 ° C to 900 ° C.
Increase the effective carrier concentration on the semiconductor surface.
It seems that there is. 850 GaN according to Schloss et al.
When annealed at ℃, the carrier concentration may increase by an order of magnitude.
Reported (Appl. Phya. Lett., 68, No. 19, p.270
2, 1996). On the other hand, in the case of a normal GaN-based HEMT,
High-density 2D electrons without deterioration
Al so as to accumulate_xGa_(1-x)The concentration of N dona
(1-5) x 10¹⁸cm^-3  In many cases Sc
According to the report of hloss et al.
-The effective carrier concentration is (1 to 5) x 10 depending on
¹⁹cm^-3It is believed that Therefore, like this
When the present invention is applied to the transistor, the result of FIG.
The carrier concentration is 5 × 10¹⁹cm^-3But Al
_xGa_(1-x)The effect of reducing the resistivity by thinning N
To get Al_xGa_(1-x)The thickness of N is 6 nm or less
Is desirable.

EXAMPLES Hereinafter, the present invention will be described with reference to examples.
The form will be described in more detail. (First Embodiment) FIG. 5 shows a first embodiment of the present invention.
The cross-sectional structure of the main part of the heterojunction field effect transistor of
It is a schematic diagram. That is, this transistor is
A thickness of 1 nm or more and 6 nm or less on the N-channel layer 11.
AlxGa (1-x) N layer 12 is laminated and
Source electrode 18, drain electrode 19 and gate electrode
20 has a structure formed respectively. This field effect
For the structure of a transistor, refer to the manufacturing process below.
I will explain while illuminating. First, not shown (0001) suff
Nucleation consisting of AlN on a fire or SiC substrate
The layer is thin, for example, about 4 nm. On top of this,
The undoped GaN layer 11 is formed by MOCVD (Metal-Organi
c Chemical Vapor Deposition: Metalorganic chemical vapor deposition
Length) method to obtain a sufficiently thick film, for example, a thickness of 2 μm.
Make it longer. Next, Al_xGa_(1-x)N (0 <x <
1) As the layer 12, for example, the molar ratio x of Al is 0.3
Become Al_0.3Ga_0.7N layer in the range of 1 nm to 6 nm
The thickness of the enclosure, for example 2 nm, is also MOCVD
It is formed by the method. Crystal growth by MOCVD
Includes an organometallic compound containing Ga (for example, trimethyl
Gallium) first source gas and an organometallic compound containing Al
Second source gas of a substance (for example, trimethylaluminum)
And a third source gas containing nitrogen (for example, ammonia)
Can be used. Al_0.3Ga_0.7N layer 12
It can be either anodic or n-type, but in this case
Na concentration is 5 × 10¹⁸cm^-3Silicon to be the n-type
Layer (Si) as an impurity. Led silicon
The raw material gas to be introduced is silane or tetrae
Organosilanes such as tylsilane can be used. This
After crystal growth like_0.3Ga_0.7N layer 12
Metal to be an ohmic electrode on top, eg Ti (bottom)
/ Al / Ni / Au (above) 25 nm and 250 respectively
nm, 40 nm, 45 nm thickness to be laminated
Then, the source electrode 18 and the drain electrode 19 are formed.
It Furthermore, between these, the work function is better than that of titanium (Ti).
Large number, Al_0.3Ga_0.7Schottky junction with N
Combination of metals to be used, such as Ni (lower layer) / Au (upper layer)
Layers) with a thickness of 50 nm and a thickness of 250 nm, respectively.
So that Al_{0. Three}Ga_0.7Deposition type on N layer 12
To form the gate electrode 20. According to this embodiment, the saw
Between the drain electrodes 18 and 19 and the GaN layer 11
By providing an AlxGa (1-x) N layer 12
The resistivity of the ohmic electrode could be reduced. Well
Further, in the structure of this embodiment, Al_xGa_(1-x)
Since the thickness of the N layer 12 is limited to a narrow range, a combination of Al
The threshold voltage will be a substantially constant value when it is determined. Tsuma
The desired threshold voltage by changing the Al composition ratio.
Can be obtained. (Second Embodiment) FIG. 6 shows a second embodiment of the present invention.
The cross-sectional structure of the main part of the heterojunction field effect transistor of
It is a schematic diagram. Regarding FIG. 1 to FIG.
The same elements as those described above are given the same reference numerals
Detailed explanation is omitted. In the case of the transistor of this embodiment
Is Al_xGa_(1-x)N layer 12A is a conventional transition
In the same way as the
Keep it. Then, the lower portion 12 of the ohmic electrodes 18 and 19
The structure is such that B is thinned in the range of 1 nm to 6 nm.
Also in this structure, the same effect as that of the first embodiment can be obtained.
It To create the structure of this embodiment, create the first embodiment.
In the method, Al_xGa _(1-x)The N layer 12 has a conventional structure.
Source / drain electrode 1
Form these ohmic electrodes before forming 8 and 19
Al_xGa_{(1 -X)}Etch a part of N layer
Add steps. When etching, use chlorine gas, etc.
The reactive ion etching technique used can
It This structure has a desired threshold voltage as compared with the first embodiment.
It is more flexible in terms of realization. However, d
It takes time to create because it requires the addition of a hatching process.
And the cost increases. Electric field structure transistor of this embodiment
Regarding the contact between the source electrode 18 and the drain electrode 19,
When measuring the electrical resistance, it was reduced to 1/10 of the conventional structure.
did it. As a result, the knee voltage of the drain current characteristic is 10
%, Transconductance improved by 20%. This
As a result, power is added at a frequency of 20 GHz and class AB operation.
The maximum efficiency should be 10% larger than that of the conventional structure.
I was able to. (Third Embodiment) FIG. 7 shows a third embodiment of the present invention.
The cross-sectional structure of the main part of the heterojunction field effect transistor of
It is a schematic diagram. Regarding this figure as well, regarding FIG. 1 to FIG.
The same elements as those described above are given the same reference numerals
Detailed explanation is omitted. In the case of the transistor of this embodiment
Is the etched Al in the structure of the second embodiment.
_xGa_(1-x)The ohmic electrode is formed on the region of the N layer 12B.
Wider than the source / drain electrodes 18 and 19
is doing. In the current process, Al_xGa
_(1-x)Mask and ohmic used for etching N layer
The mask used for patterning the electrode
It is necessary to have a margin considering "re". Obey
Therefore, it is difficult to accurately create the structure shown in FIG.
It is easier to manufacture a structure with a margin as in this embodiment.
It's easy. In addition, in the transistor of this embodiment
The source / drain electrodes 18 and 19 and the GaN layer 11
A thin AlxGa (1-x) N layer 12B between them.
By doing so, the resistivity of the ohmic electrode can be reduced.
Came. (Fourth Embodiment) FIG. 8 shows a fourth embodiment of the present invention.
The cross-sectional structure of the main part of the heterojunction field effect transistor of
It is a schematic diagram. Regarding this figure as well, regarding FIG. 1 to FIG.
The same elements as those described above are given the same reference numerals
Detailed explanation is omitted. In the case of the transistor of this embodiment
Is the etched Al in the structure of the second embodiment.
_xGa_(1-x)The ohmic electrode is formed on the region of the N layer 12B.
Formed narrower than source / drain electrodes 18 and 19
is doing. Also in this embodiment, with respect to the third embodiment,
As mentioned, Al_xGa_{(1- x)}Etching of N layer
Used for patterning mask and ohmic electrode used for
Margin is provided considering the “misalignment” of the mask.
Therefore, it is easy to manufacture. In addition, the tiger of this embodiment
In the transistor, the source / drain electrodes 18 and 19 are also included.
Thin AlxGa (1-x) N layer between GaN layer 11 and GaN layer 11
By providing 12B, the resistivity of the ohmic electrode can be increased.
Could be reduced. (Fifth Embodiment) FIG. 9 shows a fifth embodiment of the present invention.
The cross-sectional structure of the main part of the heterojunction field effect transistor of
It is a schematic diagram. Hereinafter, the structure of the transistor of this example
Will be described with reference to the manufacturing process thereof. First,
If a sapphire substrate is formed by a method such as MOCVD,
Or a thin AlN nucleation layer on a SiC substrate, for example
4 nm thick, and a GaN layer 11 to serve as a channel is formed thereon.
Grown sufficiently thick, eg 2 μm, and_xGa
_(1-x)N layer, eg Al_0.3Ga_0.7N layer 1
3 is sequentially grown to 20 nm. With these MOCVD
The same crystal growth as described above with respect to the first embodiment.
Such gases can be used. Also, Al_0.3Ga
_0.7The N layer 13 has a donor concentration of 5 × 10¹⁸cm^-3of
A layer containing silicon as an impurity so as to be n-type.
The source gas for introducing Si is the same as in the first embodiment.
You can Next, SiO 2 is formed on the entire surface of the substrate by thermal CVD or the like.
_TwoAfter depositing the film, photolithography is performed in the lithography process.
Pattern the resist and mask the photoresist
Wet etching with ammonium fluoride etc.
Then, by removing the photoresist, Si
O_TwoForm a mask. Chlorine gas and argon
For example, ECR-RIBE (Electr
on Cyclotron Resonance-Reactive Ion BeamEtching)
N-type Al_0.3Ga_0.7Etching of N layer 13
I do. Next, SiO_TwoMask with ammonium fluoride, etc.
And remove it by using MBE (Molecular Beam Epitaxial) equipment
And with a thickness in the range of 1 nm to 6 nm, for example Al
Al whose molar ratio x is 0.3_0.3Ga_0.7N layer 1
Re-growing 2 on the entire surface. Next, the entire surface of the substrate is subjected to thermal CVD or the like.
SiO_TwoAfter depositing the film, use the lithography process to
Pattern the photoresist and remove the photoresist.
Wet etching with ammonium fluoride as a mask
And n-type Al by the previous etching _0.3Ga
_0.7The N layer 13 is re-formed on the GaN layer 11 in the removed region.
Grown Al _0.3Ga_0.7A vapor deposition device on the N layer 12
For example, Ti (lower layer) / Al (upper layer) 25n each
m and 250 nm of a laminated metal film are vapor-deposited and lift-off is performed.
After the step, for example, in a nitrogen atmosphere at 900 ° C. for 30 seconds
Heat treatment is performed to remove the source electrode 18 and the drain electrode 19.
Form. Then, photolithography is performed in the lithography process.
Pattern the photoresist and use the photoresist as a mask.
Wet etching with ammonium fluoride,
Then n-type Al_0.3Ga_0.7Re-grown on the N layer 13
Al_0.3Ga_0.7Example of vapor deposition equipment on N layer 12
For example, Ni (lower layer) / Au (upper layer) 50 nm,
A lift-off process is performed by depositing a laminated metal film of 250 nm.
After that, for example, heat treatment at 300 ° C. for 10 minutes in a nitrogen atmosphere.
Then, the gate electrode 20 is formed. Book explained above
According to the embodiment, the gate portion is formed of the thick AlGaN layer 13.
By providing the threshold, the threshold can be controlled reliably and easily, and the saw
In the contact portion of the drain electrode, thin AlGaN
The provision of the layer 12 reduces the contact resistance of the present invention.
The effect can be surely obtained. (Sixth Embodiment) FIG. 10 shows a sixth embodiment of the present invention.
All the heterojunction field effect transistors
It is a schematic diagram showing. Hereinafter, the structure of the transistor of this embodiment will be described.
The structure will be described with reference to the manufacturing process. Well
On a sapphire substrate by a method such as MOCVD
Alternatively, if the AlN nucleation layer is thin on the SiC substrate,
For example, it is formed to a thickness of 4 nm, and the channel is undoped on this.
Grow the GaN layer 11 sufficiently thick, for example 2 μm,
Undoped Al to be a spacer layer on this_0.3Ga
_0.7N layer 12 is grown to a thickness in the range of 1 nm to 6 nm.
Then, n-type Al to be an electron supply layer_0.3Ga
_0.7The N layer 16 is sequentially grown to 10 nm. On this
Undoped Al to be a hotkey contact layer_0.3G
a_0.7The N layer 17 is formed to a thickness of 5 nm. these
For crystal growth by MOCVD, refer to the first embodiment.
Gases similar to those mentioned can be used. Electronic companion
Al as a supply layer_0.3Ga_0.7The N layer 16 has a donor concentration
5 x 10¹⁸cm^-3Impurity of silicon to be n-type
The layer to be included as an object. Raw material for introducing silicon
The gas can be the same as in the first embodiment.
It Next, SiO 2 is formed on the entire surface of the substrate by thermal CVD or the like._TwoDeposited film
Then, in the lithography process, the photoresist pattern is
By using the photoresist as a mask.
Wet etching with ammonia, etc., and then
By removing the photoresist, SiO_TwoForming a mask
It Chlorine-based gas and inert gas such as argon were used
For example, by ECR-RIBE, an n-type A that is an electron supply layer
l_0.3Ga_{0 ． 7}N layer 16 and Schottky contact
Undoped Al that is a layer_0.3Ga_{0 ．}7N layer 17
Etching. Next, SiO 2 is formed on the entire surface of the substrate by thermal CVD or the like.
_TwoAfter depositing the film, photolithography is performed in the lithography process.
Pattern the resist and mask the photoresist
Wet etching with ammonium fluoride etc.
The space exposed on the surface by the previous etching.
Undoped Al that is a sa layer_0.3Ga_0.7On N layer 12
In the vapor deposition device, for example, Ti (lower layer) / Al (upper layer)
Vapor deposition of laminated metal film consisting of 25 nm and 250 nm, respectively
However, after the lift-off process, for example, 900 in a nitrogen atmosphere.
The source electrode 18 and the drain are subjected to heat treatment at 30 ° C. for 30 seconds.
The electrode 19 is formed. Then, in the lithography process
Photoresist patterning by
Wet etching with ammonium fluoride etc.
And then, for example, Ni (lower layer) /
Au (upper layer) product of 50 nm and 250 nm, respectively
After depositing a layer metal film and performing a lift-off process, for example, in a nitrogen atmosphere.
Undoped by heat treatment at 300 ° C for 10 minutes in air
Al_0.3Ga_0.7Form the gate electrode 20 on the N layer 17
To achieve. Also in this embodiment, the source / drain electrode 1
8 and 19 and the GaN layer 11 between the thin AlxGa (1-
x) By providing the N layer 12, the resistance of the ohmic electrode is
The drag ratio could be reduced. Above are some specific examples.
Embodiments of the present invention have been described. However,
The description is not limited to the specific examples described above. An example
For example, the present invention is limited to the transistors shown as specific examples.
Not specified, but there are light emitting diodes and semiconductor lasers
Or other various semiconductor devices to obtain the same effect.
Can also be included in the scope of the present invention. Well
The transistor structure is also shown as a specific example.
The present invention is not limited to the above, and those skilled in the art can apply the present invention.
All semiconductor devices obtained by design modification while
It is included in the range of light. For example, each part of the semiconductor device is configured.
Material, added impurities, film thickness, shape, conductivity type, formation method
The present invention is one in which a person skilled in the art appropriately changes the design of the law.
It is included in the range of.

As described in detail above, according to the present invention,
It is possible to significantly lower the contact resistance of a semiconductor device using a nitride semiconductor to electrons as compared with the related art. For example, in the case of a field effect transistor, electrons at the hetero interface generated by polarization peculiar to the nitride semiconductor hetero interface are , Al _x Ga.sub. _(1-x) N layer is thinned to increase the current caused by the tunnel phenomenon, so that an ohmic electrode with low contact resistance can be formed.
As a result, the knee voltage of the drain current characteristic is low,
High transconductance, high output, high efficiency,
High frequency operation becomes possible. That is, according to the present invention, the n-side ohmic contact of the nitride semiconductor device can be formed reliably and easily, and the characteristics of various semiconductor devices can be improved, which is a great industrial advantage.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a cross-sectional structure of a main part of a semiconductor device of the present invention.

FIG. 2 shows Al _0.3 Ga _0.7 N formed on GaN,
It is a graph showing the potential distribution of the lower part of the conduction band in the structure in which titanium (Ti) is further laminated on Al _0.3 Ga _0.7 N.

FIG. 3 is a graph showing the ratio of tunneling current to thermionic emission current in the structure of FIG.

4 is a graph showing a contact resistivity of an electrode 18 in the structure of FIG.

FIG. 5 is a schematic view showing a cross-sectional structure of a main part of a heterojunction field effect transistor as a first embodiment of the present invention.

FIG. 6 is a schematic view showing a cross-sectional structure of a main part of a heterojunction field effect transistor as a second embodiment of the present invention.

FIG. 7 is a schematic diagram showing a cross-sectional structure of a main part of a heterojunction field effect transistor as a third embodiment of the present invention.

FIG. 8 is a schematic diagram showing a cross-sectional structure of a main part of a heterojunction field effect transistor as a fourth embodiment of the present invention.

FIG. 9 is a schematic diagram showing a cross-sectional structure of a main part of a heterojunction field effect transistor as a fifth embodiment of the present invention.

FIG. 10 is a schematic diagram showing a cross-sectional structure of a main part of a heterojunction field effect transistor as a sixth embodiment of the present invention.

FIG. 11 is a schematic diagram showing a cross-sectional structure of a main part of a conventional GaN-based HEMT.

[Explanation of symbols]

11 First Nitride Semiconductor Layer (GaN Layer) 11U upper surface 12, 12B Second nitride semiconductor layer (AlGaN layer) 12A, 13, 14, 16, 17 AlGaN layer 18 Source electrode 19 Drain electrode 20 gate electrode 111 GaN layer 112 AlGaN layer 118 source electrode 119 drain electrode 120 Schottky gate H hetero interface W potential well

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 4M104 AA04 BB05 BB14 CC01 DD34                       FF31 GG12 HH15                 5F045 AA04 AB14 AB17 AF04 AF05                       AF09 BB16 CA06 CA07 CB10                       DA52 DA63                 5F102 FA03 GB01 GC01 GD01 GJ02                       GJ10 GK04 GL04 GM04 GM07                       GM08 GM10 GQ01 GR03 GR10                       GR15 GT03 HC01 HC15 HC19

Claims (7)

[Claims] 1. A first nitride semiconductor layer, and a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a bandgap larger than that of the first nitride semiconductor layer. And an electrode provided on the second nitride semiconductor layer, wherein the second nitride semiconductor layer is caused by a difference in lattice constant between the second nitride semiconductor layer and the first nitride semiconductor layer. A semiconductor device having the above-mentioned lattice strain and reducing the contact resistance of the electrode by tunneling electrons accumulated in the vicinity of the hetero interface of the first nitride semiconductor layer to the electrode. 2. A first nitride semiconductor layer having a wurtzite structure, a first nitride semiconductor layer provided on the first nitride semiconductor layer, having a lattice constant different from that of the first nitride semiconductor layer. A second nitride semiconductor layer having a large bandgap and not undergoing lattice relaxation; and an electrode provided on the second nitride semiconductor layer, the second nitride semiconductor layer Is characterized in that the contact resistance of the n-side electrode is reduced by a tunnel current component of electrons accumulated near the hetero interface of the first nitride semiconductor layer to the electrode. Semiconductor device. 3. A first nitride semiconductor layer having a wurtzite structure, and a lattice constant different from that of the first nitride semiconductor layer, which is provided on the first nitride semiconductor layer. A second nitride semiconductor layer having a larger band gap and not undergoing lattice relaxation; a source electrode and a drain electrode provided on the second nitride semiconductor layer; and the second nitride A Schottky gate electrode provided on the semiconductor layer, wherein the layer thickness of the second nitride semiconductor layer is the source of electrons accumulated in the vicinity of the hetero interface of the first nitride semiconductor layer. A semiconductor device characterized in that the contact resistance of the source electrode and the drain electrode is reduced by a tunnel current component to the electrode and the drain electrode. 4. A first nitride semiconductor layer having a wurtzite structure, and a lattice constant which is selectively provided on the first nitride semiconductor layer and which has a lattice constant with the first nitride semiconductor layer. Second, with a larger bandgap and no lattice relaxation
A nitride semiconductor layer, a third nitride semiconductor layer selectively provided on the first nitride semiconductor layer, and having a bandgap larger than that of the first nitride semiconductor layer; A source electrode and a drain electrode provided on the second nitride semiconductor layer; and a Schottky gate electrode provided on the third nitride semiconductor layer, the second nitride semiconductor layer The layer thickness is such that the contact resistance of the source electrode and the drain electrode is reduced by the tunnel current component of the electrons accumulated near the hetero interface of the first nitride semiconductor layer to the source electrode and the drain electrode. A semiconductor device characterized by being provided. 5. The layer thickness of the second nitride semiconductor layer is 6 n.
The semiconductor device according to claim 1, wherein the semiconductor device has a thickness of m or less. 6. The surface of the first nitride semiconductor layer on which the second nitride semiconductor layer is laminated is a group III element plane, and the surface of the first nitride semiconductor layer is a group III element surface. The semiconductor device described. 7. The first nitride semiconductor layer is made of GaN, and the second nitride semiconductor layer is made of AlGaN, according to any one of claims 1 to 6. Semiconductor device.