JP2000010652A - Frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency synthesizer capable of switching oscillation frequency into target frequency without causing any overshoot. SOLUTION: The output frequency of a frequency synthesizer is switched according to a set value switching signal of a frequency division ratio switching part 6. First and second VCO 8 and 9 input an error signal from a phase comparator 3, and generates an oscillation output proportional thereto. At the time of switching the output frequency due to the change of the set value, the first VCO 8 obtains the holding voltage of a first voltage holding circuit 12, by the operation of switches 10 and 13, then the number of the oscillation outputs before switching is kept and selected by a selector 7 to obtain a clock output 16. The oscillation output of the second VCO 9 is supplied to a second program divider 4 by the selector 7 so that a loop can be formed of the second VCO 9, and the oscillation output of the second VCO 9 can be changed. When it is judged that the output frequency of the second VCO 9 is stabilized by a lock detector 17, the output of the second VCO 9 is obtained as the clock output 16 by the selector 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a frequency synthesizer using a phase locked loop (PLL).

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a configuration of a conventional frequency synthesizer. The reference oscillator 101 is
A reference frequency signal (Fref) is output. The first program divider 102 receives the reference frequency signal and performs 1 / M frequency division processing. The phase comparator (PC) 103
The frequency division output of the first program divider 102 and the frequency division output of the second program divider 104 are input, and an error signal based on the frequency difference and the phase difference is output. The low-pass filter 105 gives the error signal from the phase comparator 103 to a voltage-controlled oscillator (VCO) 106 after removing its high-frequency noise component. The voltage controlled oscillator 106
For example, it is constituted by a ring oscillator, and oscillates at a frequency proportional to the voltage of the error signal. The oscillation output of the voltage controlled oscillator 106 is taken out as a clock output 107 to the outside. Also, this voltage controlled oscillator 1
The oscillation output 06 is fed back to the phase comparator 103 after being subjected to 1 / N frequency division processing by the second program divider 104. First program divider 102
The second program divider 104 takes arbitrary values as M and N according to the switching signal from the frequency division ratio switching unit 108. M and N are changed (M ₀ → M ₁ , N
₀ → N ₁ ), the frequency synthesizer shifts from the locked state at a certain frequency f ₀ to the output state at a higher frequency f ₁ .

[0003]

However [0005] In the conventional frequency synthesizer above, when transitioning from a locked state of a certain frequency f ₀ to the output state of the even higher frequencies f _1, as shown by dotted lines in FIG. 3 It shows a transient characteristic.
That is, temporarily about 20% f ₁ is the target frequency 30
% Overshoot phenomenon frequency f ₂ is generated across occurs. When such an overshoot occurs, in the oscillation output of the frequency synthesizer in a semiconductor integrated circuit and a system for the clock source, the clock frequency f ₂ does not catch up circuit operation, which may cause malfunction.

An object of the present invention is to provide a frequency synthesizer capable of switching an oscillation frequency to a target frequency without causing overshoot in view of the above circumstances.

[0005]

In order to solve the above-mentioned problems, a frequency synthesizer according to the present invention is arranged such that the output frequency is adjusted based on an error signal proportional to a difference between a reference frequency and a feedback output frequency. A frequency synthesizer configured to switch the output frequency by changing the set value, comprising two voltage-controlled oscillators each generating an output frequency based on the error signal; At the time of switching, the output frequency at the time of the change of the set value in one of the voltage controlled oscillators is maintained and selected, and when the output frequency after the change of the set value in the other voltage controlled oscillator becomes stable, The output frequency is selected.

With the above configuration, two voltage controlled oscillators are provided, and one of the voltage controlled oscillators maintains the output frequency after the set value is changed, and the other voltage controlled oscillator stabilizes the output frequency after the set value is changed. Then, because the output frequency of the other voltage-controlled oscillator is selected and output,
The oscillation frequency can be switched to the target frequency without causing overshoot.

In the frequency synthesizer according to the present invention, the output frequency is adjusted based on an error signal proportional to a difference between a reference frequency and a feedback output frequency, and the output frequency is switched by changing a set value. In a frequency synthesizer configured to be able to be set, setting value changing means for changing the set value,
Two voltage-controlled oscillators each generating an output frequency based on the error signal, two voltage holding circuits for holding the error signal given to each voltage-controlled oscillator, and any one of output frequencies of the two voltage-controlled oscillators Selection means for selecting the clock output and feedback, respectively, switching means for activating a voltage holding circuit in the voltage-controlled oscillator selected when the set value is changed by the set value change means, and Determining means for determining whether or not the output frequency of the other voltage controlled oscillator has stabilized after the change of the set value; and one of the voltage controlled oscillators operated by the voltage holding circuit when the set value is changed by the set value changing means Is used for clock output while the output of the other voltage controlled oscillator is used for feedback. When it is, it is characterized in that and a control means for selecting the output frequency of the other of the voltage controlled oscillator as a clock output.

With the above configuration, two voltage controlled oscillators are provided, and one of the voltage controlled oscillators maintains the output frequency after the set value is changed, and the other voltage controlled oscillator stabilizes the output frequency after the set value is changed. Then, because the output frequency of the other voltage-controlled oscillator is selected and output,
The oscillation frequency can be switched to the target frequency without causing overshoot.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a frequency synthesizer according to this embodiment. Reference oscillator 1
Outputs a reference frequency signal (Fref). The first program divider 2 receives the reference frequency signal and performs 1 / M frequency division processing. The phase comparator (PC) 3
The divided output of the program divider 2 and the divided output of the second program divider 4 are input, and an error signal based on the frequency difference and the phase difference is output. Low-pass filter 5
Removes the high-frequency noise component from the error signal from the phase comparator 3 and supplies the error signal to first and second voltage controlled oscillators (VCOs) 8 and 9 via first and second switches 10 and 13, respectively. The first and second voltage controlled oscillators 8 and 9 oscillate at a frequency proportional to the voltage of the error signal.

The oscillation outputs of the first and second voltage controlled oscillators 8 and 9 are applied to a selector 7 where only one of them is selected and taken out as a clock output 16 to the outside. The content of the selection process in the selector 7 will be described later. The selected oscillation output is fed back to the phase comparator 3 after being subjected to 1 / N frequency division processing by the second program divider 4. The first program divider 2 and the second program divider 4 take arbitrary values as M and N according to a switching signal from the frequency division ratio switching unit 6.
By switching between M and N (M ₀ → M ₁ , N ₀ → N ₁ ), the frequency synthesizer shifts from a locked state of a certain frequency f ₀ to an output state of a higher frequency f _1. Will be migrated.

The lock detector 17 detects whether the oscillation output has reached a target frequency. That is, the lock detector 1
Reference numeral 7 detects the width of the pulse output from the phase comparator 3, and determines that the lock has occurred when the width of this pulse becomes equal to or less than a predetermined width.

The first voltage holding circuit 12 is connected to a signal line connected from the low-pass filter 5 to the input terminal of the first voltage controlled oscillator 8 via a third switch 11.
When the switch 11 is in the ON state, the voltage value of the error signal from the low-pass filter 5 is held.
After the FF, the holding voltage value is given to the first voltage controlled oscillator 8 via the third switch 11. The second voltage holding circuit 15 is connected to a signal line connected from the low-pass filter 5 to the input terminal of the second voltage controlled oscillator 9 via a fourth switch 14, and when the fourth switch 14 is ON. And the voltage value of the error signal from the low-pass filter 5 is held, and after the second switch 13 is turned off, the above-mentioned held voltage value is given to the second voltage / voltage controlled oscillator 9 via the fourth switch 14.

The first switch 10 and the third switch 11 are
It is configured to operate as follows. That is, when the switching signal is output from the frequency division ratio switching unit 6 when the oscillation output of the first voltage controlled oscillator 8 is selected,
The third switch 11 is turned on, and then the first switch 10
Turns off. Then, the oscillation output of the second voltage controlled oscillator 9 which is not selected is locked (reached the target frequency).
Is received from the lock detector 17, the third switch 11 is turned off and the first switch 10 is turned on.

The second switch 13 and the fourth switch 14 are
It is configured to operate as follows. That is, when a switching signal is output from the frequency division ratio switching unit 6 when the oscillation output of the second voltage controlled oscillator 9 is selected,
The fourth switch 14 is turned on, and then the second switch 13
Turns off. Then, the oscillation output of the unselected first voltage controlled oscillator 8 is locked (reached the target frequency).
Is received from the lock detector 17, the fourth switch 14 is turned off and the second switch 13 is turned on.

The selector 7 performs the first, second and third switching operations based on the output of the lock detector 17 and the switching signal of the frequency division ratio switching unit 6.
A process of selecting one of the voltage controlled oscillators 8 and 9 as the clock output 16 and a process of selecting one of the first and second voltage controlled oscillators 8 and 9 and 2 A process for supplying the program divider 4 (selection of the voltage controlled oscillator constituting the PLL) is performed.

Next, the operation of the frequency synthesizer will be described focusing on the operation of the selector 7 and the operations of the switches 10, 11, 13, and 14. First, it is assumed that, as an initial state, the oscillation output of the first voltage controlled oscillator 8 is selected as the clock output 16 and the oscillation output is similarly supplied to the second program divider 4. In this state, the first switch 10 is ON, the third switch 11 is OFF, the second switch 13 is ON, and the fourth switch 14 is OFF. Thereafter, when a switching signal is output from the frequency division ratio switching unit 6, the first program divider 2 and the second program divider 4 take predetermined values as M and N, and the M and N are switched and changed. As a result (see FIG. 2A), the frequency synthesizer shifts from the locked state of the frequency f ₀ to the output state of the higher frequency f ₁ .

Here, the third switch 11 is turned on by a switching signal from the frequency division ratio switching unit 6 to turn on the low-pass filter 5.
The potential of the error signal from the first voltage holding circuit 12 is held in the first voltage holding circuit 12, and the first switch 10 is turned off, whereby the holding potential of the first voltage holding circuit 12 is changed to the first voltage controlled oscillator 8.
(See “valid” in FIG. 2E). Further, the selector 7 keeps the oscillation output of the first voltage controlled oscillator 8 at the clock output 1 even after receiving the switching signal from the frequency division ratio switching unit 6.
6 is maintained (see FIG. 2D), but the oscillation output of the second voltage controlled oscillator 9 is selectively applied to the second program divider 4. That is, the first voltage-controlled oscillator 9 is used as the clock output 16, but the loop is constituted by the second voltage-controlled oscillator 9 (FIG. 2).
(B)).

The loop (PL) of the second voltage controlled oscillator 9
L II), the pulse width output from the phase comparator 3 increases instantaneously, and the second voltage-controlled oscillator 9
, The pulse width of the phase comparator 3 becomes smaller. When the width of this pulse becomes equal to or less than the predetermined width, the lock detector 17 outputs a lock detection signal.

Upon receiving the lock detection signal, the selector 7 outputs the oscillation output of the second voltage controlled oscillator 9 to the clock output 1.
Select as 6. In addition, the first lock detection signal causes the first
The switch 10 turns on, and the third switch 11 turns off.

The thick solid line in FIG. 3 is a graph showing a change in the frequency of the clock output 16 in the frequency synthesizer having the above configuration. For comparison, a clock output of a frequency synthesizer having a conventional structure is shown by a dotted line. As is clear from this graph, with the frequency synthesizer of this configuration, the oscillation frequency can be switched to the target frequency without causing overshoot.

Further, two voltage controlled oscillators 8 and 9, a selector 7, and voltage holding circuits 12 and 15 are required as compared with the conventional circuit, but the circuit scale is larger than when two sets of phase locked loop circuits are provided. Is small.

[0023]

As described above, according to the present invention, the frequency of the oscillation output can be switched to the target frequency without causing the frequency overshoot, so that the semiconductor integrated circuit using the oscillation output as a clock source And the system can be operated stably.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a frequency synthesizer according to an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the frequency synthesizer according to the embodiment of the present invention;

FIG. 3 is a graph showing the oscillation output of a frequency synthesizer according to an embodiment of the present invention, and showing the oscillation output of a conventional frequency synthesizer for comparison.

FIG. 4 is a block diagram showing a configuration of a conventional frequency synthesizer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reference oscillator 2 1st program divider 3 Phase comparator 4 2nd program divider 5 Low pass filter 6 Division ratio switching part 7 Selector 8 1st voltage controlled oscillator 9 2nd voltage controlled oscillator 10 1st switch 11 3rd switch 12th 1 voltage holding circuit 13 second switch 14 fourth switch 15 second voltage holding circuit 16 clock output 17 lock detector

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B079 BA03 BB04 BC10 CC20 DD02 DD20 5J004 BB03 CC01 CC09 DD14 DD20 DD21 5J060 AA04 BB01 BB03 CC01 CC19 CC20 CC41 CC53 DD09 DD33 FF09 GG01 HH02 KK03

Claims (2)

[Claims] 1. A frequency synthesizer wherein the output frequency is adjusted based on an error signal proportional to a difference between a reference frequency and a feedback output frequency, and the output frequency is switched by changing a set value. Comprises two voltage-controlled oscillators each generating an output frequency based on the error signal,
When the output frequency is switched by changing the set value, the output frequency at the time of the change of the set value in one of the voltage controlled oscillators is maintained and selected and output. A frequency synthesizer configured to select and output the output frequency of the other voltage-controlled oscillator when stabilized. 2. A frequency synthesizer configured to adjust the output frequency based on an error signal proportional to a difference between a reference frequency and a feedback output frequency, and to switch the output frequency by changing a set value. A set value changing means for changing the set value, two voltage controlled oscillators each generating an output frequency based on the error signal, and two voltage holding means for holding the error signal given to each voltage controlled oscillator A circuit, selecting means for selecting one of the output frequencies of the two voltage controlled oscillators for clock output and feedback, and voltage holding in the voltage controlled oscillator selected when the set value changing means changes the set value. Switching means for operating the circuit, and the other power supply after the set value is changed by the set value changing means. Determining means for determining whether or not the output frequency of the voltage-controlled oscillator is stabilized; and outputting the output of one of the voltage-controlled oscillators operated by the voltage holding circuit when the set value is changed by the set value changing means to a clock output. And control means for selecting the output frequency of the other voltage controlled oscillator for clock output when the stability is determined by the determination means. A frequency synthesizer characterized by the following.