JP2000068829A - Frequency synthesizer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress interference between PLL frequency synthesizers by minimizing occurrence of a frequency change such as frequency fluctuation in a PLL frequency synthesizer of other system due to a frequency change in a PLL frequency synthesizer of a system in the frequency synthesizer circuit having a plurality of PLL frequency synthesizers. SOLUTION: A frequency change detection section 11 detects a change in a lock frequency of a 1st PLL frequency synthesizer and controls a charge pump 4B of a 2nd PLL frequency synthesizer so as to make an output of the charge pump constant based on the detection and so as to make an input to an LPF 5b of a next stage constant. In the case that a lock frequency of the 1st PLL frequency synthesizer is changed, it is suppressed that fluctuation in a lock frequency of the 2nd PLL frequency synthesizer receiving its interference thereby.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a frequency synthesizer circuit, and more particularly to a technique for preventing mutual interference between two or more PLL frequency synthesizers.

[0002]

2. Description of the Related Art FIG. 16 is a block diagram showing a configuration of a dual frequency synthesizer circuit having two general PLL frequency synthesizers. This dual frequency synthesizer circuit includes a first prescaler 1A, a first program divider 2A, a first phase comparator 3A, a first charge pump 4A, a first low-pass filter (hereinafter, referred to as LPF) 5A, A first PLL frequency synthesizer comprising one voltage-controlled oscillator (hereinafter referred to as VCO) 6A, a second prescaler 1B, a second program divider 2B, a second phase comparator 3B, a second
A second PLL frequency synthesizer including a charge pump 4B, a second LPF 5B and a second VCO 6B, a reference oscillation circuit including an oscillation circuit (hereinafter, referred to as OSC) 8 and an oscillator 9 such as a crystal, OSC program divider 7A, second OSC program divider 7B, and data input unit 10.

A first OSC program divider 7A
Generates a comparison signal having a desired frequency by dividing the oscillation frequency of the reference oscillation circuit, and outputs the comparison signal to the phase comparator 3A of the first PLL frequency synthesizer.

A second OSC program divider 7B
Generates a comparison signal having a desired frequency by dividing the oscillation frequency of the reference oscillation circuit, and outputs the comparison signal to the phase comparator 3B of the second PLL frequency synthesizer.

[0005] Data for turning on or off each PLL frequency synthesizer and frequency setting data, that is, frequency division number data, are externally input to a data input section 10. The data input unit 10 inputs the input data into the first PLL frequency synthesizer program divider 2A, the second PLL frequency synthesizer program divider 2B, the first OSC program divider 7A, and the second OSC program divider. 7
Transfer to B.

In the first PLL frequency synthesizer, the oscillation output of the first VCO 6A is frequency-divided by the first prescaler 1A and the first program divider 2A,
The frequency-divided signal (hereinafter, referred to as a VCO frequency-divided output signal) is input to the first phase comparator 3A. First phase comparator 3
At A, the phase of the VCO frequency-divided output signal is compared with the phase of the comparison signal sent from the first OSC program divider 7A, and the output of the first charge pump 4A is obtained based on the comparison result. . The charge pump output is integrated in the first LPF 5A and converted into a DC voltage.

This DC voltage is a control voltage for controlling the oscillation frequency of the first VCO 6A, and the oscillation frequency of the first VCO 6A is controlled by changing this voltage. With such a feedback loop, the frequency of the output signal of the first PLL frequency synthesizer is set (locked) to a desired frequency. 2nd P
The same applies to the operation of the LL frequency synthesizer. FIG.
7 shows waveforms of the comparison signal, the VCO frequency-divided output signal, and the charge pump output when the PLL frequency synthesizer is locked.

[0008]

However, in the conventional dual frequency synthesizer circuit, the first and second
When the PLL frequency synthesizer is locked at a predetermined frequency, for example, the lock frequency (hereinafter referred to as a lock frequency) is changed only for the first PLL frequency synthesizer. As a result, there is a problem that the lock frequency of the other PLL frequency synthesizer is changed.

That is, when data for changing the output frequency of the first PLL frequency synthesizer from f1 to f2 is input to the data input unit 10, the first charge pump 4A
An output signal corresponding to the frequency change is derived as a current signal or a voltage signal according to the output form of the charge pump. The derived signal gives interference to the second PLL frequency synthesizer via a power supply line or the like,
For example, the lock frequency f of the second PLL frequency synthesizer is changed.

As the width of the frequency change of the first PLL frequency synthesizer increases, the first charge pump 4A
, The degree of interference with the second PLL frequency synthesizer also increases. In FIG.
VCO of second PLL frequency synthesizer caused by frequency change of first PLL frequency synthesizer
7 shows how the frequency-divided output signal and the charge pump output change.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. In a frequency synthesizer circuit having a plurality of PLL frequency synthesizers, a PLL system of another system is changed due to a frequency change of a PLL frequency synthesizer of one system.
It is an object of the present invention to obtain a frequency synthesizer circuit capable of suppressing mutual interference between PLL frequency synthesizers by minimizing occurrence of a frequency change such as frequency fluctuation in the L frequency synthesizer.

[0012]

In order to achieve the above object, the present invention provides at least two systems of PLL frequency synthesizers and a data input unit for receiving data for setting output signal frequencies of the respective PLL frequency synthesizers. When a change occurs in the lock frequency of any of the PLL frequency synthesizers due to the data input to the data input unit, the start of the change or the start of the change is detected, and based on the detection result, Frequency change detecting means for suppressing a change in lock frequency of at least one other PLL frequency synthesizer.

According to the present invention, the frequency change detecting means detects a change in the lock frequency of one of the PLL frequency synthesizers and suppresses a change in the lock frequency of another PLL frequency synthesizer based on the detected change. Perform control.

In the present invention, the frequency change detecting means starts or changes the lock frequency of any one of the PLL frequency synthesizers based on the phase comparison result output from the phase comparator of each PLL frequency synthesizer. Has started, and the LPF of at least one other PLL frequency synthesizer is
May be controlled so that the input of the input is constant.

According to the present invention, the frequency change detecting means detects any one of the PLs based on the phase comparison result of the phase comparator.
Detecting a change in the lock frequency of the L frequency synthesizer,
LPF of other PLL frequency synthesizer based on it
Is controlled so that the input of is constant.

Alternatively, the frequency change detecting means includes P
Data for changing the lock frequency of the LL frequency synthesizer is input, and based on the input data, any one of
A change in the lock frequency of the LL frequency synthesizer is detected to be started, or the start of the change is detected, and control is performed based on the detected change so that the input of the LPF of at least one other PLL frequency synthesizer is constant. You may.

According to the present invention, the frequency change detecting means detects that the lock frequency of any one of the PLL frequency synthesizers has changed based on the frequency change data externally input to the data input unit, and based on the change, The control is performed so that the input of the LPF of another PLL frequency synthesizer becomes constant.

Further, in the present invention, the frequency change detecting means detects a change width of a lock frequency of any one of the PLL frequency synthesizers, and based on the detection result, controls the LPF so that an input to the LPF becomes constant. May be provided with a charge pump for correcting the input to.

According to the present invention, the frequency change detecting means detects a change in the lock frequency of one of the PLL frequency synthesizers, and the input of the LPF of the other PLL frequency synthesizer is kept constant by the charge pump for frequency correction based on the detected change. Is controlled so that

In the present invention, three or more PLL frequency synthesizers may be provided.

According to the present invention, even in a frequency synthesizer circuit having three or more PLL frequency synthesizers, when the lock frequency of any one of the PLL frequency synthesizers changes, the lock frequency of another system is affected by the interference. P
Variations in the lock frequency of the LL frequency synthesizer can be suppressed.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.
In a dual frequency synthesizer circuit having an LL frequency synthesizer, a state in which the first and second PLL frequency synthesizers are locked at predetermined frequencies f1 and f2, respectively, is such that the lock frequency is f3 only for the first PLL frequency synthesizer. Will be described. Note that, for convenience of explanation, only the two systems are distinguished as a first system and a second system. The same applies to the case where the lock frequency is changed only for the second PLL frequency synthesizer. Is omitted.

Embodiment 1 FIG. 1 is a block diagram showing a configuration of the frequency synthesizer circuit according to Embodiment 1 of the present invention. In the first embodiment, when a change occurs in the lock frequency of one PLL frequency synthesizer in a general dual frequency synthesizer circuit (see FIG. 16), the change is detected, and the other is detected based on the detection result. P
A frequency change detecting unit 1 serving as frequency change detecting means for suppressing a change in a lock frequency of an LL frequency synthesizer.
1 is provided. For other configurations, see FIG.
Since it is the same as the general dual frequency synthesizer circuit shown in FIG.

The frequency change detecting section 11 detects the P
When the lock frequency of the LL frequency synthesizer is changed or when the lock frequency is changed, a signal whose state changes, for example, a signal of a phase comparison result of each of the phase comparators 3A and 3B of the first and second PLL frequency synthesizers. The system in which the lock frequency changes, that is, the first
Of the lock frequency of the PLL frequency synthesizer starts to change. The state of the output of the phase comparators 3A and 3B, that is, the signal based on the phase comparison result changes when the frequency of the signal to be compared changes.

Therefore, the outputs of the first and second phase comparators 3A and 3B are input to the frequency change detector 11.

Further, the frequency change detecting section 11 is provided with a first PL
In order to cancel interference such as frequency fluctuation that may occur with respect to the lock frequency f2 of the second PLL frequency synthesizer due to the change of the lock frequency of the L frequency synthesizer from f1 to f3, the second PLL frequency synthesizer is used. Is specially controlled so as not to fluctuate the output of the charge pump 4B.

Thus, in the second PLL frequency synthesizer, for example, the LP of the next stage of the charge pump 4B
The output voltage of F5B becomes constant, and the next stage VCO6
The oscillation frequency of B does not change and remains constant. A selection circuit for selecting whether or not to perform special control on the output of the charge pump may be provided.

Therefore, the frequency change detecting section 11 outputs a control signal to the first and second charge pumps 4A and 4B. Further, the frequency change detection unit 11 is independent of the signals input from the phase comparators 3A and 3B,
The outputs of the charge pumps 4A and 4B can be independently controlled on / off.

When detecting that both of the lock frequencies of the first and second PLL frequency synthesizers start to change, the frequency change detecting section 11 performs the above-described special control on each of the charge pumps 4A and 4B, that is, each of the above-mentioned special controls. Control is not performed so as not to fluctuate the charge pump output.

The frequency change detecting section 11 is a signal used for detecting that the lock frequency of the PLL frequency synthesizer of any system changes, for example, the phase comparator 3
A first PL based on the signals of the phase comparison results of A and 3B
The completion of the change of the lock frequency of the L frequency synthesizer is detected, and the special control for preventing the output of the charge pump 4B of the second PLL frequency synthesizer from fluctuating based on the detection result is ended. Then, the charge pump 4B performs a normal output.

FIG. 2 is a block diagram showing in detail an example of a mutual signal transmission path between the phase comparator 3B, the frequency change detector 11, the charge pump 4B and the LPF 5B in the second PLL frequency synthesizer. Note that the first P
Since the mutual signal transmission paths between the phase comparator 3A, the charge pump 4A and the LPF 5A of the LL frequency synthesizer and the LPF 5A and the frequency change detection unit 11 are also the same, the symbols in parentheses in FIG. Put it in.

The charge pump 4B (4A) is, for example, L
A DC current source 41 and a first transistor 42 acting to supply a current to the PF5B (5A);
It includes a DC current source 43 and a second transistor 44 that operate to extract current from B (5A). Note that the charge pump 4B (4A) shown in FIG. 2 is simplified.

The signal based on the result of the phase comparison output from the phase comparator 3B (3A) is input to the first transistor 42, and is also inverted by the inverter 45 and input to the second transistor 44. The signal output from the frequency change detection unit 11 is input to the first transistor 42 and is also input to the second transistor 44 after being delayed by the delay element 46.

That is, the signal output from the frequency change detector 11 is superimposed on the signal based on the phase comparison result output from the phase comparator 3B (3A) and input to the first transistor 42. The second transistor 44 includes:
The inverted signal of the signal output from the frequency change detection unit 11 is superimposed on the inverted signal of the signal based on the phase comparison result output from the phase comparator 3B (3A) and input.

The first and second LPFs 5A and 5B are general integrators, and convert a current supplied from a preceding charge pump into a DC voltage. FIG. 3 shows a typical L that can be used as the first and second LPFs 5A and 5B.
An example of a PF circuit is shown.

Next, the operation of the frequency synthesizer circuit will be described with reference to FIGS.

When both the first PLL frequency synthesizer and the second PLL frequency synthesizer are locked at their respective lock frequencies, data for changing the lock frequency of the first PLL frequency synthesizer is input to the data input unit 10. When input, the lock frequency of the first PLL frequency synthesizer begins to change. This causes interference to the second PLL frequency synthesizer,
The VCO divided output signal of the PLL frequency synthesizer starts to change.

If it is assumed that the above-mentioned special control by the frequency change detection unit 11 is not performed, the VCO frequency-divided output signal of the second PLL frequency synthesizer deviates from the frequency of the comparison signal (the second stage in FIG. 4). Therefore, the second phase comparator 3B should output a phase error signal like the waveform shown in the third stage in FIG.

However, actually, the frequency change detecting section 11
The pulse width t of the phase error signal input from the phase comparator 3A of the first PLL frequency synthesizer is detected (see FIG. 5), and if the pulse width is equal to or larger than a predetermined width (arbitrarily settable), A correction signal (waveform shown in the fourth stage in FIG. 4) having a waveform that cancels the phase error signal (waveform in the third stage in FIG. 4) that should be output from the second phase comparator 3B is charged in the second charge. Output to pump 4B.

As a result, as shown in the fourth row of FIG.
The output of the second charge pump 4B does not change and remains constant. That is, the second PLL frequency synthesizer does not need to be affected by the change in the lock frequency of the first PLL frequency synthesizer. At this time, the frequency change detection unit 11
Represents the correction signal having the waveform shown in the fourth row of FIG.
It is generated based on the pulse width t of the phase error signal input from the phase comparator 3A of the L frequency synthesizer.

Then, the frequency change detecting section 11 outputs the first P
When the pulse width of the phase error signal input from the phase comparator 3A of the LL frequency synthesizer becomes very narrow, it is determined that the change of the lock frequency of the first PLL frequency synthesizer is completed, and special control for the second charge pump 4B is performed. To end.

According to the first embodiment, the frequency change detecting section 11 detects a change in the lock frequency of the first PLL frequency synthesizer and, based on the change, detects a change in the lock frequency of the charge pump 4B of the second PLL frequency synthesizer. In order to control the charge pump output to be constant,
When the lock frequency of the first PLL frequency synthesizer changes, it is possible to prevent the lock frequency of the second PLL frequency synthesizer from fluctuating due to the interference.

Embodiment 2 FIG. 6 is a block diagram showing a configuration of the frequency synthesizer circuit according to Embodiment 2 of the present invention. The second embodiment is the same as the first embodiment described above.
The difference from the data input unit 10 is that the frequency change detection unit is replaced with a frequency change detection unit 11 that starts control based on the phase error signals input from the first and second phase comparators 3A and 3B. Is provided with a frequency change detection unit 21 that starts control based on data input from outside. Other configurations are the same as those in the first embodiment, and thus detailed description is omitted.

Therefore, the frequency change detecting section 21 receives data such as a frequency change from the data input section 10 and, based on the input data, changes the lock frequency of the first PLL frequency synthesizer and the change width thereof. Is detected (see FIG. 7). The larger the change width of the lock frequency of the first PLL frequency synthesizer is, the larger the change of the charge pump output of the system is, and thus the degree of interference with the second PLL frequency synthesizer is increased. Special control is performed so that the output of the charge pump 4B of the second PLL frequency synthesizer does not fluctuate according to the detected change width of the lock frequency.

Each output of the first and second phase comparators 3A and 3B is input to the frequency change detection unit 21, and the signals of the phase comparison results of the phase comparators 3A and 3B are output to the frequency change detection unit 21. Based on the detection result, it is detected that the change of the lock frequency of the first PLL frequency synthesizer is completed, and based on the detection result, the output of the charge pump 4B of the second PLL frequency synthesizer is not changed. The special control is terminated, and the charge pump 4B performs normal output.

The frequency change detecting section 21 detects that both the lock frequencies of the first and second PLL frequency synthesizers have changed based on the data such as the frequency change input from the data input section 10. Does not perform special control on each of the charge pumps 4A and 4B so as not to fluctuate the output of the charge pump.

Next, the operation of the frequency synthesizer circuit will be described with reference to FIG. When both the first PLL frequency synthesizer and the second PLL frequency synthesizer are locked at their respective lock frequencies, data for changing the lock frequency of the first PLL frequency synthesizer is input to the data input unit 10 from outside. Then, the lock frequency of the first PLL frequency synthesizer starts to change. As a result, the second PLL frequency synthesizer is interfered, and the VCO divided output signal of the second PLL frequency synthesizer starts to change.

At the same time, the frequency change data input to the data input unit 10 is also input to the frequency change detection unit 21. The frequency change detection unit 21 fetches the input data as shown in FIG. The lock frequency of the synthesizer is changed, and the change width is detected.

The frequency change detecting section 21 should output from the second phase comparator 3B if it is assumed that the special control by the frequency change detecting section 21 is not performed based on the detection result. A correction signal having a waveform that cancels the phase error signal (see the third stage in FIG. 4) (see the fourth stage in FIG. 4) is output to the second charge pump 4B. Thereby, the second charge pump 4
The output of B does not change and remains constant (see the waveform shown in the fifth row in FIG. 4). That is, the second PLL frequency synthesizer does not need to be affected by the change in the lock frequency of the first PLL frequency synthesizer.

Then, the frequency change detecting section 21 outputs the first P
When the pulse width of the phase error signal input from the phase comparator 3A of the LL frequency synthesizer becomes very narrow, it is determined that the change of the lock frequency of the first PLL frequency synthesizer is completed, and special control for the second charge pump 4B is performed. To end.

According to the second embodiment, frequency change detecting section 21 detects that the lock frequency of the first PLL frequency synthesizer changes based on frequency change data externally input to data input section 10. Then, based on the control, the charge pump 4B of the second PLL frequency synthesizer is controlled so that the output of the charge pump becomes constant. Therefore, when the lock frequency of the first PLL frequency synthesizer changes, the interference The second
Fluctuation of the lock frequency of the PLL frequency synthesizer can be suppressed.

Embodiment 3 FIG. FIG. 8 is a block diagram showing a configuration of the frequency synthesizer circuit according to Embodiment 3 of the present invention. The third embodiment is the same as the first embodiment described above.
What is different is that, as the frequency change detecting means, each PLL frequency synthesizer locks based on the phase comparison result of each of the phase comparators 3A and 3B of the first and second PLL frequency synthesizers instead of the frequency change detecting unit 11. A first lock detector 12A and a second lock detector 12B for detecting that the lock
A and 12B detect that the lock frequency of the PLL frequency synthesizer of one system changes, and the other PLL
The point is that control is performed so that the input of the LPF of the frequency synthesizer becomes constant. Other configurations are the same as those in the first embodiment, and thus detailed description is omitted.

The lock detector 12A of the third embodiment,
12B detects a change in the lock frequency of one of the systems based on the phase comparison results of the first and second phase comparators 3A and 3B, and based on that detects the input of the LPF of the other system to be constant. The first and second phase comparators 3A and 3A have a function.
It has a function of detecting a change in the lock frequency of one of the systems based on the phase comparison result of B, and keeping the output of the charge pump of the other system constant based on the change, thereby keeping the input of the LPF of the next stage constant. Therefore, the lock detection units 12A, 12
B shows that the frequency change detection unit 11 of the first embodiment is
It corresponds to a frequency synthesizer divided for each frequency synthesizer, and has substantially the same function as the frequency change detection unit 11.

The first lock detector 12A detects that the lock frequency of the second PLL frequency synthesizer changes based on the phase comparison result of the second phase comparator 3B, and detects the change in the lock frequency of the first PLL frequency synthesizer. Control is performed so that the input of the LPF 5A becomes constant. This prevents the first PLL frequency synthesizer from being interfered by a change in the lock frequency of the second PLL frequency synthesizer.

The second lock detector 12B detects that the lock frequency of the first PLL frequency synthesizer changes based on the phase comparison result of the first phase comparator 3A, and detects the change of the second PLL frequency synthesizer. Control is performed so that the input of the LPF 5B becomes constant. This prevents the second PLL frequency synthesizer from being interfered by a change in the lock frequency of the first PLL frequency synthesizer.

Further, the first lock detecting section 12A determines that the lock frequencies of the first and second PLL frequency synthesizers both change based on the respective phase comparison results of the first and second phase comparators 3A and 3B. If is detected,
The LPF 5A is not controlled so that its input becomes constant. The same applies to the second lock detection unit 12B.

The first lock detector 12A outputs a very narrow pulse signal output from the phase comparator 3B of the second PLL frequency synthesizer when the change of the lock frequency of the second PLL frequency synthesizer is completed. Is detected, the completion of the change of the lock frequency of the second PLL frequency synthesizer is detected, and the LPF 5A of the first PLL frequency synthesizer is detected based on the detection result.
The special control for making the input of the constant is terminated. The same applies to the second lock detection unit 12B.

In this embodiment, a selection circuit is provided for selecting whether or not the first and second lock detecting sections 12A, 12B perform a special control for keeping the inputs of the LPFs 5A, 5B constant. Is also good.

FIG. 9 is a block diagram showing in detail an example of the second lock detector 12B and its peripheral parts. Note that the configuration of the first lock detection unit 12A and its peripheral parts is also the same, so that this is indicated by the reference numerals in parentheses in FIG. 9 and the following description.

The lock detector 12B (12A) is provided with each of the phase comparators 3 of the first and second PLL frequency synthesizers.
A, 3B, a phase comparison result detector 121 for detecting a phase comparison result, and an LPF based on the detection result.
5B (5A) is provided with a constant current supply circuit 122 for flowing a direct current. In the constant current supply circuit 122, the lock frequency of the first PLL frequency synthesizer (the second PLL frequency synthesizer for the lock detection unit 12A) does not change in the phase comparison result detection unit 121, or the second PLL frequency synthesizer (Lock detector 12
A is turned off when it is detected that the lock frequency of the first PLL frequency synthesizer (A) changes, that is, the flow of DC current to the LPF 5B (5A) is stopped.

The constant current supply circuit 122 includes a first PL
When it is detected that the lock frequency of the L frequency synthesizer (the second PLL frequency synthesizer for the lock detection unit 12A) has changed, it is turned on, and the LPF 5B (5
A direct current is passed through A).

At this time, the larger the change width of the lock frequency, the larger the comparison width for changing the current frequency and the frequency, and the larger the output pulse width of the phase comparator of the PLL frequency synthesizer in which the lock frequency changes. The phase comparison result detection unit 121 detects the output pulse width of the phase comparator, and controls the constant current supply circuit 122 to supply a current having a magnitude corresponding to the change width of the frequency based on the detected pulse width.

FIG. 11 is a circuit diagram showing a specific example of the first and second lock detectors 12A and 12B. In the illustrated example, the constant current supply circuit 122 is, for example, an LPF 5B (5A).
And a charge pump provided with a DC current source 125 and a second transistor 126 that function to extract current from the LPF 5B (5A), and a DC current source 123 that functions to supply current to the LPF 5B (5A). Have been. The signal output from the phase comparison result detection unit 121 is input to the first transistor 124 and is also input to the second transistor 126 after being delayed by the delay element 127.

Next, the operation of the frequency synthesizer circuit will be described with reference to FIG. First PLL
When data for changing the lock frequency of the first PLL frequency synthesizer is input to the data input unit 10 when both the frequency synthesizer and the second PLL frequency synthesizer are locked at their respective lock frequencies, the first The lock frequency of the PLL frequency synthesizer starts to change. As a result, the second PLL frequency synthesizer is interfered, and the VCO divided output signal of the second PLL frequency synthesizer starts to change. And the charge pump 4 of the second PLL frequency synthesizer
The output of B changes (the first waveform in FIG. 12).

At this time, the second lock detecting unit 12B
Based on the phase error signal input from the phase comparator 3A of the PLL frequency synthesizer, a signal (the second-stage waveform in FIG. 12) that cancels the output change of the second charge pump 4B is converted to the second PLL frequency. Synthesizer LPF5
Output to B. As a result, the input of the LPF 5B becomes constant (the third waveform in FIG. 12). That is, the second PL
The L frequency synthesizer does not suffer from interference due to a change in the lock frequency of the first PLL frequency synthesizer.

Then, the second lock detecting section 12 B
When a very narrow pulse is input from the phase comparator 3A of the PLL frequency synthesizer, it is determined that the lock frequency of the first PLL frequency synthesizer has been changed.
The current supply or extraction to the second LPF 5B is terminated.

According to the third embodiment, the second lock detector 12B detects a change in the lock frequency of the first PLL frequency synthesizer, and based on the change, detects the change in the second PLL.
Since control is performed such that the input of the LPF 5B of the L frequency synthesizer is constant, when the lock frequency of the first PLL frequency synthesizer changes, the lock frequency of the second PLL frequency synthesizer fluctuates due to the interference. Can be suppressed.

Embodiment 4 FIG. 13 is a block diagram showing a configuration of the frequency synthesizer circuit according to Embodiment 4 of the present invention. In the fourth embodiment, the charge pumps in the lock detectors 12A and 12B having the configuration shown in FIG. 11 are independently provided outside the lock pump, and therefore, are substantially the same as the third embodiment.

The frequency change detecting means detects the lock of each PLL frequency synthesizer based on the phase comparison result of each of the phase comparators 3A and 3B of the first and second PLL frequency synthesizers. Detector 14
A and the second lock detector 14B, and the lock detector 1
4A, a first frequency correction charge pump 13A for controlling the input of the LPF 5A of the first PLL frequency synthesizer to be constant when detecting that the lock frequency of the second PLL frequency synthesizer changes; When the lock detector 14B detects that the lock frequency of the first PLL frequency synthesizer has changed, the second P
A second frequency correction charge pump 13B that controls the input of the LPF 5B of the LL frequency synthesizer to be constant. The other configuration is the same as that of the third embodiment, and thus the detailed description is omitted.

The first lock detector 14A detects that both the lock frequencies of the first and second PLL frequency synthesizers change based on the respective phase comparison results of the first and second phase comparators 3A and 3B. If detected, the first
Is not performed by the frequency correction charge pump 13A, that is, the control to keep the input of the LPF 5A constant. The same applies to the second lock detection unit 14B.

The first lock detector 14A outputs a very narrow pulse signal output from the phase comparator 3B of the second PLL frequency synthesizer when the change of the lock frequency of the second PLL frequency synthesizer is completed. Is detected, the completion of the change of the lock frequency of the second PLL frequency synthesizer is detected, and the control by the first frequency correction charge pump 13A is terminated based on the detection result. The same applies to the second lock detection unit 14B.

In this example, the first and second lock detecting units 14A and 14B are provided with the frequency correcting charge pump 1
A selection circuit may be provided for selecting whether or not to perform special control to keep the inputs of the LPFs 5A and 5B constant by the 3A and 13B.

FIG. 14 is a block diagram showing in detail an example of the second lock detector 14B, the second charge pump 13B for frequency correction and its peripheral parts. Note that the first lock detection unit 14A, the first frequency correction charge pump 13A, and their peripheral parts have the same configuration.
This is shown in FIG. 14 and the following description with reference numerals in parentheses.

The lock detector 14B (14A) is provided with each phase comparator 3 of the first and second PLL frequency synthesizers.
A phase comparison result detector 141 for detecting the phase comparison results output from A and 3B, a frequency correction charge pump control circuit 142 for controlling the frequency correction charge pump 13B (13A) based on the detection results, It has.

The frequency correction charge pump 13B (13
A) includes, for example, a DC current source 131 and a first transistor 132 that operate to supply a current to the LPF 5B (5A), and a DC current source 133 and a second transistor that operate to extract a current from the LPF 5B (5A). The transistor 134 is provided. The signal output from the frequency correction charge pump control circuit 142 is input to the first transistor 132 and is also delayed by the delay element 135 and input to the second transistor 134.

Next, the operation of the frequency synthesizer circuit will be described. When both the first PLL frequency synthesizer and the second PLL frequency synthesizer are locked at the respective lock frequencies, the data input unit 1
When data for changing the lock frequency of the first PLL frequency synthesizer is input to 0, the lock frequency of the first PLL frequency synthesizer starts to change. As a result, the second PLL frequency synthesizer is interfered, and the VCO divided output signal of the second PLL frequency synthesizer starts to change. Then, the output of the charge pump 4B of the second PLL frequency synthesizer changes.

At this time, the second lock detecting section 14B
And outputs a control signal to the second frequency correction charge pump 13B based on the phase error signal input from the phase comparator 3A of the PLL frequency synthesizer. Pump 4
A signal that cancels the output change of B is output to the LPF 5B of the second PLL frequency synthesizer. Thereby, the input of the LPF 5B becomes constant. That is, the second PL
The L frequency synthesizer does not suffer from interference due to a change in the lock frequency of the first PLL frequency synthesizer.

Then, the second lock detecting section 14 B
When a very narrow pulse is input from the phase comparator 3A of the PLL frequency synthesizer, it is determined that the lock frequency of the first PLL frequency synthesizer has been changed.
The control for the second frequency correction charge pump 13B is terminated, whereby the supply or extraction of the current to the second LPF 5B is terminated.

According to the fourth embodiment, the second lock detector 14B detects a change in the lock frequency of the first PLL frequency synthesizer and controls the second frequency correction charge pump 13B based on the detected change. And the second frequency correcting charge pump 13B outputs a second PLL signal.
In order to control the input of the LPF 5B of the frequency synthesizer to be constant, when the lock frequency of the first PLL frequency synthesizer changes, the second PLL
Fluctuation of the lock frequency of the PLL frequency synthesizer can be suppressed.

Embodiment 5 FIG. 15 is a block diagram showing a configuration of the frequency synthesizer circuit according to Embodiment 5 of the present invention. In the fifth embodiment, for example, the frequency synthesizer circuit of the fourth embodiment is applied to a case where three or more PLL frequency synthesizers are provided. Each lock detector 14A, 14B,...
The phase comparators 3A, 3B,..., 3 of the L frequency synthesizer
The phase comparison result of n is input.

The frequency change of the system in which the lock frequency changes is detected by the lock detection unit 1 of the system in which the lock frequency does not change.
, 14n, and controls the output of the frequency correction charge pumps 13A, 13B, ..., 13n. In all systems, PL
When the lock frequency of the L frequency synthesizer changes, the charge pumps 13A, 13B,.
13n is not controlled. Lock detector 14A,
, 14n and the frequency correction charge pumps 13A, 13B,..., 13n are the same as in the above-described fourth embodiment, and will not be described.

According to the fifth embodiment described above, even in a frequency synthesizer circuit having three or more PLL frequency synthesizers, when the lock frequency of any one of the PLL frequency synthesizers changes, it receives the interference and receives another signal. The fluctuation of the lock frequency of the PLL frequency synthesizer of the system can be suppressed.

In the above, the present invention is not limited to the above embodiments, but can be variously modified. For example, in the fourth embodiment and the fifth embodiment, the fact that the lock frequency of the PLL frequency synthesizer of any system is changed is notified from the data input unit 10 to which data such as frequency change is input as in the second embodiment. May be detected based on the input data.

[0084]

As described above, according to the present invention, according to the present invention, the frequency change detecting means detects a change in the lock frequency of one of the PLL frequency synthesizers, and the lock frequency of the other PLL frequency synthesizer is changed based on the detected change. In order to control so as not to change, any PL
When the lock frequency of the L frequency synthesizer changes,
It is possible to prevent the lock frequency of another PLL frequency synthesizer from fluctuating due to the interference.

Further, according to the present invention, the frequency change detecting means detects any one of P based on the phase comparison result of the phase comparator.
A change in the lock frequency of the LL frequency synthesizer is detected, and the L
Since the control is performed so that the input of the PF becomes constant, when the lock frequency of one of the PLL frequency synthesizers changes, the lock frequency of the other PLL frequency synthesizer is prevented from fluctuating due to the interference. can do.

Further, according to the present invention, the frequency change detecting means detects that the lock frequency of any one of the PLL frequency synthesizers changes based on the frequency change data externally input to the data input section, In order to control the input of the LPF of another PLL frequency synthesizer to be constant on the basis of the above, when the lock frequency of any one of the PLL frequency synthesizers changes, the lock frequency of the other PLL frequency synthesizer is affected by the interference. Can be suppressed from fluctuating.

Further, according to the present invention, the frequency change detecting means detects a change in the lock frequency of any one of the PLL frequency synthesizers and, based on the change, detects the LPF of another PLL frequency synthesizer using the charge pump for frequency correction.
Control to keep the input of
When the lock frequency of the LL frequency synthesizer changes, it is possible to prevent the lock frequency of another PLL frequency synthesizer from fluctuating due to the interference.

According to the present invention, three or more PLs
Even in a frequency synthesizer circuit having an L frequency synthesizer, when the lock frequency of the PLL frequency synthesizer of any system changes, the lock frequency of the PLL frequency synthesizer of the other system changes due to the interference. Can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a frequency synthesizer circuit according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram showing an example of a mutual signal transmission path between a phase comparator, a frequency change detection unit, a charge pump, and an LPF of the frequency synthesizer circuit in detail.

FIG. 3 is a circuit diagram showing a circuit example of a general LPF.

FIG. 4 is a waveform chart for explaining an operation of the frequency synthesizer circuit according to the first embodiment;

FIG. 5 is a waveform chart for explaining an operation of the frequency synthesizer circuit according to the first embodiment.

FIG. 6 is a block diagram illustrating a configuration of a frequency synthesizer circuit according to a second embodiment of the present invention.

FIG. 7 is a timing chart for explaining the operation of the frequency synthesizer circuit according to the second embodiment;

FIG. 8 is a block diagram showing a configuration of a frequency synthesizer circuit according to a third embodiment of the present invention.

FIG. 9 is a block diagram showing in detail an example of a lock detection unit of the frequency synthesizer circuit and its peripheral portion.

FIG. 10 is a table for explaining the operation of the lock detection unit.

FIG. 11 is a circuit diagram showing a specific example of the lock detection unit.

FIG. 12 is a waveform chart for explaining an operation of the frequency synthesizer circuit according to the third embodiment;

FIG. 13 is a block diagram illustrating a configuration of a frequency synthesizer circuit according to a fourth embodiment of the present invention.

FIG. 14 is a block diagram showing in detail an example of a lock detection unit and a frequency correction charge pump of the frequency synthesizer circuit and peripheral parts thereof;

FIG. 15 is a block diagram illustrating a configuration of a frequency synthesizer circuit according to a fifth embodiment of the present invention.

FIG. 16 is a block diagram showing a configuration of a general dual frequency synthesizer circuit.

FIG. 17 is a waveform diagram of a comparison signal, a VCO frequency-divided output signal, and a charge pump output when the PLL frequency synthesizer is locked.

FIG. 18 is a waveform diagram showing a change in a VCO frequency-divided output signal and a charge pump output of the other PLL frequency synthesizer caused by a frequency change of one PLL frequency synthesizer.

[Explanation of symbols]

3A, 3B, 3n phase comparator, 5A, 5B, 5n L
PF, 10 data input section, 11, 21 frequency change detection section (frequency change detection means), 12A, 12B, 14
A, 14B, 14n Lock detecting section (frequency change detecting means), 13A, 13B, 13n Charge pump for frequency correction (frequency change detecting means).

Claims (5)

[Claims] 1. A PLL frequency synthesizer comprising at least two systems, a data input unit for receiving data for setting an output signal frequency of each of the PLL frequency synthesizers, and any one of P by data input to the data input unit.
When a change occurs in the locked output signal frequency of the LL frequency synthesizer, the change is detected to be started or that the change is started, and based on the detection result, the other at least one PLL frequency synthesizer is controlled. And a frequency change detecting means for suppressing a change in the locked output signal frequency. 2. The method according to claim 1, wherein said frequency change detecting means starts changing the frequency of a locked output signal of any one of the PLL frequency synthesizers based on a phase comparison result output from a phase comparator of each PLL frequency synthesizer. 2. The frequency synthesizer circuit according to claim 1, wherein the start of the change is detected, and control is performed on the basis of the change so that the input of the low-pass filter of at least one other PLL frequency synthesizer becomes constant. . 3. The frequency change detecting means receives data for changing the locked output signal frequency of the PLL frequency synthesizer, and based on the input data, the frequency change detecting means. Detects that the locked output signal frequency of any of the PLL frequency synthesizers has begun to change or that it has begun, and based on which the input of the low-pass filter of at least one other PLL frequency synthesizer is constant. 2. The control according to claim 1, wherein
The frequency synthesizer circuit according to 1. 4. The method according to claim 1, wherein the frequency change detecting means includes any one of P
A charge pump for detecting the change width of the locked output signal frequency of the LL frequency synthesizer and correcting the input to the low-pass filter based on the detection result so that the input to the low-pass filter becomes constant. The frequency synthesizer circuit according to claim 2 or 3, wherein the frequency synthesizer circuit has: 5. The frequency synthesizer circuit according to claim 1, wherein three or more PLL frequency synthesizers are provided.