GB2080003A - Dot matrix character printer and control system - Google Patents

Abstract

A dot matrix character printer is of the type having encoder means producing an encoder signal alternating between two states in response to incremental changes in print head position. Encoder signal filter means (Fig. 8 shows one) remove relatively short duration noise signals from the encoder signal to thereby provide a filtered encoder signal, by sampling the encoder signal a plurality of successive times and changing the state of the filtered encoder signal only when the encoder signal is in the same state for two successive sample times. <IMAGE>

Description

1

SPECIFICATION Dot matrix character printer and control system

GB 2 080 003 A 1 This invention relates to the field of character printers, particularly dot matrix printers which form characters as an array of dots at available locations. More specifically, this invention relates to a control system for such printers to permit the printing, at variable speeds, of characters having different pitch, 5 with the capability of printing characters of different pitch on the same line.

Dot matrix character printers are well known in the art, particularly for use as output devices for computers and other electronic devices. These printers are used to produce printed character output on a paper medium in response to receiving electronic signals which correspond to the characters of the available character sets. Individual characters are formed from an appropriate combination of dots 10 selected from an array of available dot locations. Generally, these dot locations are arranged in an n column by m-row matrix. A printing head contains a sol enoid-ope rated print rod for each location in the matrix. When the printing of a character requires that a dot be written in a particular location, the corresponding solenoid in the printing head is activated; this causes the associated printing rod to be flung (or "fired") in the direction of the paper (i.e., "target"). An inked printing ribbon is interposed 15 between the printing head and the paper. Thus, the fired printing rod impacts the ribbon and prints an impression of its end surface on the paper. The printing rod is actually a thin wire-shaped element with a flat end having a round cross section. It is this end which forms a dot on the paper.

Typically, the printing head of a dot matrix printer contains printing solenoids. These are assembled into close proximity with each other. The activation of these printing solenoids causes them 20 to heat up. Dissipation of solenoid heat is normally not a problem in slow speed character printers.

However, it has been observed to sometimes become a problem in high speed dot matrix character printers. When the print head is activated for a substantial time and the characters to be generated in a relatively short interval require the printing of a somewhat higher than average number of dots during that interval, solenoid heat may be inadequately dissipated. When that happens, solenoid response 25 characteristics may be altered due to parametric variations, and one or more of the printing rods may cause a dot to be printed slightly earlier or later than intended, or even not at all. This degrades the appearance of dots and characters printed under such conditions and may, under severe conditions, even lead to the printing of unrecognizable or incorrect characters. Solenoid power supply failure or degraded performance may also result, as a greater load is imposed thereon. And excessive heat may 30 cause permanent damage to the solenoids or other components. Considerable efficiency is lost if the character printing rate is significantly reduced in order to avoid the solenoid heat dissipation problem, since high reliability would require a substantial reduction in speed.

Typically, in the prior art, in order to change the pitch of printed characters, it has been necessary to provide additional tracks on the encoder at different pitches or to physically change the encoder-tocarriage "gear" ratio. These approaches have typically been cumbersome and not conducive to changing pitch on a character to character basis.

It should also be noted that the printing heads of prior art printers generally have their print rods all arrayed in a single vertical column. Unless the print head is capable of vertical motion, this means that dots formed by adjacent print wires (or rods) cannot overlap; some dot spread caused by the ribbon 40 may, however, allow some blending together of adjacent dots, but resolution is ultimately limited to that provided by tangentially touching dots.

The printer embodying the present invention is designed to permit the printing of dot-matrix characters of different pitches (i.e., horizontal widths). Character pitch is selectable and variable on a character by character basis, if desired. Electronic signals under the user's control provide for pitch selection. Provision is also made to control the printing speed electronically, to achieve smooth starting and stopping of the carriage while maximizing the character printing rate. The maximum printing speed is limited by the speed at which the print head solenoids can operate. However, if the text to be printed requires a dot printing rate which would result in overheating of the print solenoids or their power supply, the printing speed is reduced until a safe dot printing rate is achieved. The maximum permissible 50 dot printing rate is a system parameter empirically derived.

Variable rate character printing requires that the printing head carriage traverse the paper at a variable rate. Because the rate of carriage travel is appreciable with respect to the time between a solenoid actuation command and the time the associated printing rod strikes the paper, it is necessary to compensate for variations in the carriage motion in order to always have the printing rods strike the 55 paper in a desired position; this position is, of course, intended to be insensitive to the character printing rate. The situation is analogous to the case of a hunter shooting at a moving duck from a fixed location.

In order to allow for the motion of the duck during the time his bullet is in flight, the hunter must aim ahead of the duck; this character printer merely presents the converse situation since the target is fixed and the projectile is fired from a moving platform, although the relative motion problem is the same. 60 Means are therefore provided for deriving a correction factor for actuating the solenoids at the proper times to compensate for the instantaneous rate of carriage motion relative to the paper.

Additionally, in the preferred embodiment of the invention, the print rods are arranged in two columns such that the print rods in one of the columns are vertically displaced with respect to the print 2 GB 2 080 003 A 2 rods in the other column. This permits a higher resolution (i.e., density) dot printing and allows dots to be overlapped a significant amount, so that the dot matrix characters more nearly approximate conventionally printed characters. Separate solenoid firing time signals are required for each column of print rods, to account for their different horizontal positions at any given time.

The printer embodying the present invention also provides such features as the capability of 5 allowing the user to change type fonts and pitch from character to character within the line.

In order that the invention may be more readily understood, reference will now be made to the accompanying drawings, in which:

Figure 1 is a high level functional block diagram of a dot matrix character printer embodying the present invention; Figure 2 is a diagrammatic illustration of a seven-wire printing head, further depicting one possible mapping of dot buffer output lines to solenoids; Figure 3 is a diagrammatic illustration of an eleven-wire printing head, further depicting one possible mapping of dot buffer output lines to solenoids; 1 Figure 4 is a functional block diagram of the Printer Control Circuit (PCC) of Figure 1; Figure 5 is a state transition diagram of the Print Enable Circuit of Figure 4; Figure 6 is a state table for the Print Enable Circuit; Figure 7 is an overall functional block diagram of the encoder signal processor of Figure 4; Figure 8 is a detailed block diagram of the signal filters of Figure 7; Figure 9 is a detailed block diagram of the transition detector of Figure 7; Figure 10 is a detailed block diagram of the direction detector of Figure 7; Figure 11 is a detailed block diagram of the transition and increment counter of Figure 4; Figure 12 is a detailed block diagram of the pulse stretcher of Figure 4; and Figure 13 is a diagram of the method steps involved in computing the flight time compensation count and for controlling the transition adder.

Referring now to Figure 1, there is shown a high-level functional block diagram of a dot matrix character printer embodying the present invention. Paper 12 is the output medium on which the printing is performed. The paper is normally carried on sprockets 14A, 14B passed a print bar not shown, according to conventional practice. The print bar serves the same basic purpose as a platen (i.e., acts as a hard backing surface to print against) except that it does not move the paper. The edges of the 30 paper contain evenly spaced vertical holes which mate with the teeth of drive sprockets 14A and 14B for vertically feeding the paper. Images are formed on the paper by a ribbon 16 which may be carried between a pair of ribbon reels 18A and 18B or may be a cartridge type ribbon wound on one reel or spool. The print rods or wires from print head 20 force the inked ribbon 16 onto the paper 12 and against the print bar, to cause an image of the print rod to be formed on the paper. Print head 20 is carried on a carriage which traverses the paper for positioning the print head in the proper location as each column of dots is printed. Printing mechanism 22 comprises a mechanical assembly which includes the carriage and the necessary linkages and so forth for moving the carriage, together with a ribbon advancement mechanism for winding the ribbon (e.g., onto reel 18B) as it is used. The printer mechanism also includes conventional mechanical linkages for connecting the line feed stepper motor 40 24 to the tractors or drive sprockets 14b and for connecting the carriage motor 26a to the carriage motion mechanism.

A printer control circuit (PCQ 30 provides the actual control signals which cause the carriage to move to the proper location and the appropriate print solenoids to be energized. PCC 30 provides basically three types of control signals as outputs. A line feed control signal is provided as the first output on line 32 to line feed amplifer 34. In turn, line feed amplifer 34 provides the required drive signal to the line feed stepper motor 24, to cause the line feed advance mechanism to move the drive sprockets an appropriate distance to advance the paper one line space. A carriage drive control signal is the second PCC output; it is provided on line 36 to carriage motor amplifier 38. The carriage motor amplifier, in turn, provides the drive signal to carriage motor 26A, for controlling the motion of the carriage. The carriage motor is also equipped with an incremental shaft position encoder 26B for providing an output signal on line 42, to the PCC, representative of the change in angular position of the motor shaft. Since the rotational position of the carriage motor shaft directly corresponds to the position of the carriage and, in particular, the print head, the signal on line 42 represents the position and position changes of the print head. The third output of the PCC is a print head control signal provided on 55, line 44 to the print head driver 46. The print head driver 46, responsive to signals provided on line 44, provides an actuation signal to appropriate solenoids in the print head 20 to cause the associated dots to be printed at a desired location.

For use with a computer, or other similar source of data to be printed, the printer is provided with an input interface 48. This interface provides appropriate input buffering for capturing the data to be printed. A table of character-to-dot patterns stored in ROM 56 of sequential controller 50 is used to convert the character information provided by the input data source into dot matrix information representing each character to be printed. By varying the character-to- dot pattern mapping, different fonts (such as different typefaces or typefaces for different alphabets e.g., Cyrillic, Greek, etc.) may be printed. Characters having the same basic font (i.e., typeface) maybe spread or compressed in the 65 Z 3 GB 2 080 003 A 3 horizontal dimension by altering the spaces between dots and the blank spaces between characters, thereby altering the pitch of the characters. And, since the mapping must be done on a character-bycharacter basis, it is possible to change character size and font on the same basis. There is no provision for changing the size of printed characters in the vertical dimension if the number of vertical print rod positions would thereby be exceeded, but various character widths can be accommodated and vertically 5 compressed or stretched characters can be generated using less than, or at most, the full number of vertically available print rod positions.

A sequential controller 50 for generating PCC control or command signals and provided characterto-dot mapping comprises a processor unit 52, random access memory (RAM) 54 and a read only memory (ROM) 56. Interface 48, processor 52, RAM 54, ROM 56 and PCC 30 are all interconnected via 10 a bus or communication link 58.

Character information to be printed is fed from the input interface 48, via bus 58, to RAM 54, where it is temporarily stored. ROM 56 controls the operation of the processor 52 and the data paths between the various elements connected to the bus 58. Using the character-dot mapping provided by the ROM, processor 52 provides instructions to PCC 30 regarding the dot pattern to be printed. In turn, PCC 30 determines the appropriate times, as a function of carriage position, for activating the print head driver to fire the print head solenoids.

While various components may be used to fabricate the box described above, it is particularly noted that the models 8080A and 8085 microprocessors manufactured by Intel Corporation have been found suitable for the processor 52. Accordingly, the particular embodiment disclosed in detail herein is 20 described with reference to the use of the aforesaid Model 8080A. The printer control circuit 30 could also be implemented in a number of ways. However, in order to minimize cost and number of interconnections, we have implemented it as a single large scale integrated circuit using metal oxide semiconductor technology, with a design architecture suitable for control by a microprocessor.

The printer control circuit is capable of operation in two modes for generating characters of different pitches. The first mode permits the use of a conventional seven wire head containing seven print rods arranged in a single vertical column. The second mode permits use of two, horizontally displaced columns of print rods. The specific illustration of this mode, described below, shows the use of an eleven wire print head having a first vertical column of six print rods and a second vertical column of five print rods. The embodiment illustrated further shows the rod positions in the second row vertically 30 spaced from the rod positions in the first row so as to achieve a vertical interleaving of positions and permit the printed dots formed by vertically adjacent rods in the two rows to overlap. Figure 2 illustrates the print rod positions in a seven wire head and Figure 3 illustrates the print rod positions in an eleven wire head.

A functional block diagram for the printer control circuit (PCQ 30 is shown in Figure 4, to which 35 reference will now be made. Character data to be printed and supervisory. commands to the PCC are received via the bus 58 which enables the PCC to communicate with the sequential controller and input interface, as required. Information received by the PCC upon the bus 58 is captured by an input buffer 62. The input buffer 62 feeds this information to the various functional elements of the PCC via a parallel bus 64. In the drawing, bus 64 is indicated separately at the appropriate functional blocks (by an 40 arrow comprising two spaced, short parallel lines terminated by an arrowhead at one end and broken off at the opposite end); it should be understood that the bus interconnects all of the indicated blocks even though the full interconnection is not illustrated.

One of the elements connected to bus 64 is a command decoder 66. This command decoder is also connected via lines 68 to the various other elements of the PCC; such connections are not explicitly 45 shown, however, in order to maintain clarity in the drawing. Command decoder 66 detects and decodes the commands provided by the sequential controller and through the use of appropriate steering logic activates, deactivates and controls the functional blocks shown in Figure 4 to achieve the operation directed by the commands.

As briefly stated above, the function of the PCC is to supply appropriate signals to drive the line 50 feed amplifier 34, carriage motor amplifer 38 and print head driver 46. The dominant function of the PCC is to implement the required control of the print head driver 46 for printing, with variable pitch and performing the "duck shooting" operation involved in printing with a variable carriage speed. The desired carriage speed is a function of carriage position in the line, with the objective being to maintain maximum throughput of characters with the limits imposed by available acceleration, start/stop 55 dynamics of the print head, and solenoid actuation rates which avoid excessive heating. The processor 52 determines the appropriate carriage speed and the PCC actuates the print head driver accordingly.

Thus, the basic information required by the processor 52 is the position and velocity of the print head.

This information is obtained from encoder 26B which is driven by the carriage motor 26A. Encoder 26B is an incremental two-channel encoder which provides a digital output. A short up-down position counter 72 receives the output of the incremental encoder 26B via an encoder signal processor 74 which suitably conditions and formats the output of the encoder. Thus, the position counter 72 keeps track of the relative position of the print head, modulo its radix. The output of position counter 72 is supplied to the output buffer 78 on demand, and, from the output buffer, to bus 58 and processor 52.

Processor 52 periodically examines the position information provided by the position counter 72 and 65 4 GB 2 080 003 A 4 calculates print head velocity from the change in position during the inter-sample time. In the particular embodiment heretofore implemented, the processor 52 samples the output of the position counter approximately once every 2.5 ms. The change in position observed at each sample time is summed in a position register (i.e., address location) in RAM 54. Absolute position information is obtained by initializing the position register to a known value when the carriage is forced against a fixed stop. 5 The initialization procedure of the printer requires that the carriage motor be commanded to drive the carriage in the direction of the stop. When the processor detects no change in the position counter's output during a predetermined number of sample times in which the carriage is being commanded to move toward the stop, it "knows" that the carriage has already reached the stop; the position register is then initialized. All relative motion can then be compared against this initial position, to be transformed 10 to absolute position.

While various encoder designs well suited to this application will be apparent to those skilled in the art, this system has been successfully implemented with an encoder of the type which uses two tracks to provide a pair of (phase) quadrature output signals; these encoder signals are supplied to the IPCC encoder signal processor (ESP) 74 via lines 42A and 42B (which are collectively shown as line 42 15 in Figure 1). Encoder signal processor 74 is used to give---clean- position decoding and insure that only valid state changes on lines 42A and 42B are interpreted by the PCC as indicative of carriage motion. ESP 74 may, for example, comprise a socalled -majority vote- circuit which uses a high sampling rate to distinguish between valid and invalid state changes in the encoder's quadrature output signals.

At this point it would be helpful to the further understanding of the operation of the PCC to digress 20 briefly for an explanation of character---cell-structure. All printing of characters by this system takes place within programmable character cells whose fundamental units are encoder -transitions" (i.e., logic state changes in the encoder quadrature output signals). As successfully implemented, for example, each encoder transition may correspond to print head or carriage motion of 11660 of an inch.

A character cell consists of two sections, the first (from the left) is the increment field in which dots may 25 be printed; the second is the inter-character space. Within the increment field, two or more increments are equally spaced. Their spacing is a programmable parameter called transitions per increment,- TP 1. TPI is often also referred to as the radix of the character and is a function of character width or pitch. The number of increments per character, IPC, is also programmable. Since an increment occurs at both the beginning and end of the increment field, the width of the increment field (in transitions) is given by 30 TPI x (IPC 1). The inter- character space has no fine structure and is directly programmed as transitions per space, TPS. As the name implies, dot printing is inhibited (i.e., no increments occur) in the inter-character space. A character cell's width is equal to the sum of the widths of the increment field and the inter-character space, so that total width is given by:

WIDTH= TPI X OPC - 1) + TPS. 35 The diagram below illustrates a single cell of width 40, IPC = 13, TP 1 = 3, and TPS = 4:

1.. 1.. 1.. 1.. 1.. 1.. 1.. 1.. 1.. 1.. 1.. 1.. Isss where 1 represents an increment, s represents a space, and the ".--- symbol represents any other transition.

Each of the parameters mentioned above - TPI,]PC and TPS - can be programmed into the PCC from the processor 52 to select a particular font compression or pitch. While printing, the PCC counts transitions and increments so that it knows when a character boundary, increment or space is occurring.

When the printing of a character is begun, the transition counter uses the value of TPI as a radix. Every time the transition counter overflows, an increment is generated which, among other things, causes the increment counter to change its count. When the increment counter reaches a count equal to IPC, the radix of the transition counter is changed to TPS, so that the proper inter-character space is generated. When the next increment is received, the increment counter goes to a value less than]PC (either 0 or [PC - 1, depending on direction). At this time a character boundary signal is generated and the radix of the increment counter again becomes TPI.

It can be seen that the transitions per space could be any non-zero number. However, the fact that 5Q the timers operate on every increment makes it desirable for TPC to beat least equal to the value of TPI.

The counters involved can be initialized by a command from the sequential controller 50. Table 1, below lists several character pitches and the parameters that generate them.

4 GB 2 080 003 A 5 TABLE 1

CP1 TPC IPC TPI TPS 66 11 6 6 12 55 11 5 5 13.2 50 10 5 5 16.5 40 10 4 4 132 11 12 12 6 110 11 10 10 6.6 100 10 10 10 8.25 80 10 8 8 Where CPI means characters per inch and TPC means transitions per character (i.e., pitch). The first four rows represent normal pitches and the second four rows represent double width pitches.

Encoder signal processor 74 provides three output signals derived from the quadrature signals received from the shaft encoder. The first of these signals is a direction signal, on line 82, indicative of 5 the direction of carriage motion. The direction signal is provided to position counter 72 in order to cause it to either count up or down, as appropriate. Carriage motion in a first direction will cuase the position counter to count up and carriage motion in the other direction will cause the position counter to count down, A second output of the ESP, provided on line 84, is an encoder transition pulse signal. The latter signal comprises a pulse each time one of the two quadrature encoder signals on lines 42A and 42B 10 changes state, indicating that the carriage has moved one transition distance from its prior position. The pulses in the encoder transition pulse signal on line 84 are supplied to and counted by the position counter 72 for keeping track of changes in carriage position. Lines 82 and 84 are also connected to transition and increment counter (T & IC) 86 and line 82 is further connected to a pulse stretcher 88.

The third output signal from the ESP 74 is a speed transition pulse signal on line 92; this signal 15 comprises the second input signal to the pulse stretcher 88.

To implement the above-described performance capabilities, print commands must be given to the solenoids at varying (i.e., not fixed) positions relative to the "target" location at which printing is desired; the solenoid actuation (i.e., "firing") positions are functionally related to print head velocity, since the distance travelled by the print wires is fixed. Sequential controller 50 computes the required 20 solenoid firing position and PCC 30 generates the actual signals which control solenoid actuation in accordance with the calculations of the sequential controller. The transition and increment counter 86 is the starting point within the PCC for the generation of the necessary control signals. T Et IC 86, as its name implies, comprises a pair of counters for respectively tracking transitions and increments. Signal inputs for the T & IC 86 are the direction signal on line 82 and the encoder transition pulse signal on line 25 84. Since the carriage is moving while the printing operation takes place, the print rods must be "fired" from the moving print head before the carriage reaches the impact location. Nominally, the mean value of this lead "time" is known for an average carriage speed, one of the system design parameters. However, carriage speed may be variable in this invention and other, non-average speeds will require a greater or smaller lead (i.e., positional displacement) between print wire firing and impact, depending 30 upon whether the speed is below or above average. Translating the lead into position units, there is a nominally known displacement (in transitions) between the impact position on the paper and the position of the print head when the solenoids are actuated. Appropriate circuitry is provided for reading the "position" indicated by the T & IC and triggering the firing of the solenoids when the position of the carriage indicated by the T & IC is the correct distance from the target position on the paper, for the then 35 Current carriage velocity. Thus, a preselected transition count (e.g., a count equal to the transition counter radix) in the T Et IC comprises a trigger signal for the printing solenoids. The solenoids are actuated in response to the appearance of this count. Processor 52 supplies a transition add/subtract command to the T & IC via bus 64 to cause the transition count stored therein to be either increased or decreased. This creates a false or pseudo-transition reading in the T & IC; this reading may be used to 40 actuate the printing solenoids by forcing the "triggering" count to appear at the position suggested by print head velocity. Thus, the transition count indicated in the T & IC to is shifted from the count registered in position counter 72 by an amount representing a flight time compensation count. That is, this difference represents the displacement, in transitions, between the point of solenoid actuation and the point of impact.

6 GB 2 080 003 A 6 The transition counter portion of the T & IC 86 comprises a counter having two programmable radices corresponding to the TP I and TPS parameters. The increment counter portion of the T Ef IC comprises a counter having a single programmable radix corresponding to the parameter IPC. The radices are supplied from the sequential controller 50 via bus 64. The transition and increment counter 86 provides three output signals.

The first of these is a character boundary signal provided on line 94 to the print enable circuit (PEC) 96. The character boundary signal merely defers the execution of the print-start command until the print wire input position enters the cell of the character to be printed. The second signal provided by the T & IC, on line 98, is a net transition signal. Line 98 is connected to increment shift register 100 for supplying the net transition signal thereto. The third output signal provided by the T Ef IC, on line 102, is a primary 10 increment signal. The primary increment signal is supplied to increment shift register 100 and to increment steering circuit 104.

The function of print enable circuit 96 is to provide internal PCC control (i.e., enablement and disablement) of the elements used to trigger the solenoids. Basically, the print enable circuit is a finite state machine the operation of which is defined in Figures 5 and 6. Remaining briefly with Figure 4, 15 however, it will be seen that the PEC 96 has three signal inputs and one signal output. The first signal input is the character boundary signal on line 94. The second signal input is a printing done signal on line 106 from buffer monitor circuit 108. Sequential controller 50 provides the third input signal, a print start signal, via bus 64. The output of P EC 96 is a print enable signal on line 112. The print enable signa is supplied to increment shift register 100 and to increment steering circuit 104. The print enable signal 20 will assume a first logic state when printing is to be enabled and will assume a second logic state when printing is to be disabled. Referring now to Figure 5, there is shown a state transition diagram illustrating the normal operation sequence of the print enable circuit. The PEC has three states, labeled respectively, 114, 115, and 116. Printing is disabled in states 114 and 115; only in state in 116 is printing enabled. Assuming initially that the PEC is in state 114, as it would be after printing has 25 previously been terminated or at a time following initialization but prior to the start of any printing, a print start command from the sequence controller received via bus 64, will cause a change to state 115; at this point the PEC assumes control over the printing operation. Once the PEC is in state 115, it monitors the character boundary signal on line 94; when that signal indicates that the leading edge of the character cell boundary has been crossed, the PEC advances to its third state, 116, and provides the 30 print enable signal on line 112 in the state which permits printing. The printing operation will continue until buffer monitor circuit 108 provides a printing done signal on line 106 to indicate that there is no more information to be printed. Upon receipt of the printing done signal, the PEC will return to state 114 and disable printing by changing the state of the print enable signal on line 112. Printing will not resume until another print start command is received from the sequence controller. Thus, the state 114 may be 35 called an idle state, state 115 corresponds to a state of waiting for a character cell boundary and state 116 corresponds to the active printing state. The state transition table shown in Figure 6 provides another description of the PEC, assuming a particular implementation in which the printing disabled condition corresponds to a logical "0" print enable signal and a logical "I" print enable signal permits printing to be performed. Corresponding assumptions are made with respect to the logic values of the 40 PEC input signals. The symbol "X" is used in Figure 6 to indicate, with respect to input, that either logic level may exist and, with respect to states, that any state satisfies the condition.

It is noted that in the above description the term "character boundary" corresponds to the increment which makes the increment counter in the T & IC exit the intercharacter space. The term "increment" refers to that transition which makes the transition counter in the T Ef IC overflow; that is, count up from maximum to zero or down from zero to maximum. And "intercharacter space" is that interval during which the increment counter value is equal to its radix (i.e., its maximum value).

Two dot buffer and timer circuits, 120A and 120B are provided. When a twocolumn (e.g., eleven wire) print head is employed, one of the dot buffer and timers is associated with a first of the columns and the other dot buffer and timer is associated with the other of the columns. These might correspond, 50 respectively, to five and six dot columns, respectively. When only one column of print rods is provided in - the print head, such as for a seven-wire head, both dot buffer and timer circuits are operated in parallel.

The dot buffer and timer circuits receive character dot data from the processor and fire the corresponding print solenoids at appropriate times. Each dot buffer and timer circuit includes a plurality of registers, a register controller, an output buffer and a timer. The registers are preferably arranged as a first-in-first-!6 out (or fifo) stack buffer. One of the registers in the stack is an input register which is loaded by the processor; another register comprises an output register. Data propagates through each register, beginning with the input register, until it eventually reaches the final, output register. The output of the output register is gated to the print head amplifiers at a precise point in the head travel and is held for a precise amount of time, as controlled by a timer in the dot buffer and timer circuit. The purpose of the 60 dot buffer and timer circuits is to allow the processor 52 to supply dot data for the print head asynchronously with respect to the time that such data is needed for actuation of the solenoids. The controller in the dot buffer and timer circuits consists of a memory which tracks the presence, in each register, of data to be printed together with logic which causes all data to advance as far as possible through the fifo stack. The controller detects when the timer has ceased actuating the output buffer and 65 1 4 7 GB 2 080 003 A 7 thereupon advances the data in the registers. This creates space at the input of the stack. A buffer status signal is supplied on lines 122A and 122B to buffer monitor circuit 108. When a predetermined number of spaces exist in the fifo stack(s), as indicated by the buffer stack signals to the buffer monitor, the buffer monitor generates a dot data request signal to the processor, on line 124. The processor then supplies more data into the dot buffer input register. When both buffer stacks are completely empty, the buffer monitor generates a printing done signal on line 106, to reset the PEC 96.

The timer in each of the dot buffer and timer circuits is used to cause the dot data to be present to the printing element (i.e., solenoid) for a programmable amount of time determined by the characteristics of the element being controlled. The timer consists of a binary counter which counts a programmable number of clock cycles. It starts counting on command of the increment steering circuit 10 104, unless already running. Each time the timer halts, it supplies a signal to the stack controller to allow new data to be presented to the output buffer.

The output buffer in the dot buffer and timer circuit allows the output of the stack to propagate to the print head whenever the timer is running.

Each register in the fifo stack in the dot buffer and timer circuits 1 20A and 1 20B contains storage15 sufficient for one vertical column of dots. In the particular implementation shown in the drawings and discussed herein, one of the dot buffers contains five-bit registers and the other contains six-bit registers, thus providing for the control of a maximum of eleven printing solenoids in the print head. It is readily possible, of course, if only a single column print head is to be employed, to use but one dot buffer and timer circuit having the same number of bits per register as the number of print wires. The 20 increment shift register 100 and increment steering circuit 104 also become unnecessary in the latter application, as the single dot buffer and timer circuit is directly controllable by the primary increment signal, explained below.

With a two column printing head, solenoid control is complicated by the fact that the two columns of wires are physically displaced in the horizontal direction. Therefore, in order to print a single vertical 25 line of dots, the trailing set (i.e., column) of wires must be fired a number of transitions later than the leading set - the number of transitions corresponding to the displacement between the two columns of wires, measured in transitions. Thus, the two columns of wires are provided with two different firing control signals. These are referred to as primary and secondary increment signals. The primary increment signal fires the leading set of wires and the secondary increment signal fires the t railing set of wires. When 30 printing, the secondary increment repeats the primary increment pattern, only delayed by the necessary number of transitions. It should further be noted that printing may be done either left to right or right to left. In one direction, one of the columns will be the leading set and the other will trail; but the situation will be reversed in the opposite direction, with the other column being the leading set.

The primary increment signal is generated by the transition and increment counter 86 and is provided 35 on line 102 to the increment shift register 100 and increment steering circuit 104. Increment shift register 100 performs the transition delay function for generating the secondary increment signal therefrom. The secondary increment signal is provided on line 126 to increment steering circuit 104.

Net transition signal 98 is essentially used as a clocking signal for increment shift register 100.

When the printer is operated in the two column print head mode, the increment steering circuit 40 directs the primary increment signal to the dot buffer and timer for the leading set of print wires and the secondary increment signal to the dot buffer and timer for the trailing set of print wires. When the printer is operated in the single column print wire mode, increment steering circuit 104 directs the primary increment signal to both dot buffer and timer circuits, as the secondary increment signal is not used.

The PCC also drives the carriage amplifier in the carriage servomotor system, for controlling carriage motor speed. Carriage motor speed control is accomplished by a servo system. Processor 52 determines the maximum possible carriage speed based upon the highest solenoid actuation rate at which the print solenoids will operate properly and which may be maintained without causing overheating. It provides a speed command signal via bus 64 to bit rate multiplier (BRM) 132. The BRM 50 is of conventional design and provides two output signals.-The first of these is a command sign signal, on line 134, to indicate the direction in which the motor is being commanded to operate; the second of the BRM output signals is a command pulse signal on line 136, which provides the actual motor velocity information. The speed transition pulse signal on line 92 and the direction signal on line 82 comprise corresponding signals indicative of the actual motion of the carriage motor. These latter two signals are 55 received by pulse stretcher 88 which, in turn, supplies the feedback signals required in the servo loop. A feedback sign signal is provided on line 138 and a feedback pulse signal is provided on line 139. The speed steering circuit 142 connects lines 136 and 139 to the appropriate output pins 144 and 146 in accordance with the associated sign signals carried on lines 134 and 138 respectively. These pulse trains are received by the Carriage Amplifier 38 which integrates these pulse signals to obtain their average values. The Carriage Amplifier is the "error" amplifier of the carriage motor servo; it determines the difference between the commanded speed and direction and the actual speed and direction of the motor and provides a drive signal to the carriage motor to drive the carriage motor toward the commanded speed.

The command given to the servo mechanism by the BRM consists of a stream of narrow pulses.65 8 GB 2 080 003 A 8 The speed transition pulse signal on line 92 containing the motor speed information used for feedback, have the same width as the BRM command pulses; however, there are several e.g., eight, command pulses for every speed transition pulse provided on lines 92. The servo mechanism is designed, typically, to respond to the average value of the command pulse and feedback pulse signals; thus, it becomes necessary to "stretch" the speed transition pulses a commensurate amount. This is done by producing a 5 feedback pulse on line 139, for every speed transition pulse on line 92, which is eight times as long thereas. For example, if the command pulses are each 6.5 ms in width, the feedback pulses are' approximately 52 ms in width.

In Figures 7-12, there is a further breakdown, still on the block diagram level, of some more of the blocks shown in Figure 4. Figures 7-10 provide a breakdown of the encoder signal processor 74. 10 An overall block diagram of the encoder signal processor is shown in Figure 7. The purpose of the encoder signal processor is to convert quadrature encoded squarewave position signals, received on lines 42A and 42B from the two encoder tracks, into transition event and direction signals that can be counted in up/down counters and used to trigger transition-related events. The encoder signal processor which performs these functions consists of a direction detector 202 and, for each of the two channels of 15 encoder signal input, a signal filter, 204A or 204B, and an associated transition detector 206A and 206B. The outputs of the transition detectors on lines 208A and 208B, respectively, are combined together by OR gate 210 to provide the encoded transition pulse signal which is supplied to the position counter 72 and T & IC 86 on line 84. The speed transition pulse signal is provided on line 92 by AND gate 212 which receives as its inputs the transition detector output signal on line 208A from one of the 20 channels and the input of the transition detector 206B of the other channel, on line 214. Direction detector 202 receives the outputs of the two signal filters on lines 214 and 216 to provide the direction signal on line 182. It will thus be seen that the encoder transition pulse signal provides a pulse each time there is a state transition in either of the two signals provided by the encoder, and that the speed transition pulse signal provides a pulse when there is a transition on one of the channels while the other channel is in the 'T' state. In steady state operation, a speed transition pulse will appear on line 92 every fourth transition. In the specific implementation discussed herein, the width of these pulse signals corresponds to one clock period of the system clock.

The output of the direction detector is, by contrast, a level which represents the sign (+ or -) of the transition and identifies which of the two quadrature signals is ahead of the other in phase. 30 The purpose of signal filters 204A and 204B is to remove short duration noise pulses from the signals on line 42A and 42B so that they do not cause false outputs and false responses by the transition detectors and direction detector. It has been found particularly desirable to implement the signal filters as majority vote circuits which compare two new samples of their input with the previous output. The outputs of thesignal filters are allowed to change state only if the two new samples agree 35 with each other. For further reliability, an even greater number of samples could be used. The two samples of the input of the signal filter are taken at a normal system clock rate but approximately 1801 out of phase with each other, thereby yielding a net sampling rate which is twice the normal clock rate.

An appropriate block diagram for each of the signal filter elements 204A, 204B is shown in Figure 8. While the example is described in terms of signal filter 204A, it is equally applicable to signal 40 filter 204B, of course. Four conventional sample-and-hold (S Ef H circuits and a majority vote circuit are employed in each signal filter. The sample-and-hold circuit 222 provides the output of the signal filter which represents the signal provided by the majority vote circuit 224 at sampling time T, The two signal samples are taken at times T, and T3, respectively, by S & H circuits 226 and 228. The fourth sample-and-hold circuit 232, samples the prior output which is present on line 216 at time TV as well. 45 As explained above, sample and times T, and T3 are displaced from each other by approximately 1800 but occur at the same rate, being derived from the same clock. Majority vote circuit 224 reads the outputs of S & H circuits 226, 228 and 232 appearing on lines 227, 229, and 23 1, respectively, and provides an output on line 225 corresponding to the state of the majority of its inputs. The signal input on line 42A is preferably synchronized so as to be stable at the T2 and T, sample times. A clocked 50 D-type flip-flop, Schmitt trigger or similar device (not shown) may be used for this purpose.

The purpose of the transition detectors 206A and 206B is to produce an event pulse each time their input signals change state. This is easily accomplished with the arrangement shown in Figure 9. As shown therein, the transition detector 206A, for example, consists of a delay element 236 and an exclusive -OR gate 238. The output of the delay element, online 237 and the input, online 216, 55 provide two inputs of the exclusive OR gate 238. This produces at the output of the exclusive OR gate, on line 208A, a stream of pulses each of whose width is equal to the delay time of the delay element.

The delay time of one clock period of the system clock is satisfactory for this purpose. Thus, delay element 236 is shown as also receiving the system clock on line 239.

The output of the direction detector 202 in the encoder signal processor accompanies each of the 60 transition event signals (i.e., the speed transition pulse signal and the encoder transition pulse signal) to their destination. The purpose of the direction detector is to decode the quadrature encoded direction information in the two input signals on lines 42A and 42B, producing an output signal whose states correspond to the directions associated with the transition event pulses. One satisfactory exemplary implementation of the direction detector is shown in Figure 10. As illustrated therein the direction 65 1 J 9 GB 2 080 003 A 9 detector 202 consists of a delay element 242 and then exclusive-OR gate 244. One of the inputs, e.g.

the one on line 216, is delayed by the delay element 242 and the delayed signal is provided on line 243 to one of the inputs of the exclusive-OR gate 244. The other input, e.g. the one on line 14, is supplied directly to the other input of the exlusive-OR gate. The output on line 82, if observed only during the periods when the encoder transition event signal is asserted, will (at those times) be in one state when the transition was in one direction and then the other state when the transition was in the opposite direction. Delay element 242, like delay element 236 provides a single clock period delay and receives a system clock as an input on line 246. It will be observed that if the clocking signals on lines 246 and 239 are the same, the outputs of the delay elements 236 and 242 are the same. Hence, a single delay element maybe shared between the direction detector and one of the transition detectors.

Referring to Figure 11, there is shown a block diagram breakdown of the T & IC 86. The transition and increment counter 86 has three component elements: transition adder 252, transition counter 254 and increment counter 256. The transition counter and increment counter have already been alluded to above. The transition adder 252 basically operates under the control of the sequential controller 50 to provide the required offset in the count maintained in the transition counter from the count maintained 1 & in the position counter (i.e., the flight time compensation count) so as to cause the transition counter to produce the solenoid-actuating count at the appropriate location. When a two-column print head is used, the transition adder also "moves" the primary increment when the direction of printing changes, to account for the displacement between the two columns of print wires. Additionally, the transition adder serves to eliminate single transitions having opposite signs (i.e., direction) from the immediately 20 preceding and following transitions, such as are produced by the operation of the transition add/subtract circuit. Other such signal transitions should not and would not occur but for the presence of "noise" and sampling inaccuracies.

Included within the transition adder 252 is a net transition generator 252A which actually provides the two transition adder output signals, the net transition signal (on line 98) and the net direction 25 signal (on line 253). In addition to eliminating single transitions of opposite sign, the net transition generator 252A operates under the command of the sequential controller 50 either add transitions on line 98 which are in addition to those provided on line 84, or prevents pulses on line 84 from reaching line 98, in order to force the transition counter 254 to properly reflect the positional correction required for actuating the solenoids at the proper time. The net direction signal on line 253 is simply the direction 30 signal which corresponds to the net transition signal on line 98; it is the direction signal on line 82 as modified by the operation of the net transition generator 252A in adding, subtracting or eliminating pulses.

Transition counter 254 comprises a programmable radix counter having two programmable radices, corresponding to TPI and TIPS, which are set by the sequential controller 50 via the bus 64. 35 Transition counter 254 is an up/down counter which receives counting direction control from the net direction signal on line 253 and which counts the pulses in the net transition signal on line 98. The output of the up/down counter is decoded to provide as the output of the transition counter a signal, termed the primary increment signal, on line 102 when the transition count of the up/down counter corresponds to the position at which the printing solenoids should be actuated. Increment counter 256 40 receives the primary increment signal and the net direction signal as inputs and provides the character boundary signal as an output, on line 94. The increment counter is a simple, programmable radix counter whose radix, corresponding to the parameter IPC, is set by the sequential controller via the bus.

The third block shown on Figure 4 to be broken down for further explanation of its structure is the pulse stretcher 88, shown in Figure 12. The pulse stretcher comprises two components: speed transition processor (STP) 262 and pulse generator 264. The speed transition processor receives the direction signal on line 82 and the speed transition signal on line 92 as well as a 19.2 kHz pulse on line 266; its outputs are the feedback sign signal on line 138 and a feedback pending signal on line 268.

The feedback pending signal comprises one of the inputs to pulse generator 264. The 19.2 kHz pulse signal on line 266 is the other input to the pulse generator, and the feedback pulse signal on line 139 is 50 its output. The STP contains a one-bit memory of feedback sign and one- bit memory of feedback pending. If a speed transition occurs with a direction (i.e., sign) which matches the previously - established feedback sign, the feedback pending signal is then asserted. The feedback pending signal is deasserted immediately after the next occurrence of the 19.2 kHz pulse. If the direction of the speed 56 transition pulse does not match the feedback sign, the feedback sign is changed, but no feedback pending signal is generated. The pulse generator 264 samples the feedback pending signal on line 268 each time a 19.2 kHz pulse occurs and asserts a feedback pulse on line 139 appropriately, thus producing pulses approximately 52 microseconds wide, eight times the width of the command pulses on line 136 from the bit rate multiplier 132.

As stated above, the sequential controller 50 is the commanding agent, or "brain," driving the 60 PCC 30. Among other things, the sequential controller determines flight time compensation count which is necessary and provides transition add/subject commands to the transition adder to cause the net transition generator to feed a lesser or greater number of pulses to the transition counter, to produce the correct flight time compensation count. The sequential controller drives the carriage motor to the highest available speed consistent with satisafactory acceleration and solenoid operation. The upper 65 GB 2 080 003 A 10 limit on carriage motor speed is partially a function of the dot density of characters to be printed over a preselected time interval, so that the solenoid actuation rate does not exceed empirically derived bounds for satisfactory operation. Accordingly, the carriage speed is greater in blank regions, as the solenoid actuation rate does not impose a limit at all in those areas.

In the present implementation, the system clock speed of 2 MHz has been selected because it allows operation of the model 8080A microprocessor at nearly its maximum speed and when divided by 13, yielding 153.6 kHz, provide the 6.5 microsecond sampling interval used by the encoder signal processor 74. It also provides the clock signal needed by input interface 48 for serial data communication; in particular, it permits the use of many standard signaling rates such as 9600 bits per second and derivatives thereof. The same 153.6 kHz signal drives BRM 132. As a byproduct, the BRM 10 provides a signal at 1/128 this frequency which when divided by 3, provides the 2.5 ms sampling interval used by sequential controller 50 to process the readings of position counter 72.

While the method employed by the sequential controller for flight time compensation may be generalized to the extent illustrated in Figure 13, the flight time compensation count needed by a particular embodiment of this invention is a function of carriage velocity; if carriage acceleration is not 15 kept low enough, the compensation function must depend on that parameter too, of course. The compensation available is limited by the velocity range resolved by minimally incrementing or decrementing the flight time compensation count, Since the compensation required is dependent on the mechanical parameters of the printer (i.e., the goal is to compensate for the finite flight time of print wires and other dynamically induced positional offsets), the actual compensation function needed is 20 characteristic of the particular printer. The appropriate printer parameters may be obtained either by modeling or by empirical evaluation.

An illustration of the sequential method steps required for flight time compensation count derivation is shown in Figure 13. The first step, 310, is to measure the positional change of the carriage which occurred during the previous inter-sample interval; this is labelled DELTAX DELTAX is obtained 25 by sampling the output of position counter 72 at each sample time (i.e., at the beginning and end of that interval). DELTAX is a signed variable and its sign indicates the direction of carriage motion during the interval time. Next, if required by the nature of the printer mechanism, an appropriate offset may be added to DELTAX, in step 320. The purpose of the offset is to compensate for mechanical "play" in the printer drive or other such factors which are functions primarily of direction and not velocity. In some 30 systems, such offsets may not beneeded for acceptable registration of printed dots. The next step, 330, is to compute the change in FTC required by virtue of the change in the offset-adjusted DELTAX observed during the last sampling period. The required value of FTX may generally be expressed as a function of offset-adjusted DELTAX In the particular implementation using a printer mechanism similar to that employed in the model LA36 terminal manufactured by Digital Equipment Corporation, Maynard, 35 MA, it has been found that this function may be expressed as a proportionality constant whose value is primarily determined by print wire flight time and secondarily determined by velocity-related mechanism variations, such as elasticity of the carriage driving linkage. Thus, the FTC connection function may be obtained from an expression in the form:

desired FTC = KFTC (DELTAX + offset adjustment), 40 where KFTC represents the proportionality constant.

Since the transition counter can only resolve integer multiples of a transition and the above calculation may lead to the computation of a desired FTC which differs from the position count by a non-integral number of transitions, the desired FTC can only be approached on a greatest integer basis.

Specifically, the resolution obtained in the above calculation is equal to one transition divided by KFTC. 45 Thus, in step 340, an add-subtract command is sent to the T Ef IC 86 to cause the net transition generator to add or subtract a number of transitions corresponding to the greatest integer in the difference between the prior FTC and the desired FTC, to cause the greatest integer in the desired FTC -to become the new FTC.

While it may be possible to complete the above updating of FTC in its entirety during one inter- 5Q sample period, it has also been found that if acceleration is low enough, the updating may be done at a slower rate, even as slow as one transition add or subtract per sample interval.

A

Claims (3)

1. A dot matrix character printer of the type having a print head positioned by a motor and including encoder means for producing an encoder signal responsive to the incremental changes in print 55 head position, said encoder signal alternating between two states and changing state when the print head moves a predetermined distance, said printer further comprising encoder signal filter means operable to remove relatively short duration noise signals from the encoder signal and to thereby provide a filtered encoder signal, the encoder filter means comprising means for sampling the encoder signal a plurality of times and for changing the state of the filter encoder signal only when the encoder 60 signal is in the same state for two successive sample times.

2. A dot matrix character printer as claimed in claim 1, wherein said encoder filter means z i GB 2 080 003 A 11 comprises means for sampling the encoder signal a plurality of times during the smallest increment of print head movemenrof interest and for changing the state of the filter encoder only when the encoder signal is in the same state for a majority of such sample times.

3. A dot matrix character printer as claimed in claim 1 or 2 and substantially as hereinbefore described with reference to Figures 1, 4 and 8 of the accompanying drawings.

Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1982. Published by the Patent Office, 25 Southampton Buildings, London, WC2A lAY, from which copies may be obtained.

3. A dot matrix character printer as claimed in claim 1 and substantially as hereinbefore described 5 with reference to Figures 1, 4 and 8 of the accompanying drawings.

New claims or amendments to claims filed on 28.8.81.

Superseded claims 2-3.

New or amended claims:- 2. A dot matrix character printer of the type having a print head positioned by a motor and including encoder means for producing an encoder signal responsive to the incremental changes in print 10 head position, said encoder signal alternating between two states and changing state when the print head moves a predetermined distance, said printer further comprising encoder signal filter means operable to remove relatively short duration noise signals from the encoder signal and to thereby provide a filtered encoder signal, the encoder filter means comprising means for sampling the encoder signal a plurality of times during the smallest increment of print head movement of interest and for 15 changing the state of the filter encoder only when the encoder signal is in the same state for a majority of such sample times.