Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/185—Joining of semiconductor bodies for junction formation
  • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02002—Preparing wafers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/02587—Structure
  • H01L21/0259—Microstructure
  • H01L21/02592—Microstructure amorphous
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
  • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
  • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
  • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
  • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
  • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
  • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
  • H01L21/28562—Selective deposition
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing

Definitions

• TITLE COMPOS ITE STRUCTURE COMPRISING A USEFUL LAYER IN S IC MONOCRI STALLIN ON A SUPPORT SUBSTRATE IN S IC POLY-CRI STALLIN
• the present invention relates to the field of semiconductor materials for microelectronic components. It relates in particular to a composite structure comprising a useful layer of monocrystalline silicon carbide arranged on a support substrate of polycrystalline silicon carbide, and a process for manufacturing said composite structure. The invention also relates to the polycrystalline silicon carbide support substrate.
• SiC is increasingly widely used for the manufacture of innovative power devices, to meet the needs of rising areas of electronics, such as electric vehicles in particular.
• Power devices and integrated power systems based on monocrystalline silicon carbide can handle much higher power density compared to their traditional silicon counterparts, and this with smaller active area dimensions.
• To further limit the dimensions of power devices on SiC it is advantageous to manufacture vertical rather than lateral components.
• vertical electrical conduction, between an electrode arranged on the front face of the Sic structure and an electrode arranged on the rear face, must be authorized by said structure.
• Monocrystalline SiC substrates intended for the microelectronics industry nevertheless remain expensive and difficult to supply in large sizes. It is therefore advantageous to resort to solutions for transferring thin layers, to produce composite structures typically comprising a useful layer (the thin layer) of monocrystalline SiC (c-SiC) on a lower cost, monocrystalline (c-SiC) support substrate.
• a well-known thin layer transfer solution is the Smart Cut® process, based on implantation of light ions and on assembly, by direct bonding, at a bonding interface.
• the bonding interface must have a resistivity that is as low as possible, preferably less than 1 mohm.cm 2 , or even less than 0.1 mohm.cm 2 .
• Chichignoud et al (“Processing of poly-SiC substrate with large grains for wafer bonding" - Materials Science Forum, vols 527 - 529 , p71 -74 (2006) ) proposes the transfer of a monocrystalline SiC layer onto a poly SiC support substrate -crystalline which has thermal and electrical properties favorable to power microelectronic applications, and physical properties (surface roughness, curvature) compatible with direct bonding.
• the grains of the SiC poly-crystal are chosen to be large (typically greater than 1 cm) and mechanical-chemical polishing for surface preparation before assembly makes it possible to achieve average roughnesses of less than 5 nm.
• Document EP3441506 proposes a p-SiC support substrate on which a c-SiC semiconductor layer can be transferred, via direct bonding.
• the support substrate comprises grains of average size of the order of 10 ⁇ m and has a grain size variation rate between its front and rear faces, reduced to its thickness, of less than or equal to 0.43%; this last characteristic makes it possible to limit the residual stress in the support substrate and therefore its curvature.
• An average roughness of less than Inm is reached at the surface of the support substrate to be assembled with the c-SiC layer.
• the present invention proposes an alternative solution to the solutions of the state of the art, aiming to remedy all or part of the aforementioned drawbacks. It relates to a process for manufacturing a composite structure comprising a useful layer of monocrystalline SiC transferred onto a support substrate of polycrystalline SiC; the invention also relates to said support substrate and the composite structure obtained.
• the invention relates to a method for manufacturing a composite structure comprising a useful layer of monocrystalline silicon carbide placed on a support substrate of polycrystalline silicon carbide, the method comprising: a) a step of providing an initial substrate polycrystalline silicon carbide, having a front face and comprising grains whose average size, in the plane of said front face, is greater than 0.5 ⁇ m; b) a step of forming a surface layer of polycrystalline silicon carbide, on the initial substrate, to form the support substrate, the surface layer being made up of grains whose average size is less than 500 nm and having a thickness comprised between 50nm and 50pm; c) a step of preparing a free surface of the superficial layer of the support substrate to obtain a roughness of less than Inm RMS; d) a step of transferring the useful layer to the support substrate, based on bonding by molecular adhesion, the surface layer being placed between the useful layer and the initial substrate.
• step a) is carried out by a chemical vapor deposition technique, at a temperature between 1100° C. and 1500° C.;
• step a) is performed by a sintering technique or by a physical vapor deposition technique
• step b) comprises a deposition of a layer of polycrystalline silicon carbide and is operated by a technique of chemical vapor deposition at a temperature less than or equal to 1100°C, or even less than or equal to 1000° VS ;
• step b) is carried out in the same equipment as step a) and following the latter, without returning the initial substrate to the ambient atmosphere;
• step b) comprises depositing a layer of amorphous silicon carbide on the initial substrate and recrystallization annealing, to form the surface layer of polycrystalline silicon carbide;
• the surface layer formed in step b) has a dopant concentration of between 1E18/cm 3 and 1 E 21 /cm 3 ;
• step c) comprises mechanical-chemical polishing of the surface layer, involving a removal of between 1 and 10 times the average size of the grains constituting said surface layer;
• step d) comprises the following phases: dl) providing a donor substrate; d2) the introduction of light species into the donor substrate to form a buried fragile plane delimiting, with a front face of the donor substrate, the useful layer to be transferred; d3) assembly of the front face of the donor substrate on the support substrate, by bonding by molecular adhesion; d4) the separation along the buried fragile plane leading to the transfer of the useful layer onto the support substrate;
• the manufacturing process comprises the formation of a second surface layer, of the same nature as the surface layer, on the front face of the donor substrate, before or after phase d2);
• step d) comprises, before assembly phase d3), the deposition of an additional film of a metallic or silicon material on the surface layer of the support substrate and/or on the front face of the donor substrate.
• the invention also relates to a polycrystalline silicon carbide support substrate comprising: an initial substrate comprising grains of silicon carbide, said grains having an average size greater than 0.5 ⁇ m,
• a free surface of the surface layer has a roughness of less than Inm RMS and less than 1 defect/cm 2 , for a measurement of defectiveness by dark field reflection microscopy, at a threshold of 0.5 ⁇ m;
• the thickness of the surface layer is between 200 nm and 5 pm;
• the surface layer has a dopant concentration of between 1E18/cm 3 and 1E21/cm 3 .
• the invention relates to a composite structure comprising:
• the composite structure may further comprise at least one power device on or in the useful layer.
• Figure 1 shows a composite structure developed according to a manufacturing method according to the invention
• FIG. 2d Figures 2a to 2d show steps of a manufacturing method according to the invention
• FIG. 3c [Fig. 3d] Figures 3a to 3d present steps of a preferred mode of the manufacturing method according to the invention.
• the same references in the figures may be used for elements of the same type.
• the figures are schematic representations which, for the purpose of readability, are not to scale.
• the thicknesses of the layers along the z axis are not to scale with respect to the lateral dimensions along the x and y axes; and the relative thicknesses of the layers between them are not necessarily observed in the figures.
• the present invention relates to a method for manufacturing a composite structure 100 comprising a useful layer 10 of monocrystalline silicon carbide (“c-SiC” will be used hereafter to speak of monocrystalline silicon carbide) arranged on a support substrate 20 ( figure 1) .
• the support substrate 20 is made of polycrystalline silicon carbide (“p-SiC” will be used to speak of polycrystalline SiC). It should be noted that, for the production of microelectronic components on and/or in the useful layer 10 of the composite structure 100, it is usually desired that the free face of the useful layer 10 in c-SiC be a silicon face.
• the method firstly comprises a step a) of supplying an initial substrate 21 of polycrystalline silicon carbide, intended to provide its mechanical properties to the support substrate 20 (FIG. 2a).
• the initial substrate 21 represents the major part of the thickness of the support substrate 20. front 21a and a rear face 21b, and of thickness typically between 200 ⁇ m and 800 ⁇ m.
• the initial polycrystalline substrate 21 comprises grains of silicon carbide of the 4H, 6H and/or 3C type.
• the grains have an average size, in the plane of the front face 21a, greater than 0.5 ⁇ m, typically between I ⁇ m and 10 ⁇ m.
• the size of a grain, delimited by the grain joints, corresponds to the largest dimension of said grain, in the plane of the front face 21a.
• the average size of the grains is defined by the average of the sizes of the different grains in the plane of the front face 21a. Very small grains, typically less than 50 nm, are preferentially excluded from the measurement to limit measurement uncertainties.
• p-SiC grains favor good thermal conductivity and are therefore preferred for the initial substrate 21 .
• n-type dopants for example nitrogen dopants.
• Step a) can be performed by known techniques of the state of the art, such as sintering, physical vapor deposition (PVD) or even chemical vapor deposition (CVD).
• Sintered substrates are advantageous due to their relatively low cost.
• the CVD deposition technique is advantageous in that it makes it possible to obtain p-SiC substrates of good quality and of large diameter; the deposition is preferably carried out at a temperature between 1100°C and 1500°C.
• the applicant has carried out numerous tests for preparing the surface of an initial substrate 21 as mentioned above, with a view to transferring a useful layer onto its front face 21a.
• the typical initial RMS roughness on the front face of the initial substrate 21 can vary from a few nanometers to a few micrometers (measurement by AFM atomic force microscopy, on 20 ⁇ m x 20 ⁇ m scans), depending on the production techniques and the smoothing treatments applied by the supplier.
• Mechanical-chemical polishing is necessary to reduce this roughness (target below Inm RMS, or even below 0.5nm RMS), so as to ensure excellent quality of direct bonding by molecular adhesion, and consequently excellent quality of useful layer 10 transferred.
• the manufacturing method according to the present invention comprises a step b) of forming, on the initial substrate 21, a surface layer 22 of polycrystalline silicon carbide of particular morphology, to allow preparation of surface suitable for bonding by molecular adhesion of good quality, but without significantly degrading the thermal and electrical properties expected of the support substrate 20 (FIG. 2b).
• the support substrate 20 formed includes the initial substrate 21 and the surface layer 22, and has a front face 22a (the free face of the surface layer 22) and a rear face 21b (the rear face of the initial substrate 21).
• a layer of the same nature as the surface layer 22, could possibly also be deposited on the rear face 21b of the initial substrate 21 (not shown), in particular to avoid impacting the curvature of the initial substrate 21.
• the surface layer 22 is formed on the front face 21a of the initial substrate 21, without a prior polishing step; the roughness of the initial substrate 21, at the time of the deposition of step b) is therefore typically between 10 nm and 3000 nm RMS.
• the surface layer 22 is composed of silicon carbide grains of the 4H, 6H and/or 3C type. These grains have an average size of less than 500 nm, or even less than 100 nm, typically between 10 nm and 100 nm.
• the size of a grain, delimited by the grain boundaries, corresponds to the largest dimension of said grain, in the plane of the free surface of surface layer 22.
• the average size of the grains is defined by the average of the sizes of the different grains in said plane.
• the p-SiC surface layer 22 advantageously has a concentration of p- or n-type dopants of between 1E18/cm 3 and 1E21/cm 3 , typically between 1E19/cm 3 and 1E20/cm 3 .
• the type and level of doping of the superficial layer 22 are generally chosen respectively to be identical to and higher than those of the initial substrate 21.
• step b) comprises a deposition of silicon carbide in polycrystalline form to form the surface layer 22.
• said deposition is carried out by a chemical vapor deposition technique, in particular at low pressure (LPCVD) and at a temperature less than or equal to 1100° C., or even less than or equal to 1000° C.
• LPCVD low pressure
• surface diffusion decreases, causing an increase in the number of nucleation sites: this promotes the formation of very small p-SiC grains.
• the thickness of the surface layer 22 generally remains low (typically less than 5 ⁇ m), the average size of the grains can easily be kept less than 500 nm, or even less than 100 nm.
• the precursors can be chosen from methylsilane, dimethyldichlorosilane or even dichlorosilane and i-butane, preferably with a C/Si ratio greater than 1.
• step b) has been described as carried out on the initial substrate 21, at the end of step a), it is possible that it be carried out with the same deposition technique and in the same equipment as step a), and following it, without returning the initial substrate 21 to the ambient atmosphere.
• step b) comprises a deposition of silicon carbide in amorphous form, then recrystallization annealing in polycrystalline form to form the surface layer 22.
• the deposition of amorphous SiC can be carried out by a technique of chemical vapor deposition (for example, assisted by PECVD plasma, or assisted by direct liquid injection DLI-CVD), by a technique of physical vapor deposition, or by any other known technique. Recrystallization annealing is then carried out at a temperature typically greater than 900°C, preferably greater than or equal to 1100°C, 1200°C, or even 1400°C. This annealing is carried out so as to obtain a surface layer 22 composed of silicon carbide grains of the 4H, 6H and/or 3C type having an average size of less than 500 nm, or even less than 100 nm, typically between 1 0 nm and 100 nm.
• a technique of chemical vapor deposition for example, assisted by PECVD plasma, or assisted by direct liquid injection DLI-CVD
• Recrystallization annealing is then carried out at a temperature typically greater than 900°C, preferably greater than or equal to 1100°C,
• the latter then comprises a step c) of preparing the free surface 22a of the surface layer 22 to obtain a roughness less than or equal to Inm RMS, advantageously less than or equal to 0.5 nm RMS (figure 2c).
• Step c) can be carried out in different ways:
• the nanometric size of the p-SiC grains of the surface layer 22 is favorable in that it is much lower than the typical planarization length of mechanical-chemical polishing techniques, of the order of 1 jim.
• step c) is based on chemical-mechanical polishing of the surface layer 22, it typically involves a removal of between 1 and 10 times the average grain size of the surface layer 22, depending on the roughness of the initial substrate 21 and the thickness of surface layer 22 deposited.
• Step c) makes it possible to obtain a roughness less than or equal to Inm RMS, preferably less than or equal to 0.5 nm RMS, for example of the order of 0.1 nm to 0.5 nm RMS, over ranges of spatial wavelength ranging from a few tens of nanometers to a few tens of micrometers.
• a conventional cleaning (of the chemical type with potentially brushing), after the smoothing step, is applied to the support substrate 20: the level of defectivity obtained is very low, with less
• the method finally comprises a step d) of transferring a useful layer 10 of monocrystalline silicon carbide onto the support substrate 20, based on bonding by molecular adhesion: the surface layer 22 is then placed between the useful layer 10 and the initial substrate 21 (FIG. 2d).
• a second surface layer can be formed, prior to bonding by molecular adhesion, on the face of the useful layer 10 intended to be bonded to the support substrate 20.
• This has the advantage of assembling layers (the surface layer 22 and the second surface layer) of the same nature, namely in p-SiC with nano-grains; such a configuration can improve the quality of direct bonding.
• step d) of the process involves implantation of light species according to the principle of the Smart Cut® process.
• a donor substrate 1 in monocrystalline silicon carbide, from which the useful layer 10 will come is provided (FIG. 3a).
• the donor substrate 1 is preferably in the form of a wafer with a diameter of 100 mm or 150 mm or even 200 mm (identical to that of the support substrate 20) and with a thickness typically comprised between 300 ⁇ m and 800 ⁇ m. It has a front face 1a and a rear face 1b.
• the surface roughness of the front face 1a is advantageously chosen to be less than Inm RMS, or even less than 0.5 nm RMS, measured by atomic force microscopy (AFM) on a 20 ⁇ m ⁇ 20 ⁇ m scan.
• AFM atomic force microscopy
• a carbon face will be chosen as the front face of the donor substrate 1.
• the donor substrate 1 can be of 4H or 6H polytype, and have an n or p type doping, depending on the needs of the components which will be produced on and/or in the useful layer 10 of the composite structure 100.
• a second phase d2) corresponds to the introduction of light species into the donor substrate 1 to form a buried fragile plane 11 delimiting, with a front face of the donor substrate 1, the useful layer 10 to be transferred (FIG. 3b).
• the light species are preferably hydrogen, helium or a co-implantation of these two species, and are implanted at a determined depth in the donor substrate 1, consistent with the thickness of the intended useful layer 10 .
• These light species will form, around the determined depth, microcavities distributed in a thin layer parallel to the free surface la of the donor substrate 1, ie parallel to the plane (x,y) in the figures. This thin layer is called the buried fragile plane 11, for simplicity.
• the implantation energy of the light species is chosen so as to reach the determined depth.
• hydrogen ions will be implanted at an energy of between 10 keV and 250 keV, and at a dose of between 5 E 16/cm 2 and 1 E 17/cm 2 , to delimit a useful layer 10 having a thickness of 1 order of 100nm to 1500nm.
• a protective layer could be deposited on the front face 1a of the donor substrate 1, prior to the ion implantation step. This protective layer can be composed of a material such as silicon oxide or silicon nitride for example. It is removed prior to the next phase.
• a second surface layer (of the same nature as the surface layer 22) can be formed on the front face la of the donor substrate 1, before or after the second phase d2) of introduction of the light species .
• the formation and preparation of this second surface layer may be carried out under the aforementioned conditions of steps b) and c).
• the implantation energy (and potentially the dose) of the light species will be adjusted when crossing this additional layer.
• care will be taken to form this second superficial layer by applying a thermal budget lower than the bubbling thermal budget, said bubbling thermal budget corresponding to the appearance of blisters on the surface of the donor substrate 1 due to growth and excessive pressurization of the microcavities in the buried fragile plane 11.
• the transfer step d) then comprises a third phase d3) of assembling the front face 1a of the donor substrate 1 on the front face 22a of the support substrate 20, by bonding by molecular adhesion, along a bonding interface 3 ( Figure 3c).
• a bonding interface 3 Figure 3c
• direct bonding by molecular adhesion does not require an adhesive material, bonds being established on the atomic scale between the assembled surfaces.
• Several types of bonding by molecular adhesion exist, which differ in particular by their conditions of temperature, pressure, atmosphere or treatments prior to bringing the surfaces into contact.
• the assembly phase d3) may comprise, prior to bringing the faces 1a, 22a to be assembled into contact, conventional sequences of chemical cleaning (for example, RCA cleaning), surface activation (for example, by oxygen or nitrogen plasma) or other surface preparations (such as cleaning by brushing (“scrubbing”), likely to promote the quality of the bonding interface 3 (low defectivity, high adhesion energy).
• chemical cleaning for example, RCA cleaning
• surface activation for example, by oxygen or nitrogen plasma
• other surface preparations such as cleaning by brushing (“scrubbing”), likely to promote the quality of the bonding interface 3 (low defectivity, high adhesion energy).
• the low level of roughness and defectiveness of the front face 22a of the support substrate 20 is particularly advantageous to obtain a high quality bonding interface 3.
• the quality of the bonding direct can be further improved due to the assembly of two surfaces of the same polycrystalline nature, or even of the same polytype, preferably 3C.
• step d) comprises, before assembly phase d3), the deposition of an additional film in a metallic material or in amorphous or polycrystalline silicon, on the prepared front face 22a of the surface layer 22 and/or on the front face of the donor substrate 1.
• the metallic material may be chosen from tungsten, nickel, titanium, etc.
• the surface roughness of the free face 22a of the surface layer 22 being very low, the thickness of this additional film is advantageously limited, typically between a few nanometers and a few tens of nanometers.
• a fourth step d4) comprises the separation along the buried fragile plane 11, which leads to the transfer of the useful layer 10 onto the support substrate 20 (FIG. 3d).
• the separation along the buried fragile plane 11 usually takes place by applying a heat treatment at a temperature between 800°C and 1200°C. Such a heat treatment induces the development of cavities and microcracks in the buried fragile plane 11, and their pressurization by the light species present in gaseous form, until the propagation of a fracture along said fragile plane 11 .
• a mechanical stress can be applied to the bonded assembly and in particular at the level of the buried fragile plane 11, so as to mechanically propagate or help to propagate the fracture leading to separation.
• the semiconductor structure 100 comprising the support substrate 20 and the useful layer 10 transferred in monocrystalline SiC, and on the other hand, the remainder 1' of the donor substrate.
• the level and the type of doping of the useful layer 10 are defined by the choice of the properties of the donor substrate 1 or can be adjusted later via known techniques for doping semiconductor layers.
• the free surface 10a of the useful layer 10 is usually rough after separation: for example, it has a roughness of between 5 nm and 10 Onm RMS (AFM, scan 20 ⁇ m ⁇ 20 ⁇ m).
• Cleaning and/or smoothing phases can be applied to restore a good surface state (typically, a roughness lower than a few Angstroms RMS on a 20pm x 20pm scan by AFM).
• these phases can comprise a mechanical-chemical smoothing treatment of the free surface of the useful layer 10 .
• a removal of between 50 nm and 300 nm makes it possible to effectively restore the surface state of said layer 10 .
• They may also comprise at least one heat treatment at a temperature of between 1300° C. and 1800° C.
• Such a heat treatment is applied to evacuate the residual light species from the useful layer 10 and to promote the rearrangement of the crystal lattice of the useful layer 10 .
• I t also makes it possible to reinforce the bonding interface 3 .
• a heat treatment in this temperature range can also induce an increase in the size of the grains of the surface layer 22 (and of the second surface layer, if it is present) which is of interest for improving the thermal conductivity properties of the composite structure 100 .
• step d) of transfer can comprise a step of reconditioning the remainder 1' of the donor substrate with a view to reuse as donor substrate 1 for a new composite structure 100 .
• Mechanical and/or chemical treatments similar to those applied to the composite structure 100, can be implemented at the level of the front face a of the remaining substrate 1'.
• the reconditioning step can also comprise one or more treatments of the edges of the remaining substrate 1' and/or of its rear face 1'b, by mechanical-chemical polishing, by mechanical rectification, and/or by dry or wet chemical etching.
• the invention also relates to the support substrate 20, resulting from steps a) and b) of the manufacturing method detailed above (FIG. 2b), which comprises:
• an initial substrate 21 comprising grains of silicon carbide, said grains having an average size greater than 0.5 ⁇ m,
• a layer of the same nature as the surface layer 22 can also be present on the rear face and the edges of the initial substrate 21, and allow the encapsulation of said substrate 21: a low quality of the initial substrate (for example sintered substrate) can thus be chosen to limit the costs of the support substrate 20.
• the free surface 22a of the superficial layer of the support substrate 20 has a roughness of less than Inm RMS, or even less than or equal to 0.5 nm RMS, and less than 10 defects/ cm 2 , or even less than 1 defect/cm 2 , by measuring defectivity by reflection microscopy in a dark field, at a threshold of 0.5 ⁇ m.
• These characteristics make the support substrate 20 particularly suitable for the implementation of an assembly step by bonding by molecular adhesion, between a useful layer 10 (or a donor substrate 1) in monocrystalline silicon carbide (or in p-SiC when a second surface layer is present) and the front face 22a in p-SiC with nano-grains.
• the invention relates to the composite structure 100 resulting from the aforementioned manufacturing process, which comprises:
• Such a composite structure 100 is extremely robust to heat treatments at very high temperatures likely to be applied to improve the quality of the useful layer 10 or to manufacture components on and/or in said layer 10.
• the composite structure 100 according to the invention is particularly suitable for producing one (or more) high-voltage microelectronic component(s), such as for example Schottky diodes, MOSFET transistors, etc.
• the composite structure 100 responds more generally to power microelectronic applications, by allowing a excellent vertical electrical conductivity, good thermal conductivity and providing a useful layer of high quality c-SiC.

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• Recrystallisation Techniques (AREA)

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• 2021
  • 2021-10-05 FR FR2110493A patent/FR3127842B1/fr active Active
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