Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
  • H01L28/10—Inductors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
  • H01L23/64—Impedance arrangements
  • H01L23/645—Inductive arrangements
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present invention relates to an electrical conductor in an integrated circuit (IC) having a low loss to a substrate and a method of making such a conductor, in particular to a method of fabricating spiral inductors and also to an integrated circuit inductor.
• IC integrated circuit
• CMOS and BiCMOS circuits are today used for high-speed electronic applications in the 1 - 2 GHz frequency range and they replace circuits previously only possible to implement using devices based on materials found in column III-V in the periodic table.
• Inductor elements are often needed in high-frequency circuits when forming blocks like resonators and filters.
• a problem common to all integrated circuit devices is how to achieve integrated circuit inductors having high quality factors, Q, and high operating frequencies, the operating frequency being limited by the resonance frequency.
• the Q- value of the inductor is reduced.
• the Q-value can be increased by a factor of two by such a removal.
• the removal can be in the form of a silicon etching process, giving air gaps of several hundred micrometers, see J.Y.C. Chang, A.A. Abidi, M. Gaitan, "Large Suspended Inductor on Silicon and Their Use in a 2 ⁇ m CMOS RF Amplifier", IEEE Transactions on Electron Devices Vol. 40, No. 5, p. 246, May 1993, but such removals are not regarded as feasible in large production volumes or compatible with silicon IC processes.
• Inductor elements are usually laid out as square-spirals metal stripes, see for instance N.M. Nguyen, R.G. Meyer, "Si IC- Compatible Inductor and LC Passive Filter", IEEE Journal of Solid-State Circuits Vol. 25, No. 4, p. 1028, August 1990.
• ICs usually comprise multiple metal layers and up to five layers is now common in complex Very Large-Scale Integration (VLSI) circuits. At least two metal layers are required for spiral layouts, one for the very spiral and one for closing the structure, i.e. for forming a conductor path from the centre of the spiral to an output terminal at the edge of the inductor.
• the uppermost ones of the metal layers usually have a lower resistivity because of larger thicknesses and should therefore be used.
• a 10% reduction of the resistance value can be obtained for an equal inductance value, resulting in an increased Q-value of the inductor formed of the same magnitude.
• the circular layout is not very well suited for common software used for Computer Aided Design (CAD), but can be replaced by an octagonal configuration without increasing the resistance value of the inductor, see S. Chaki, S. Aono, N. Andoh, Y. Sasaki, N. Tanino, "Loss Reduction of a Spiral Inductor", Technical Report of IEICE, p. 61, ED93-166, MW93-123, 1CD93-181(1994-01) .
• a better way of reducing the resistance is to make an inductor having parallel spiral paths in adjacent layers, e.g. to connect the uppermost metal layers in parallel.
• the Q-value of the inductor can in this way be increased 1.5 - 2 times, at the expense of a lower resonance frequency because of the decreased isolation thickness.
• the inductance value is made larger.
• the capacitance of the inductor spiral to the substrate will however also increase, leading to a lower resonance frequency limiting the useful frequency range of operation of the inductor.
• U.S. patent 5,446,311 describes such a structure having an inductor formed in multiple metal layer levels in order to reduce the inductor resistance.
• Japanese patent application JP A 07-106 514 discloses a structure similar to the structure described in U.S. patent 5,446,311, in which the loss due to electrostatic capacity is reduced and the Q-value is increased by forming an inductor which has two spiral metallic paths formed in different metallization layers and which are interconnected by a third layer.
• Deep trenches are applied in modern IC processes for isolation of devices.
• the advantages of such trenches are reduced parasitic capacitances and reduced device spacing.
• a deep, 5 - 20 ⁇ m, and narrow, 1 - 2 ⁇ m, trench is obtained by means of dry etching and refilling it with oxide and undoped poly-silicon or a dielectric material. After the refilling process, the surface of the substrate will be coated with a layer of refilling material and thus be substantially flat so that e.g. metal layers can be placed over the trenches without any restrictions.
• U.S. patents 5,336,921 and 5,372,967 a method of form ⁇ ing an inductor in a vertical trench is described.
• the inductor described aims at eliminating some of the problems encountered with conventional, horizontal inductors on integrated circuits by means of providing a method of fabricating vertical inductors in the shape of an inductive coil in a trench.
• U.S. patent 5,095,357 discloses an inductive structure having low parasitic capacitances for direct integration in semiconductor integrated circuits.
• trenches filled with an isolating material under the spiral inductor layout which increase the effective distance from the metal to the semiconducting substrate.
• the losses in the substrate of the integrated device and the capacitance to the substrate will then decrease.
• the Q-value and the resonance frequency of the inductors will increase accordingly.
• the filled trenches may be enough to achieve acceptable Q-values and resonant frequencies.
• the spiral should be laid out in the uppermost of the metal layers, furthermore lowering the parasitic capacitance to the substrate, already lowered by the filled trenches in the substrate, giving a higher self-resonance frequency.
• the uppermost layer usually has the lowest sheet resistivity, which also will increase the Q-value.
• the reduced substrate capacitance can also be utilized to connect the upper metal layers in parallel, e.g. metal layer three and four from the substrate for the spiral, metal layer two from the substrate for the cross-under, thus increasing the Q-value by another factor of 1.5 - 2.
• Trenches can also be used under any metal line or bond pad in order to reduce parasitic capacitance and reduce losses to the substrate.
• the inductor is produced in or on an electrically semiconducting or semi- isolating substrate and in particular by depositing or coating various layers on a silicon substrate.
• the inductor can generally comprise a structure of electrical conductor paths extending substantially in one plane or in several, for example substantially parallel planes. Before the conductor paths are produced, in particular before the inductor metal paths are applied to or deposited on the substrate, trenches are etched in the substrate extending from the substrate surface at suitable locations.
• the locations of the trenches are selected so that the inductor paths will be located above and close to the trenches and generally so that the trenches will intersect the hypothetical electrical current paths inside the material of the substrate, when the inductor is used and there is an electrical current flowing therein and no trenches would have been made in the substrate, this configuration of the trenches then attenuating or hindering the currents inside the substrate.
• the trenches are filled with an electrically isolating material, in particular a dielectric or semiconducting material, in order that the following process steps when making the conductor paths will experience a substantially flat surface.
• the trenches may then advantageously be arranged so that they occupy the largest possible area under the inductor, that is they can be densely spaced. Also, the trenches are preferably arranged in a structure of substantially parallel trenches or a in meshlike structure.
• the integrated circuit having an inductor integrated therein thus comprises, in the most general aspect, thin plates of a material that is a worse or poorer electrical conductor than the substrate, these "plates" being the filled trenches as described above.
• the plates are arranged in the substrate in some region at the conductor paths, e.g. under the inductor paths, but also configurations having plates between planes of conductor paths and above the inductor paths are conceivable in complex multi ⁇ layer structures.
• the plates may in any case be arranged substantially perpendicularly to the plane or planes of the conductor paths or have any other suitable geometrical configuration in order to make the undesired current paths, when the circuit is used and the desired current flows in the conductor paths, in the substrate from one place at the conductor to another place thereat, long to give these current paths a large resistance, this configuration reducing these currents significantly.
• the plates may thus be arranged substantially in parallel to each other, at least in subsets of the total set of all plates.
• the plates can then, as viewed in a direction from the conductor paths, for example be arranged in a meshlike structure formed of two subsets of parallel plates.
• the plates can have a suitable thickness in order to sufficiently cut off the current paths inside the substrate and restricting the current in the substrate to have only long paths inside the substrate.
• the thickness of the plates may e.g. be substantially equal to the thickness of the conductor paths for typical plate materials.
• the width or depth of the plates, as seen from a conductor path, should also be sufficient to restrict the current paths inside the substrate.
• the plates are then also preferably densely arranged or arranged to have a dense or close spacing, so that the interspace between neighbouring plates is small, this also limiting the current paths and thus the currents inside the substrate material from a place on a conductor to a place thereon located very closely.
• the spacing could be substantially equal to 2 or a few times, e.g. 5, the thickness of the plates. This may also be worded in the way that the plates or trenches are arranged to occupy the largest possible area as seen from the inductor, the cross-sectional area of each plate however being small as seen in this view.
• An integrated circuit can as above, generally, comprise a metal conductor formed on or in an electrically semiconducting or semi-isolating substrate, in particular on a silicon substrate, the conductor for example being a part of an inductor path.
• plates or trenches can be arranged in a region or region adjacent the conductor as described above, for reducing losses in the conductor to the substrate.
• the plates can then as above for example be arranged substantially perpendicularly to the plane of the conductor or the electrical current path therein.
• the plates may be filled trenches arranged to generally cross the electrical current path in the metallic conductor and preferably to extend in a direction substantially perpendicular to said current path and/or in a longitudinal direction of the conductor.
• Fig. 1 is a highly schematic, rectangular spiral layout as seen from above for an integrated circuit inductor according to state of the art
• FIG. 1 - FIG. 2a and 2b are schematic cross sectional views of the inductor in fig. 1,
• FIG. 3 is a schematic cross sectional view of an integrated circuit inductor
• - Fig. 4 is a trench pattern to be used on a substrate
• Fig. 5 shows a trench pattern under a metal conductor line.
• inductor is in this case formed in a fourth, as counted bottom up, uppermost metal layer 101 by a spiral, electrically conductive path comprising a number of rectangular turns, the number of turns typically being between 5 and 10.
• a lower metallization layer 103 in this case the third layer, is used for closing the spiral structure by means of a cross-under.
• fig. 1 The inductor structure of fig. 1 is also shown in cross section- al views in figs. 2a and 2b, the sections being taken along lines a - a and b - b in fig. 1, respectively.
• fig. 2a shows the metal 201 of the fourth metal layer forming the rect ⁇ angular turns. Underneath the metal spiral 201, there is an oxide layer 203 applied to a silicon substrate 205.
• the thick ⁇ ness of the metal layer is typically in the range of 1 - 2 ⁇ m and the thickness of the oxide layer is typically 6 ⁇ m and the width of the conductor paths can be about 5 ⁇ m, the distance between neighbouring paths being the same order of magnitude as the width of the paths.
• the third metal layer 207 is shown in fig. 2b, which is a cross sectional view along the line b - b in fig. 1, also the third metal layer 207 is shown.
• the third metal 207 layer constitutes a an electrically conductive cross- under for completing the coil of the inductor.
• the fourth metal layer 201 and the third metal layer are connected via electri ⁇ cally conductive connectors 209. These connectors can be made in a separate step using etching and metallization or, they can be made by first making suitable holes and then filling the holes with the material of the fourth layer.
• Fig. 3 shows a cross sectional view of an inductor 305 having an improved isolation, the inductor paths being formed in the top ⁇ most, fourth metal layer on a silicon substrate 301.
• an etching operation for producing a trench has been performed on the silicon substrate 301 followed by a refilling of the trenches with an isolating material, i.e. a material that has a lower electrical conductivity than that of the substrate.
• the refilled trenches 303 serve as to increase the effective distance from the metal layer of the inductor to the semi ⁇ conducting substrate. The losses in the substrate and the capacitance to the substrate will then decrease.
• the Q-value and the self-resonance frequency of the inductors will also increase accordingly.
• the trenches can be made substantially as in the recited con ⁇ ventional methods used in modern IC processes for device isolation. Deep and narrow trenches can thus be produced by dry etching and refilling the etched voids with an isolating material like silicon oxide and undoped poly-silicon or a dielectric material. The surface above the substrate produced in the refilling process will then still be substantially flat.
• the trenches can have widths of about 1 - 2 ⁇ m and depths of about 5 - 20 ⁇ m. The width of the substrate material between neigh ⁇ bouring trenches may be as small as is practically possible, for instance 2 - 4 ⁇ m.
• the trenches are arranged in some suitable pattern to cross the overlying conductor paths.
• Fig. 4 shows a view of a portion of a substrate 401 from above in which a preferred pattern of trenches 403 has been etched.
• the trench pattern is then used under an inductor for reducing the losses to the substrate.
• the pattern comprises a first set of several straight identical trenches located in parallel to each other and having an equal spacing and also a second set of identical trenches located in parallel to each other and equally spaced, the trenches of the second set being perpendicular to those of the first set.
• the trenches should always be so long and located that they pass beyond the outermost inductor turn into the free material surrounding the inductor.
• the trench pattern used can however have any meshlike shape, and it is generally desirable to remove as much of the substrate as possible.
• fig. 5 shows how the method as described herein can be used in another application.
• trenches 501 are etched under a metallization line 503 in order to reduce the parasitic capacitance and reduce losses to the substrate.
• the trenches may have the same dimensions as discussed above and they are arranged to cross under the electrically conductive path at substantially straight angles. They can be located symmetrically under the conductor path and extend to each side of the path as long as is required or possible, e.g. some 4 - 10 ⁇ m.
• This trench configuration or preferably the meshlike con ⁇ figuration of fig. 3 can be also used for reducing losses of bond pads.

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• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
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• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
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• 1996
  • 1996-05-31 SE SE9602191A patent/SE510443C2/sv not_active IP Right Cessation
• 1997
  • 1997-05-30 KR KR1019980708627A patent/KR100298480B1/ko not_active IP Right Cessation
  • 1997-05-30 EP EP97926345A patent/EP0902974A1/de not_active Withdrawn
  • 1997-05-30 CA CA002256763A patent/CA2256763A1/en not_active Abandoned
  • 1997-05-30 CN CN97195081A patent/CN1220778A/zh active Pending
  • 1997-05-30 WO PCT/SE1997/000954 patent/WO1997045873A1/en not_active Application Discontinuation
  • 1997-05-30 AU AU31130/97A patent/AU3113097A/en not_active Abandoned
  • 1997-05-30 JP JP09542247A patent/JP2000511350A/ja not_active Abandoned

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