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EP0730214B1 - Stromspiegel in MOS-Technik mit weit aussteuerbaren Kaskodestufen - Google Patents

Stromspiegel in MOS-Technik mit weit aussteuerbaren Kaskodestufen Download PDF

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Publication number
EP0730214B1
EP0730214B1 EP96102646A EP96102646A EP0730214B1 EP 0730214 B1 EP0730214 B1 EP 0730214B1 EP 96102646 A EP96102646 A EP 96102646A EP 96102646 A EP96102646 A EP 96102646A EP 0730214 B1 EP0730214 B1 EP 0730214B1
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EP
European Patent Office
Prior art keywords
current
input
node
source
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP96102646A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0730214A3 (de
EP0730214A2 (de
Inventor
Ulrich Dr.-Ing. Theus
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
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TDK Micronas GmbH
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Filing date
Publication date
Application filed by TDK Micronas GmbH filed Critical TDK Micronas GmbH
Publication of EP0730214A2 publication Critical patent/EP0730214A2/de
Publication of EP0730214A3 publication Critical patent/EP0730214A3/de
Application granted granted Critical
Publication of EP0730214B1 publication Critical patent/EP0730214B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a current mirror in MOS technology with widely controllable Cascode stages, containing a power bank, which are controlled by a control circuit from one Differential current is controlled that at a circuit node between the Current mirror input and an associated, high-resistance cascode output tapped is, cf. the preamble of claim 1.
  • V DS ⁇ (V GS - V T ) with the n-channel transistor V DS ⁇ (V GS - V T ) with the p-channel transistor.
  • the main cause of the critical operating state of the n-channel current mirror in FIG. 1 is the gate potential of the common n-channel current bank control line, which is connected directly to the current mirror input. Since the series connection of the two drain-source current paths of the cascoded current mirror input is also located at this connection point, it can be seen immediately that the gate potential of the current bank transistor t1, which is also referred to below as the current mirror control transistor, by the drain-source voltage of the cascode transistor t2 is higher than its drain potential.
  • V DSt2 denotes the drain-source voltage of the cascode transistor t2
  • V Tt1 denotes the threshold voltage of the current bank transistor t1.
  • the size of the threshold voltage V T is predetermined by the technology, whereby its negative temperature coefficient unfortunately just runs counter to the positive temperature coefficient of the effective gate voltage - for the same current but increasing crystal temperature.
  • a certain remedy is the known circuit according to FIG. 2, in which the gate electrode the current mirror control transistor is controlled by a control circuit, whose input is fed by a signal tapped at the current mirror input.
  • the input current path of the actual current mirror becomes, so to speak electronically separated and a residual current from the supplied Current mirror input current and the output current of the current mirror control transistor educated. If the differential current becomes zero, then the input current supplied equal to the output current of the current mirror control transistor and thus the setpoint of Control process reached.
  • This measure sets the control voltage for the Gate connection of the current mirror control transistor and thus the potential of common power bank control line by itself to an uncritical value.
  • a simple consideration of the resulting potential relationships shows that the potential of the common power bank control line significantly lower than the potential of the Auxiliary voltage source can be and thus the desired state of saturation for the Current mirror control transistor and ensured for the cascode stages of the current mirror becomes.
  • control circuit contains a negative feedback operational amplifier, is the critical stability behavior, which can lead to control loop vibrations without suitable damping measures.
  • the usual damping measures influence the frequency behavior of the current mirror, so that it becomes too slow for many signal applications.
  • the stabilization circuit requires at least one additional capacitor, which is particularly disadvantageous in the monolithic integration of the circuit.
  • the Saturation operating state is determined by means of the gate-drain voltage value of the Cascode transistor monitored in the current mirror input. As long as its drain voltage is higher than its gate voltage this transistor works and because of that technological equality everyone else in saturation, that is, with a high-impedance output. Will this normal saturation operation due to temperature changes or more common Leave tolerances in the MOS manufacturing process, then without that Control circuit the drain voltage of the cascode transistor below the gate voltage sink and the cascode transistor goes into low-resistance switch mode. The Control circuit, to which this gate-drain voltage is supplied as a sensor signal however, the voltage equality of gate and drain, so that the saturation condition always remains.
  • the object of the invention characterized in claim 1 is therefore an improved Regulation for a current mirror in MOS technology with widely controllable cascode levels specify, with the aim of keeping the required circuitry low and the Keep the speed of the current mirror as high as possible.
  • control circuit as an essential unit contains current-controlled current source, whose control input with the residual current tap in the current mirror input and their current output with the common Strombank control line is connected, the control time constant by a capacitive load of the power source output is set.
  • the use of a current source in the control circuit has the advantage that the capacitive load of the common power bank control line, which depends on the size and The number of connected gate electrodes can be very different in size dominant pole of the entire control loop and therefore essentially that Loop behavior determined. The other pole points act behind it back. As a rule, the capacitive load of the common is unnecessary Bank control line an additional internal or external capacity.
  • the stability behavior also depends on the loop gain and thus on Current transformation ratio of the current-controlled current source. It is therefore advantageous if the current transformation ratio does not exceed 10, a preferred value is approximately 1, so that the input and output currents approximately are the same size. About the W / L ratio of that with the power source and power bank coupled transistors, the current transformation ratio can be easily adjusted.
  • the potential of the low-impedance power source control input is determined in the type of a gate circuit, the reference input, the gate connection, at a Reference voltage and its low-impedance signal input, the source connection, forms the power source control input. It is pointed out that the input and Output of the current source, hence the output of the voltage follower, in bidirectional direction works, i.e. the direction of flow of the respective currents can be positive or negative.
  • a power source can, for example, two interacting complementary current mirrors contain an arrangement that especially the CMOS technology is taken into account.
  • Such an arrangement connects for example, an n- and a p-channel current mirror with one another such that the Output of the p-channel current mirror directly with the input of the n-channel current mirror or is connected via cascode transistors.
  • the output of the n-channel current mirror is the same with the input of the p-channel current mirror directly or via Cascode transistors connected.
  • Via the cascode transistors in the two cross current paths currents can be coupled in with low resistance and coupled out with high resistance.
  • Such a current mirror arrangement is therefore particularly suitable for Residual current formation, where the differential current can be positive or negative. Capacitive influences on the frequency behavior of current mirrors are inherently known from DE 42 01 155 C1, which has a switchable current mirror with MOS transistors of the same channel type.
  • the known current mirror in Fig. 1 causes one from a source, not shown generated input current ie at an n-channel current bank mb with transistors t1, t3 is mirrored as the output current ia.
  • the input current is also via a cascode transistor t2 led out between the current mirror input em and the drain of Current bank transistor t1, which also serves as a current mirror control transistor.
  • the common gate potential of the cascode transistors t2, t4 is connected to an auxiliary voltage uh, by means of an auxiliary current ih and an n-channel transistor connected as a diode t5 is formed.
  • the common power bank control line cl of the power bank mb is to the Drain electrode of the cascode transistor t2 connected. It is easy to see that by connecting the two n-channel transistors t2, t1 in series, the drain potential of the Current bank transistor t1 compared to its gate potential at certain Operating states is too small, so that the presumed saturation of the transistors t1 and t2 is no longer present, whereby the current symmetry between the Current bank transistors t1, t3 and possibly no further current bank transistors remains more protected.
  • the common power bank control line is controlled by a control circuit r.
  • the Auxiliary voltage uh for the two cascode transistors t2, t4 is identical to that Realization according to FIG. 1. More complex circuits that stabilize the Auxiliary voltage uh serve are known, but have with the actual invention None to do.
  • the common one Current bank control line connected to the output of an operational amplifier op, its non-inverting input with the current mirror input em and its inverting input is coupled to a reference voltage Ur.
  • the non-inverting input is common via an RC element R, C Ground reference line M connected.
  • the current mirror input em does not depend on the temporally arbitrary input current ie represented source fed. If both currents ie, i1 are not equal, then this must be one Differential current id result that can be tapped at a first circuit node k1 is or must be fed into this point.
  • operational amplifiers assume that the output voltage independent of the common mode voltage at the two operational amplifier inputs is.
  • this decoupling means that the voltage at the current mirror input em is also higher than the voltage of the power bank control line.
  • the RC element R, C is necessary in order to Ensure stability of the circuit.
  • the drain-source current changes as a result of the control action i1 and adjusts to the input current ie.
  • the control goal has been achieved when no more differential current id flows and thus the current bank control line cl her has reached the right potential. With the size of the current i1 it goes without saying also the output current ia of the current bank mb and thus the actual current level m changed proportionally.
  • the circuit according to FIG. 2 is very complex, whereby for stationary or slowly changing input currents ie the behavior of the Circuit is satisfactory. However, if the input currents change quickly and the output currents should generally follow these changes, then that is temporal Behavior of the control loop.
  • the first circuit node k1 is e.g. on high-impedance decoupling point and forms c1 with the associated parasitic capacitance a first pole.
  • a second pole is through the negative feedback Operational amplifier op and the RC element R, C formed, the Frequency feedback of the operational amplifier through the capacitor c2 is indicated schematically. Is in the normal frequency range of the operational amplifier its output signal in any case 90 ° with respect to its input signal in phase turned.
  • the gate capacitances c3 of the current bank transistors t1, t3 and associated parasitic capacitances represent a third pole, which in connection with the Output resistance of the operational amplifier takes effect.
  • the three time constants of the poles cause a phase shift that makes the control loop easily vibrate can bring. This is particularly critical if the resulting ones Zero points / poles for the control loop are adjacent in frequency and the Loop gain there is still big enough.
  • Fig. 3 is an embodiment of a current mirror according to the invention shown. Circuit parts that are identical to those in Fig. 1 or Fig. 2 are with The same reference numerals are shown, in particular the circuit parts of the actual current level m.
  • the control circuit r contains one current-controlled current source q, the low-impedance control input with the Differential current id is fed and its high-impedance output, the circuit node k3, is directly connected to the current bank control line cl.
  • the use of a Current source q for controlling the current bank transistors t1, t3 is an essential one Point of the invention, because it is generally assumed that MOS transistors are voltage and not current controlled via the gate electrodes and their Control should therefore be as low-resistance as possible, especially if the up or Discharge of the gate capacities should be very fast.
  • the controlled output current of the Current source q is used at Strombank mb as gate current ig for the gate capacities c3 to the current bank mb the fluctuations of the input current ie track.
  • the drive potential u3 becomes the drive current ig Current bank transistors t1, t3 changed.
  • the differential current id injected into the circuit node k2 disturbs the specified current balance of the interacting current mirrors m1, m2 and generates a differential current ig, which is tapped at a circuit node k3 can. This is the gate current ig.
  • the high-resistance tap k3 is by the common connection point of the drain connections of an n-channel transistor t13 and of the p-channel transistor t9 is formed.
  • the n-channel transistor t13 is the output transistor of the n-channel current mirror m2 and the transistor t9 is the p-channel output transistor the four transistor cell.
  • the circuit node k3 thus represents the output of the Current source q represents the functioning of the actual current level m and the To be able to better describe current source q in separate form is in FIGS associated description of the common connection point k1, k2 as a separate Circuit nodes k1, k2 shown.
  • the potential u4 of the reference voltage source Ur determines the level as described u2 of the current mirror input em.
  • the auxiliary voltage uh By appropriate choice of the auxiliary voltage uh can in a simple way the gate drive potential for the cascode stages t2, t4 lower than the current mirror input voltage u2 can be set.
  • the output voltage u3 the Current source q corresponds to the saturation voltages of transistors t13 and t9 the entire range of voltage u2.
  • the quiescent current of the two current mirrors m1, m2 connected in chain is determined by the Current source currents i6, i8 set in the input of the voltage follower sf.
  • An internal one Coupling the two current sources makes currents i6 and i8 the same size. Since the Potentials of the circuit nodes k2 and k4 are equal to one another, the n-channel transistors t6, t7 and the p-channel transistors t8, t9 are each viewed as current mirrors that the current source current i6 or the same current i8 on the respective Mirror output.
  • the differential current id is superimposed on these currents Direction via the current mirror m1, m2 and in the other direction via the transistor t9 is supplied to the circuit node k3. If the current mirror m1, m2 each one Current ratio 1: 1, then the tapped output current is ig identical to the supplied differential current id. They are also more complex Current source circuits can be implemented that are one of 1 between the input and output have different current transformation ratios, for example between 0.1 and 10. This affects the charging or discharging of the current bank transistors t1, t3, but also changes the stability reserve.
  • the schematic representation of the auxiliary voltage source t5, the reference voltage source Ur and the current sources for the currents i6, i8 in FIG. 3 include known measures to improve the respective circuit function, e.g. the use of Bandgap circuits for generating stable voltages or currents.
  • Further 3 shows only a single one of the actual current mirror m Output current path for the current ie. Other current outputs, also with any Current translation ratios are not shown for clarity.
  • the 3 contains q CMOS transistors in the current-controlled current source.
  • a current-controlled current source is also in pure n or. P-channel technology can be implemented.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Electromagnetism (AREA)
  • Nonlinear Science (AREA)
  • Automation & Control Theory (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Control Of Electrical Variables (AREA)
EP96102646A 1995-03-01 1996-02-22 Stromspiegel in MOS-Technik mit weit aussteuerbaren Kaskodestufen Expired - Lifetime EP0730214B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19507155A DE19507155C1 (de) 1995-03-01 1995-03-01 Stromspiegel in MOS-Technik mit weit aussteuerbaren Kaskodestufen
DE19507155 1995-03-01

Publications (3)

Publication Number Publication Date
EP0730214A2 EP0730214A2 (de) 1996-09-04
EP0730214A3 EP0730214A3 (de) 1997-07-16
EP0730214B1 true EP0730214B1 (de) 2001-10-17

Family

ID=7755363

Family Applications (1)

Application Number Title Priority Date Filing Date
EP96102646A Expired - Lifetime EP0730214B1 (de) 1995-03-01 1996-02-22 Stromspiegel in MOS-Technik mit weit aussteuerbaren Kaskodestufen

Country Status (5)

Country Link
US (1) US5654629A (ko)
EP (1) EP0730214B1 (ko)
JP (1) JP3880649B2 (ko)
KR (1) KR960036010A (ko)
DE (2) DE19507155C1 (ko)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5801523A (en) * 1997-02-11 1998-09-01 Motorola, Inc. Circuit and method of providing a constant current
JP3315652B2 (ja) * 1998-09-07 2002-08-19 キヤノン株式会社 電流出力回路
DE19903577C2 (de) * 1999-01-29 2000-11-23 Micronas Intermetall Gmbh Schaltungsanordnung eines integrierten Stromspiegels
JP2007508771A (ja) * 2003-10-15 2007-04-05 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ バイポーラ信号の増幅用電子回路
JP4170963B2 (ja) * 2004-07-22 2008-10-22 浜松ホトニクス株式会社 Ｌｅｄ駆動回路
US8786359B2 (en) * 2007-12-12 2014-07-22 Sandisk Technologies Inc. Current mirror device and method
JP5163437B2 (ja) * 2008-11-12 2013-03-13 ソニー株式会社 差動出力回路および通信装置
US20110050198A1 (en) * 2009-09-01 2011-03-03 Zhiwei Dong Low-power voltage regulator
FR2964274B1 (fr) * 2010-08-26 2013-06-28 St Microelectronics Sa Convertisseur a decoupage
TWI461702B (zh) * 2012-04-27 2014-11-21 Powerforest Technology Corp 極低啟動電流電源偵測裝置
FR3103333A1 (fr) * 2019-11-14 2021-05-21 Stmicroelectronics (Tours) Sas Dispositif pour générer un courant

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4583037A (en) * 1984-08-23 1986-04-15 At&T Bell Laboratories High swing CMOS cascode current mirror
US4983929A (en) * 1989-09-27 1991-01-08 Analog Devices, Inc. Cascode current mirror
US5099205A (en) * 1990-11-29 1992-03-24 Brooktree Corporation Balanced cascode current mirror
DE4201155C1 (ko) * 1992-01-17 1993-01-28 Texas Instruments Deutschland Gmbh, 8050 Freising, De
NL9201053A (nl) * 1992-06-15 1994-01-03 Koninkl Philips Electronics Nv Switched capacitor ladingspomp, alsmede zaagtandoscillator voorzien van een dergelijke switched capacitor ladingspomp.
GB9300155D0 (en) * 1993-01-06 1993-03-03 Philips Electronics Uk Ltd Electrical circuit arrangement
EP0613072B1 (en) * 1993-02-12 1997-06-18 Koninklijke Philips Electronics N.V. Integrated circuit comprising a cascode current mirror

Also Published As

Publication number Publication date
JPH08274550A (ja) 1996-10-18
US5654629A (en) 1997-08-05
EP0730214A3 (de) 1997-07-16
JP3880649B2 (ja) 2007-02-14
KR960036010A (ko) 1996-10-28
DE59607907D1 (de) 2001-11-22
DE19507155C1 (de) 1996-08-14
EP0730214A2 (de) 1996-09-04

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