DE69022310D1 - Halbleiterspeichergerät. - Google Patents
Halbleiterspeichergerät.Info
- Publication number
- DE69022310D1 DE69022310D1 DE69022310T DE69022310T DE69022310D1 DE 69022310 D1 DE69022310 D1 DE 69022310D1 DE 69022310 T DE69022310 T DE 69022310T DE 69022310 T DE69022310 T DE 69022310T DE 69022310 D1 DE69022310 D1 DE 69022310D1
- Authority
- DE
- Germany
- Prior art keywords
- storage device
- semiconductor storage
- semiconductor
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/26—Accessing multiple arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C29/34—Accessing multiple bits simultaneously
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1171283A JP2780354B2 (ja) | 1989-07-04 | 1989-07-04 | 半導体メモリ装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69022310D1 true DE69022310D1 (de) | 1995-10-19 |
DE69022310T2 DE69022310T2 (de) | 1996-02-22 |
Family
ID=15920453
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69022310T Expired - Fee Related DE69022310T2 (de) | 1989-07-04 | 1990-07-04 | Halbleiterspeichergerät. |
Country Status (5)
Country | Link |
---|---|
US (1) | US5148398A (de) |
EP (1) | EP0407173B1 (de) |
JP (1) | JP2780354B2 (de) |
KR (1) | KR930009543B1 (de) |
DE (1) | DE69022310T2 (de) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4028819A1 (de) * | 1990-09-11 | 1992-03-12 | Siemens Ag | Schaltungsanordnung zum testen eines halbleiterspeichers mittels paralleltests mit verschiedenen testbitmustern |
JP2863012B2 (ja) * | 1990-12-18 | 1999-03-03 | 三菱電機株式会社 | 半導体記憶装置 |
JP2957284B2 (ja) * | 1990-12-22 | 1999-10-04 | 富士通株式会社 | 半導体回路 |
US6781895B1 (en) | 1991-12-19 | 2004-08-24 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and memory system using the same |
US5361227A (en) * | 1991-12-19 | 1994-11-01 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and memory system using the same |
KR950000305Y1 (ko) * | 1991-12-23 | 1995-01-16 | 금성일렉트론 주식회사 | 메모리 장치의 테스트 모드회로 |
JPH05210998A (ja) * | 1992-01-30 | 1993-08-20 | Nec Corp | 半導体メモリ装置 |
US5216672A (en) * | 1992-04-24 | 1993-06-01 | Digital Equipment Corporation | Parallel diagnostic mode for testing computer memory |
JPH0612878A (ja) * | 1992-06-25 | 1994-01-21 | Mitsubishi Electric Corp | 半導体メモリ装置 |
US5327382A (en) * | 1992-09-09 | 1994-07-05 | Katsunori Seno | Method of testing redundant memory cells |
JP2768175B2 (ja) * | 1992-10-26 | 1998-06-25 | 日本電気株式会社 | 半導体メモリ |
KR960002016B1 (ko) * | 1993-02-15 | 1996-02-09 | 금성일렉트론주식회사 | 반도체 기억소자의 테스트 모드회로 |
JPH06275100A (ja) * | 1993-03-19 | 1994-09-30 | Fujitsu Ltd | 半導体記憶装置 |
JPH0877797A (ja) * | 1994-09-01 | 1996-03-22 | Fujitsu Ltd | 半導体記憶装置 |
JP3603440B2 (ja) * | 1996-01-12 | 2004-12-22 | 富士通株式会社 | 半導体記憶装置 |
US5959911A (en) * | 1997-09-29 | 1999-09-28 | Siemens Aktiengesellschaft | Apparatus and method for implementing a bank interlock scheme and related test mode for multibank memory devices |
US6058056A (en) * | 1998-04-30 | 2000-05-02 | Micron Technology, Inc. | Data compression circuit and method for testing memory devices |
US6295618B1 (en) * | 1998-08-25 | 2001-09-25 | Micron Technology, Inc. | Method and apparatus for data compression in memory devices |
JP2001243795A (ja) * | 1999-12-24 | 2001-09-07 | Nec Corp | 半導体記憶装置 |
JP4057756B2 (ja) * | 2000-03-01 | 2008-03-05 | 松下電器産業株式会社 | 半導体集積回路 |
US6421794B1 (en) | 2000-03-09 | 2002-07-16 | John T. Chen | Method and apparatus for diagnosing memory using self-testing circuits |
CN100455611C (zh) | 2004-04-13 | 2009-01-28 | 大金工业株式会社 | 氯三氟乙烯共聚物 |
US7339841B2 (en) * | 2005-09-16 | 2008-03-04 | Infineon Technologies Ag | Test mode method and apparatus for internal memory timing signals |
JP5181698B2 (ja) | 2008-01-30 | 2013-04-10 | 富士通セミコンダクター株式会社 | 半導体メモリおよび半導体メモリの製造方法 |
JP5131348B2 (ja) | 2008-03-19 | 2013-01-30 | 富士通セミコンダクター株式会社 | 半導体メモリ、システム、半導体メモリの動作方法および半導体メモリの製造方法 |
JP2012022750A (ja) * | 2010-07-15 | 2012-02-02 | Lapis Semiconductor Co Ltd | 半導体メモリのテスト回路 |
GB2498980A (en) * | 2012-02-01 | 2013-08-07 | Inside Secure | Device and method to perform a parallel memory test |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57105897A (en) * | 1980-12-23 | 1982-07-01 | Fujitsu Ltd | Semiconductor storage device |
US4686456A (en) * | 1985-06-18 | 1987-08-11 | Kabushiki Kaisha Toshiba | Memory test circuit |
JP2523586B2 (ja) * | 1987-02-27 | 1996-08-14 | 株式会社日立製作所 | 半導体記憶装置 |
JPS63257999A (ja) * | 1987-04-15 | 1988-10-25 | Mitsubishi Electric Corp | 半導体記憶装置 |
JPS6473600A (en) * | 1987-09-16 | 1989-03-17 | Hitachi Ltd | Semiconductor memory device |
JP2805853B2 (ja) * | 1989-06-26 | 1998-09-30 | 日本電気株式会社 | 半導体メモリ |
-
1989
- 1989-07-04 JP JP1171283A patent/JP2780354B2/ja not_active Expired - Fee Related
-
1990
- 1990-07-03 US US07/553,027 patent/US5148398A/en not_active Expired - Lifetime
- 1990-07-04 DE DE69022310T patent/DE69022310T2/de not_active Expired - Fee Related
- 1990-07-04 KR KR1019900010074A patent/KR930009543B1/ko not_active IP Right Cessation
- 1990-07-04 EP EP90307314A patent/EP0407173B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0407173A3 (en) | 1992-01-08 |
DE69022310T2 (de) | 1996-02-22 |
KR930009543B1 (ko) | 1993-10-06 |
EP0407173A2 (de) | 1991-01-09 |
JPH0337900A (ja) | 1991-02-19 |
KR910003679A (ko) | 1991-02-28 |
US5148398A (en) | 1992-09-15 |
EP0407173B1 (de) | 1995-09-13 |
JP2780354B2 (ja) | 1998-07-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |