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DE3777522D1 - Verfahren zum herstellen einer gemischten struktur fuer halbleiteranordnung. - Google Patents

Verfahren zum herstellen einer gemischten struktur fuer halbleiteranordnung.

Info

Publication number
DE3777522D1
DE3777522D1 DE8787115028T DE3777522T DE3777522D1 DE 3777522 D1 DE3777522 D1 DE 3777522D1 DE 8787115028 T DE8787115028 T DE 8787115028T DE 3777522 T DE3777522 T DE 3777522T DE 3777522 D1 DE3777522 D1 DE 3777522D1
Authority
DE
Germany
Prior art keywords
producing
mixed structure
semiconductor arrangement
semiconductor
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787115028T
Other languages
English (en)
Inventor
Kenichi Mizuishi
Masahide Hitachi Koyasu Tokuda
Katuaki Chiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP5652887A external-priority patent/JP2510557B2/ja
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of DE3777522D1 publication Critical patent/DE3777522D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4332Bellows
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    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
DE8787115028T 1986-10-17 1987-10-14 Verfahren zum herstellen einer gemischten struktur fuer halbleiteranordnung. Expired - Lifetime DE3777522D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP24525286 1986-10-17
JP5652887A JP2510557B2 (ja) 1986-10-17 1987-03-13 複合構造体の製造方法

Publications (1)

Publication Number Publication Date
DE3777522D1 true DE3777522D1 (de) 1992-04-23

Family

ID=26397487

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787115028T Expired - Lifetime DE3777522D1 (de) 1986-10-17 1987-10-14 Verfahren zum herstellen einer gemischten struktur fuer halbleiteranordnung.

Country Status (3)

Country Link
US (1) US4819857A (de)
EP (1) EP0264122B1 (de)
DE (1) DE3777522D1 (de)

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EP0460286A3 (en) * 1990-06-06 1992-02-26 Siemens Aktiengesellschaft Method and arrangement for bonding a semiconductor component to a substrate or for finishing a semiconductor/substrate connection by contactless pressing
US5906310A (en) * 1994-11-10 1999-05-25 Vlt Corporation Packaging electrical circuits
JP2732823B2 (ja) * 1995-02-02 1998-03-30 ヴィエルティー コーポレーション はんだ付け方法
CA2156941A1 (en) * 1995-08-21 1997-02-22 Jonathan H. Orchard-Webb Method of making electrical connections to integrated circuit
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US6070321A (en) * 1997-07-09 2000-06-06 International Business Machines Corporation Solder disc connection
US6095400A (en) * 1997-12-04 2000-08-01 Ford Global Technologies, Inc. Reinforced solder preform
US6316737B1 (en) 1999-09-09 2001-11-13 Vlt Corporation Making a connection between a component and a circuit board
JP3946393B2 (ja) * 1999-10-19 2007-07-18 株式会社東芝 階層構造をもつ並列計算機
US7443229B1 (en) 2001-04-24 2008-10-28 Picor Corporation Active filtering
AU2002318144A1 (en) * 2001-05-24 2003-01-29 Fry's Metals, Inc. Thermal interface material and heat sink configuration
MXPA06005908A (es) * 2001-05-24 2007-01-26 Fry Metals Inc Material termico de interfaz y preformas para soldar.
US6848610B2 (en) * 2003-03-25 2005-02-01 Intel Corporation Approaches for fluxless soldering
US7621435B2 (en) * 2004-06-17 2009-11-24 The Regents Of The University Of California Designs and fabrication of structural armor
US7723830B2 (en) * 2006-01-06 2010-05-25 International Rectifier Corporation Substrate and method for mounting silicon device
EP2142489A1 (de) * 2007-04-24 2010-01-13 CeramTec AG Bauteil mit einem keramischen körper mit metallisierter oberfläche
US8076773B2 (en) * 2007-12-26 2011-12-13 The Bergquist Company Thermal interface with non-tacky surface

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DE2032939B2 (de) * 1970-07-03 1975-05-07 Robert Bosch Gmbh, 7000 Stuttgart Verfahren zum Auflöten eines Halbleiterkörpers auf einen Träger
US3711939A (en) * 1970-11-10 1973-01-23 M Stoll Method and apparatus for sealing
JPS5614069A (en) * 1979-07-16 1981-02-10 Nec Corp Soldering method and soldering material
DE2939666C2 (de) * 1979-09-29 1982-07-15 Robert Bosch Gmbh, 7000 Stuttgart Verfahren zur lunkerfreien Verlötung eines metallisierten Halbleiterplättchens mit einem Träger
US4645116A (en) * 1982-10-08 1987-02-24 At&T Bell Laboratories Fluxless bonding of microelectronic chips
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JPS60214536A (ja) * 1984-04-09 1985-10-26 Fujitsu Ltd 半導体装置の製造方法
JPS61125025A (ja) * 1984-11-22 1986-06-12 Hitachi Ltd 半導体装置の製造方法
DE3442537A1 (de) * 1984-11-22 1986-05-22 BBC Aktiengesellschaft Brown, Boveri & Cie., Baden, Aargau Verfahren zum blasenfreien verbinden eines grossflaechigen halbleiter-bauelements mit einem als substrat dienenden bauteil mittels loeten
US4604644A (en) * 1985-01-28 1986-08-05 International Business Machines Corporation Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making
US4709849A (en) * 1985-11-27 1987-12-01 Fry Metals, Inc. Solder preform and methods employing the same

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EP0264122B1 (de) 1992-03-18
EP0264122A3 (en) 1989-06-07
US4819857A (en) 1989-04-11
EP0264122A2 (de) 1988-04-20

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