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CN204231766U - 高频模块 - Google Patents

高频模块 Download PDF

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Publication number
CN204231766U
CN204231766U CN201390000231.1U CN201390000231U CN204231766U CN 204231766 U CN204231766 U CN 204231766U CN 201390000231 U CN201390000231 U CN 201390000231U CN 204231766 U CN204231766 U CN 204231766U
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via conductors
cavity
frequency model
base plate
multilager base
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乡地直树
马场贵博
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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    • H—ELECTRICITY
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    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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Abstract

防止内置于多层基板内的空腔中的IC芯片受到损伤等，该多层基板将由热塑性树脂材料构成的片材进行层叠、热压接而成的。本实用新型的高频模块将IC芯片(25)内置于设置在多层基板(10)中的空腔(20)内，该多层基板(10)通过将由热塑性树脂材料构成的多个片材(11a)～(11g)进行层叠、热压接而成。在IC芯片(25)的侧面与空腔(20)的内壁部之间设有间隙(G)。在多层基板(10)中，与空腔(20)的内壁部相邻地设有通孔导体(17)，以防止对树脂片材进行热压接时树脂片材发生软化而流入空腔(20)内。

Description

高频模块
技术领域
本实用新型涉及高频模块、尤其涉及作为通信用设备装载在移动体通信终端等电子设备上的高频模块。
背景技术
近年来，对于移动体通信终端等电子设备要求其高功能化、小型化，对所装载的电子元器件也要求高性能化、小型化。因此，作为这种电子元器件，使用一种使各种高频功能元器件与一个基板成为一体的高频模块。
以进一步高功能化、小型化为目的，有时使用将IC芯片内置于热塑性树脂制的多层基板内的模块。为了将IC芯片内置于树脂制多层基板内，如专利文献1、2记载的那样，将利用冲孔等形成了开口部的树脂片材进行层叠而形成空腔，将IC芯片埋入该空腔内。
然而，在现有的IC芯片内置模块中，在将树脂片材的层叠体进行热压接时，树脂发生软化而流动，所述空腔的侧壁部会与IC芯片的侧面压接并固化。即，在完成的模块中，在空腔内，IC芯片的侧面与固化的树脂接触甚至被推压。因此，若因掉落、碰撞等对多层基板作用有机械方式的冲击，或空腔的侧壁部因热应力而发生变形，则有可能会在硅制的IC芯片中产生裂缝等损伤，或者产生位置偏差，进而动作不良。
现有技术文献
专利文献
专利文献1：日本专利特开2002－270712号公报
专利文献2：日本专利特开2005－317585号公报
实用新型内容
实用新型所要解决的问题
本实用新型的目的在于提供一种高频模块，该高频模块不会招来内置于多层基板内的空腔中的IC芯片的损伤等，所述多层基板将由热塑性树脂材料构成的片材进行层叠、热压接而成。
解决技术问题所采用的技术方案
本实用新型的一个实施方式的高频模块将IC芯片内置于设置在多层基板中的空腔内，该多层基板通过将由热塑性树脂材料构成的多个片材进行层叠、热压接而成，其特征在于，
在所述IC芯片的侧面与所述空腔的内壁部之间设有间隙，
在所述多层基板中，与所述空腔的内壁部相邻地设有通孔导体，以防止对所述树脂片材进行热压接时该树脂片材发生软化而流入所述空腔内。
在所述高频模块中，在将树脂片材进行层叠、热压接而成为多层基板时，能利用通孔导体来防止树脂片材发生软化而流入空腔内。因此，在树脂片材固化的情况下，IC芯片的侧面与空腔之间保持有间隙，即使在对多层基板作用有机械性冲击、或空腔的侧壁部因热应力而发生变形等情况下，该间隙也能发挥缓冲作用，避免IC芯片产生损伤等。
实用新型的效果
根据本实用新型，能排除内置于多层基板内的空腔中的IC芯片产生损伤等的可能性，其中，所述多层基板将由热塑性树脂材料构成的片材进行层叠、热压接而成。
附图说明
图1表示作为实施例1的高频模块，(A)是垂直剖视图，表示相当于(B)的X-X线的截面，(B)是俯视图，表示相当于(A)的Y-Y线的平面。
图2是表示设置在所述高频模块中的IC芯片与空腔之间的间隙的各种形态的剖视图。
图3是表示作为实施例2的高频模块的俯视图，表示相当于图1(A)的Y-Y线的平面。
图4是表示作为实施例3的高频模块的俯视图，表示相当于图1(A)的Y-Y线的平面。
图5是表示作为实施例4的高频模块的俯视图，表示相当于图1(A)的Y-Y线的平面。
图6是表示作为实施例4的高频模块的垂直剖视图，表示相当于图5的Z-Z线的截面。
具体实施方式
以下，参照附图对本实用新型所涉及的高频模块的实施例进行说明。另外，在各图中，对共同的元器件、部分标注相同的标号，并省略重复的说明。
(实施例1，参照图1)
如图1所示，实施例1的高频模块1A将存储IC芯片25内置于形成在多层基板10内部的空腔20内。在多层基板10的下表面形成有被阻焊剂32部分覆盖的导体图案31，通过该导体图案31安装在未图示的移动体通信终端等电子设备的母基板上。在多层基板10的上表面，无线通信用IC40、电容器45、电感器46等贴片型电子元器件安装在导体图案33上，且导体图案33被阻焊剂34覆盖。
无线通信用IC40是用于处理高频信号的例如RFIC芯片，电容器45用于构成无线通信用IC40的阻抗匹配电路，电感器46用于构成滤波电路。内置于多层基板10内的存储IC芯片25是起到安全元件IC的作用的具有编码功能的存储器，存储IC芯片25从设置在半导体基板上的集成电路通过再布线层26、再经由通孔导体15与导体图案16相连接。
此外，在多层基板10的内部通过各种导体图案、通孔导体构成所需的电路。存储IC芯片25经由这些内置电路实现与所述无线通信用IC40的电连接。此外，在再布线层26中设有连接盘26a，该连接盘26a与通孔导体15的端面直接相连接。
多层基板10是通过将由热塑性树脂材料构成的多个片材11a～11g进行层叠、热压接而成的，在片材11b、11c中通过冲孔形成开口部，将该片材11b、11c与其它片材11a、11d～11g一起进行层叠，从而在内部形成空腔20。此外，在各个片材11a～11g中形成通孔导体、所需的导体图案，通过将片材11a～11g进行层叠，从而形成线路、电容器等无源元件。作为树脂材料，能优选使用聚酰亚胺树脂、液晶聚合物等热塑性树脂材料。液晶聚合物在高频特性方面较为优异，且吸水性较低，因此，是特别优选的材料。导体图案、通孔导体优选为由以银、铜等为主要成分的电阻率较小的金属材料来形成。此外，作为所述阻焊剂32、34，能使用环氧树脂、硅树脂等。
空腔20是与存储IC芯片25的俯视形状相同的四边形，其具备如下的容积：在收容存储IC芯片25时，空腔20与该芯片25的四个侧面分别形成10～300μm左右(优选为100μm左右)的间隙G。此外，对于防止在与空腔20的内壁部相邻地对树脂片材进行热压接时树脂片材(尤其是片材11b、11c)发生软化而流入空腔20内的通孔导体17(以下，将该导体称为流动防止用通孔导体)，例如以1mm的间隔在空腔20的整个一周、即四个侧面的每一面配置成一列。通孔导体17的直径例如为50～300μm。
树脂片材11a～11g由在250～300℃左右发生软化的材料形成，在热压接时加热到该温度为止。另一方面，流动防止用通孔导体17由在比该温度要低的温度下发生固化的材料形成。例如，使用以银或铜为主要成分的金属合金材料或焊料，出于简化制造工序，优选为使用与其它通孔导体相同的材料。
通常，若不存在流动防止用通孔导体17，则在将树脂片材进行层叠并热压接时，软化的树脂片材11b、11c的内壁部会流动到空腔20内，在与存储IC芯片25的大致整个侧面相接触甚至压接的状态下固化。然而，在本实施例1中，由于与空腔20的内壁部相邻地配置多个通孔导体17，因此，即使在对树脂片材进行热压接之后，仍能将间隙G基本保持原状。因此，在作为高频模块完成之后，即使因掉落、碰撞等对多层基板10作用有机械性冲击，或产生热应力，空腔20的内壁部也不太会变形，不会在存储IC芯片25产生裂缝等损伤、或者产生位置偏差，能预防动作不良。
此外，也不会因热压接时的冲压而使存储IC芯片25产生位置偏差。而且，由于间隙G的存在，能提高存储IC芯片25与多层基板10之间的电、热的隔离性，提高作为高频模块的电特性和可靠性。
另外，存储IC芯片25的上下表面也可以被树脂片材11a、11d压接，即使未被压接，存储IC芯片25也可以通过连接盘26a与通孔导体15的连接而在空腔20的内部固定位置。
流动防止用通孔导体17也可以形成电路，即，也可以经由形成在任意的树脂片材上的导体图案与接地导体、电容器等无源元件电连接。此外，流动防止用通孔导体17未必一定要形成电路，也可以是所有的流动防止用通孔导体17或至少一个流动防止用通孔导体17为电绝缘状态。
或者，流动防止用通孔导体17未必需要在空腔20的整个一周配置。即使在四个内壁部中的部分树脂片材产生流动，只要结果是不对存储IC芯片25的侧面有较强的推压的程度，也可以省略允许这样的流动的部分的通孔导体17。可能对存储IC芯片25的侧面产生较强推压的是俯视时位于对角线上的角落部，优选为流动防止用通孔导体17至少配置在四个角落部。因此，流动防止用通孔导体17也无需与四个内壁部相邻并分别等间隔地配置。
如图2(A)所示，在存储IC芯片25的侧面与空腔20的侧面之间，所述间隙G作为各个侧面均不接触的完整的间隙来设置，但并不限于此。也可以如图2(B)所示，空腔20的侧面具有随机的凹凸部，凸部与存储IC芯片25的侧面部分接触。此外，在存储IC芯片25的侧面形成有凹凸部的情况下，也可以在空腔20的侧面形成与该凹凸部相对应的凹凸部，以使凹凸部彼此卡合的状态设置间隙G。
(实施例2，参照图3)
如图3所示，在作为实施例2的高频模块1B中，与空腔20的四个内壁部相邻且俯视时呈交错状地配置流动防止用通孔导体17a、17b。内侧的流动防止用通孔导体17a形成在树脂片材11b(参照图1(A))中，外侧的流动防止用通孔导体17b形成在树脂片材11c中。本实施例2中的其他结构与所述实施例1相同，其作用效果也与实施例1相同。
然而，若将流动防止用通孔导体17在多层基板10的层叠方向上重叠配置，则在热压接时，通孔导体与树脂片材相比几乎不收缩，因此，多层基板10的该部分(形成有通孔导体的部分)的厚度有所增大，有可能损害多层基板10的平坦性。尤其是，在实施例2中，流动防止用通孔导体17a、17b呈交错状地配置，因此，能消除多层基板10的局部厚度的不均匀。
(实施例3，参照图4)
如图4所示，在作为实施例3的高频模块1C中，流动防止用通孔导体17c、17d、17e～17g分别由形成在树脂片材上的连接盘35a、35b相连接。本实施例3中的其他结构与所述实施例1相同，其作用效果也与实施例1相同。使流动防止用通孔导体17c～17g每两个或每三个与共用的连接盘35a、35b相连接，从而各通孔导体17c～17g的强度得到加强，能更有效地保护内置的存储IC芯片25。连接盘35a、35b厚度为5～35μm，并形成为覆盖流动防止用通孔导体17，从而能起到加强通孔导体17、防止树脂片材的树脂流入空腔20内的效果。
(实施例4，参照图5及图6)
如图5所示，在作为实施例4的高频模块1D中，由形成在树脂片材上的环状的单一的连接盘35将各个流动防止用通孔导体17相连接。本实施例4中的其他结构与所述实施例1相同，其作用效果也与实施例1相同。尤其是，在实施例4中，所有的流动防止用通孔导体17由共用的连接盘35相连接，因此，能更有效地保护内置的存储IC芯片25。此外，如图6所示，环状的连接盘35在设有流动防止用通孔导体17的截面部分的基础上，在未设有流动防止用通孔导体17的截面部分，也能防止树脂片材中的树脂发生软化而从连接盘35的形成区域及其外侧流入空腔20。
(其它实施例)
另外，本实用新型所涉及的高频模块并不限于所述实施例，在其要点的范围内能进行各种变更。
尤其是，表面安装在多层基板上的电子元器件、内置的电子元器件的种类是任意的，内置于多层基板中的导体图案的形状、电路结构也是任意的。
工业上的实用性
如上所述，本实用新型适用于高频模块，尤其在能避免内置于多层基板中的IC芯片产生损伤等方面较为优异。
标号说明
1A～1D…高频模块
10…多层基板
11a～11g…树脂片材
17、17a～17g…流动防止用通孔导体
20…空腔
25…存储IC芯片
35、35a、35b…连接盘
G…间隙

Claims (10)

1.一种高频模块，该高频模块将IC芯片内置于空腔内，该空腔设置在多层基板中，该多层基板通过将由热塑性树脂材料构成的多个片材进行层叠、热压接而成，其特征在于，
在所述IC芯片的侧面与所述空腔的内壁部之间设有间隙，
在所述多层基板中，与所述空腔的内壁部相邻地设有通孔导体，以防止对所述树脂片材进行热压接时该树脂片材发生软化而流入所述空腔内。
2.如权利要求1所述的高频模块，其特征在于，
在所述多层基板的上表面设有表面安装IC芯片。
3.如权利要求1或2所述的高频模块，其特征在于，
在所述多层基板中内置有无源元件。
4.如权利要求1至3的任一项所述的高频模块，其特征在于，
所述通孔导体由如下那样的材料构成，该材料在比所述树脂片材发生软化、流动的温度要低的温度下发生固化。
5.如权利要求1至5的任一项所述的高频模块，其特征在于，
所述通孔导体中的至少一个通孔导体为电绝缘状态。
6.如权利要求1至5的任一项所述的高频模块，其特征在于，
所述通孔导体中的至少一个通孔导体与其它无源元件电连接。
7.如权利要求1至7的任一项所述的高频模块，其特征在于，
所述通孔导体与形成在所述树脂片材上的导体图案或连接盘相连接。
8.如权利要求1至8的任一项所述的高频模块，其特征在于，
所述通孔导体在所述空腔的整个一周配置成一列。
9.如权利要求1至8的任一项所述的高频模块，其特征在于，
所述通孔导体俯视时呈交错状地配置。
10.如权利要求1至8的任一项所述的高频模块，其特征在于，
所述空腔俯视时呈矩形，所述通孔导体至少配置在所述矩形的角部。
CN201390000231.1U 2012-06-14 2013-04-15 高频模块 Expired - Lifetime CN204231766U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108012418A (zh) * 2017-12-07 2018-05-08 生益电子股份有限公司 一种内置空腔的pcb及其制造方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN204335177U (zh) * 2012-10-22 2015-05-13 株式会社村田制作所 电子元器件内置模块
US9326373B2 (en) * 2014-04-09 2016-04-26 Finisar Corporation Aluminum nitride substrate
JP6477894B2 (ja) * 2015-09-02 2019-03-06 株式会社村田製作所 樹脂回路基板、部品搭載樹脂回路基板
WO2017065028A1 (ja) 2015-10-15 2017-04-20 株式会社村田製作所 樹脂基板、部品実装樹脂基板、および、部品実装樹脂基板の製造方法
JP2017123459A (ja) * 2016-01-08 2017-07-13 サムソン エレクトロ−メカニックス カンパニーリミテッド． プリント回路基板
CN106971993B (zh) * 2016-01-14 2021-10-15 三星电子株式会社 半导体封装件
KR102595276B1 (ko) 2016-01-14 2023-10-31 삼성전자주식회사 반도체 패키지

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6617193B1 (en) * 1997-04-30 2003-09-09 Hitachi Chemical Company, Ltd. Semiconductor device, semiconductor device substrate, and methods of fabricating the same
US6492203B1 (en) * 1997-04-30 2002-12-10 Hitachi Chemical Company, Ltd. Semiconductor device and method of fabrication thereof
JP3051700B2 (ja) * 1997-07-28 2000-06-12 京セラ株式会社 素子内蔵多層配線基板の製造方法
CN100381026C (zh) * 1999-09-02 2008-04-09 伊比登株式会社 印刷布线板及其制造方法
US6512182B2 (en) * 2001-03-12 2003-01-28 Ngk Spark Plug Co., Ltd. Wiring circuit board and method for producing same
JP2002270712A (ja) * 2001-03-14 2002-09-20 Sony Corp 半導体素子内蔵多層配線基板と半導体素子内蔵装置、およびそれらの製造方法
KR100488412B1 (ko) * 2001-06-13 2005-05-11 가부시키가이샤 덴소 내장된 전기소자를 갖는 인쇄 배선 기판 및 그 제조 방법
JP2003078250A (ja) * 2001-09-04 2003-03-14 Matsushita Electric Ind Co Ltd 部品内蔵モジュールおよびその製造方法
JP4268560B2 (ja) 2004-04-27 2009-05-27 大日本印刷株式会社 電子部品内蔵モジュールおよびその製造方法
JP2006073763A (ja) * 2004-09-01 2006-03-16 Denso Corp 多層基板の製造方法
KR100716815B1 (ko) * 2005-02-28 2007-05-09 삼성전기주식회사 칩 내장형 인쇄회로기판 및 그 제조방법
US8101868B2 (en) * 2005-10-14 2012-01-24 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
EP1962569A1 (en) * 2005-12-16 2008-08-27 Ibiden Co., Ltd. Multilayer printed wiring plate, and method for fabricating the same
JP2007287844A (ja) * 2006-04-14 2007-11-01 Matsushita Electric Ind Co Ltd 部品内蔵基板の製造方法およびその製造装置
JP5082321B2 (ja) * 2006-07-28 2012-11-28 大日本印刷株式会社 多層プリント配線板及びその製造方法
JP2008159819A (ja) * 2006-12-22 2008-07-10 Tdk Corp 電子部品の実装方法、電子部品内蔵基板の製造方法、及び電子部品内蔵基板
WO2009093343A1 (ja) * 2008-01-25 2009-07-30 Ibiden Co., Ltd. 多層配線板およびその製造方法
JP2009224379A (ja) * 2008-03-13 2009-10-01 Renesas Technology Corp 半導体装置およびその製造方法
KR100996914B1 (ko) * 2008-06-19 2010-11-26 삼성전기주식회사 칩 내장 인쇄회로기판 및 그 제조방법
JP2011165741A (ja) * 2010-02-05 2011-08-25 Renesas Electronics Corp 半導体装置およびその製造方法
TWI530241B (zh) * 2010-03-16 2016-04-11 A multi - layer circuit board manufacturing method for embedded electronic components
WO2011114766A1 (ja) * 2010-03-16 2011-09-22 日本電気株式会社 機能素子内蔵基板
JP2011222555A (ja) * 2010-04-02 2011-11-04 Denso Corp 半導体チップ内蔵配線基板の製造方法
JP2012151372A (ja) * 2011-01-20 2012-08-09 Ibiden Co Ltd 配線板及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108012418A (zh) * 2017-12-07 2018-05-08 生益电子股份有限公司 一种内置空腔的pcb及其制造方法
CN108012418B (zh) * 2017-12-07 2019-11-01 生益电子股份有限公司 一种内置空腔的pcb及其制造方法

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CU01 Correction of utility model

Correction item: Claims

Correct: Correct

False: Error

Number: 12

Page: Description

Volume: 31

RECT Rectification
CX01 Expiry of patent term

Granted publication date: 20150325

CX01 Expiry of patent term