CN1530718A - Method for manufacturing reflective liquid crystal display and peripheral circuit - Google Patents

Abstract

A low temperature poly-silicon liquid crystal display comprises a P-type thin film transistor TFT (without lightly doped drain LDD), a driving circuit of an n-type TFT comprising LDD, and a manufacturing method of a pixel TFT, a storage capacitor and a bottom electrode of the pixel capacitor. The process comprises defining the source/drain, forming the active layer and the gate oxide layer, forming the photosensitive resin layer before the deposition of the transistor gate metal, patterning to form a bump prototype, reflowing and smoothing, and simultaneously depositing and patterning the gate metal layer and the reflective metal layer on the bump. Next, LDD implantation is performed. Then, using the photoresist pattern defining the P-type TFT as a mask, a source/drain ion implantation is performed to form the source and drain of the P-type TFT. Finally, after removing the photoresist, a passivation layer and a contact hole are formed. Only six masks are needed in the process to manufacture the reflective liquid crystal display TFT and its driving circuit.

Description

Method for manufacturing reflective liquid crystal display and peripheral circuit

technical field

The present invention is related to a liquid crystal display process technology, in particular to a reflective low-temperature polysilicon liquid crystal display process technology, which uses the simplest mask to complete the technology including the driving circuit and liquid crystal display pixels.

Background of the invention

Liquid crystal display (LCD) is a flat display with low power consumption, and because it is much smaller in terms of space and quality than a cathode ray tube (CRT) with the same window size, and There will be no curved surface like a normal CRT. Therefore, it has been widely used in various products, including consumer electronics such as palmtop computers, computer dictionaries, watches, mobile phones, larger portable computers, communication terminals, display panels, personal desktop computers, and even high-end It's not hard to see traces and popularity of high-definition TV (HDTV) and so on. Especially the active matrix thin film transistor liquid crystal display (TFT-LCD) is much better than the passive matrix STN-LCD due to its viewing angle and contrast performance, and has a better response time.

The main components of a TFT liquid crystal display include: fluorescent tubes, light guide plates, polarizers, filter plates, glass substrates, alignment films, liquid crystal materials, and thin film transistors. First of all, the liquid crystal display must first use the backlight, that is, the fluorescent tube to project the light source. These light sources will first pass through a polarizer and then pass through the liquid crystal. At this time, the arrangement of the liquid crystal molecules will change the angle of light that penetrates the liquid crystal. Then the light must pass through the front color filter and another polarizer. Therefore, we only need to change the voltage value of stimulating the liquid crystal to control the final light intensity and color, and then can change the color combinations with different shades on the liquid crystal panel.

The above-mentioned TFT liquid crystal display needs to use fluorescent tubes as the backlight source and the diffusion film, or at least needs the side light source and the light guide plate. Therefore, if you want to further reduce power consumption and make the LCD display thinner, reflective LCD is a good choice. The light source of the reflective LCD mainly comes from the light irradiated from the outside, and only needs a small auxiliary light source, so it can save more power and make the thickness of the display thinner. Therefore, for electronic products using batteries, and when the place of use is not intentionally dark, the reflective LCD display is the best choice.

For the TFT-LCD mentioned above, the traditional amorphous silicon is mostly used as the main material of the TFT of the TFT-LCD. However, today there is a trend of using polysilicon to replace amorphous silicon, and it may become the mainstream. This mainly focuses on whether it is the mobility of electrons or holes, polysilicon has a better mobility than amorphous silicon. In addition, another advantage of polysilicon TFT-LCD is that the drive circuit for forming the LCD panel (including nMOS transistors or PMOS transistors or even complementary metal-oxide-semiconductor transistors) can be manufactured simultaneously with the pixel panel. Due to the above factors, polysilicon type TFT-LCD can provide a better switching rate than amorphous silicon type TFT-LCD, further accelerating its attractiveness. However, the above-mentioned polysilicon TFT-LCD is mostly limited to the transmissive TFT-LCD, such as US Patent No. 5,940,151 obtained by Hu.

In view of this, the present invention proposes a manufacturing technology that can combine polysilicon TFT-LCD and reflective TFT-LCD.

Contents of the invention

The main purpose of the present invention is to provide a method that requires fewer photomask steps (about six photomasks) and can simultaneously manufacture a reflective TFT-LCD including a driving circuit.

A method of manufacturing a reflective liquid crystal display, at least comprising the following steps:

forming a metal layer on a substrate;

forming a silicon layer of the first conductivity type on the metal layer;

Patterning the metal layer and the first conductivity type silicon layer to form a source/drain predetermined region of a first conductivity type TFT, a predetermined source region of a second conductivity type TFT, and a pixel A source/drain predetermined region of a pixel TFT and a predetermined storage capacitor region are formed in the region;

forming an active layer on the patterned surface;

forming a gate oxide layer on the active layer;

patterning the gate oxide layer and the active layer to form a first reserved area, a second reserved area, and a third reserved area, wherein the first reserved area is located at the source of the first conductivity type TFT Between the /drain regions and partially covering the source/drain region of the first conductivity type TFT, the second reserved region is located between the drain of the first conductivity type TFT and the source of the second conductivity type TFT and partially cover the drain of the first conductivity type TFT and the source of the second conductivity type TFT, the third reserved area is located between the source/drain regions of the pixel TFT and partially covers the pixel TFT source/drain regions;

forming an insulating layer on the patterned surface;

patterning the insulating layer to form a plurality of bumps on the pixel area; forming a gate metal layer on the patterned surface;

patterning the gate metal layer to form the reference potential connection electrode, the gate of the first conductivity type TFT, the gate of the second conductivity type TFT, the top electrode of the storage capacitor, and the bump in the pixel area A reflective metal layer is formed on it, and the reflective metal layer is connected to the drain of the pixel TFT and the top electrode of the storage capacitor;

Apply lightly doped drain (LDD) implantation, implant the first conductivity type impurity, use the patterned gate metal layer as a mask, and use it on both sides of the gate of the first conductivity type TFT The LDD region is formed on the side of the pixel TFT, and the LDD region is also formed on both sides of the gate of the pixel TFT;

forming a photoresist pattern layer on all regions except the second reserved region;

Implanting a second conductivity type impurity to mask the photoresist pattern layer and the gate of the second conductivity type TFT to form a source/drain region of the second conductivity type TFT;

removing the photoresist pattern layer;

forming a protective layer over the exposed surface; and

Patterning the protective layer is used to remove the protective layer on the reflective metal layer in the pixel area to expose the reflective metal layer and form contact holes at the end of the driving circuit area and the pixel area.

The method, wherein the first conductivity type is n-type, the second conductivity type is p-type, and the pixel TFT is n-type TFT.

Said method, wherein the step of forming the active layer further includes firstly forming an amorphous silicon layer, and then transforming into a polysilicon layer through laser crystallization.

Said method, wherein the insulating layer is a photosensitive resin layer.

The method further includes performing a thermal reflow step after the step of patterning the insulating layer and before the step of forming the gate metal layer to smooth the bump.

The method further includes forming a second reflective bump region on the source region of the pixel TFT to enlarge the aperture ratio, wherein the second reflective bump region exposes the third reserved region to retain the LDD Formation area.

The method, wherein the distance between the gate metal of the pixel TFT and its source/drain is not equidistant, and the distance between the gate metal of the first conductivity type TFT and its source/drain is not equidistant, and the nonequidistance is Make the distance between the drain and the gate larger than the distance between the source and the gate to reduce the leakage current.

Said method, wherein the protective layer is selected from one of photosensitive resin, silicon nitride layer, silicon oxide layer or any combination thereof.

Said method, wherein the steps of forming the protective layer and patterning the protective layer further include depositing a photosensitive resin layer, and then using a photomask to irradiate the photosensitive resin to form a contact hole pattern.

The method further includes performing annealing before forming the photosensitive resin layer to activate the impurities of the second conductivity type.

The method, wherein the steps of forming the protective layer and patterning the protective layer further include:

depositing a silicon nitride layer;

performing annealing to activate the second conductivity type impurity;

depositing the photosensitive resin layer;

patterning the photosensitive resin layer to expose the reflective metal layer and form a contact hole pattern; and using the photosensitive resin layer as a mask, patterning the silicon nitride layer to complete the structure of the contact hole.

In the manufacturing process, only about six photomasks are needed to manufacture reflective liquid crystal display TFT and its driving circuit.

Description of drawings

FIG. 1A is a schematic top view of a basic pixel of a TFT-LCD of the present invention;

FIG. 1B to FIG. 1H are cross-sectional schematic diagrams of the process steps according to the present invention, wherein the pixel portion is taken along the line a-a' in FIG. 1A .

Description of drawing number comparison:

100 transparent substrate

101 drive circuit area

102 pixel area

105 metal layer

110 n+ impurity doped polysilicon layer

120 LDD of n-type TFT and predetermined area of channel (abbreviated as predetermined area)

120d Drain of n-type TFT

120s source of n-type TFT

122 The source/drain of the p-type TFT and the predetermined area of the channel (referred to as the predetermined area)

122s source of p-type TFT

122s’ p-type TFT source predetermined area

122d The drain of p-type-TFT

124 pixel TFT LCD and the predetermined area of the channel (referred to as the predetermined area)

124s signal line (as the source of the pixel TFT)

124d pixel TFT drain

124s pixel TFT source

125 storage capacitor

129A First reflective bump area

129B Second reflective bump area

130 undoped amorphous silicon layer

135 Gate oxide layer (also known as capacitor dielectric layer)

140 scan lines

140A first reflective bump area metal layer

140B second reflective bump area metal layer

140C storage capacitor top electrode

140d Drain area

140i pixel TFT gate

140L, 144L LDD reservation area

140n n-type gate of a TFT

140p p-type gate of a TFT

145 photoresist pattern layer

160 protective layers

Vss The first reference electrode

Detailed ways

Please refer to FIG. 1A, which is a top view showing a pixel according to the present invention. In FIG. 1A, the scanning line 140 and the signal line 124s are vertically intersected, and the scanning line 140 includes the gate electrode 140i of the pixel TFT, and the signal line 124s is for the pixel TFT. source line. The metal layer 140A of the first reflective bump area occupies most of the pixel area, and is connected to the drain 124d of the pixel TFT and the top electrode 140C of the storage capacitor. The second reflective bump metal layer 140B is connected across the signal line 124s to the gate 140i of the next pixel.

Fig. 1B is a schematic diagram showing a cross section corresponding to a-a' in Fig. 1A. According to the method of the present invention, the metal layer 140A of the first reflective bump area in the pixel A is connected to the upper electrode plate of the top electrode 140C of the storage capacitor through the drain of the pixel A. The second reflective bump metal layer 140B is to further increase the aperture ratio, and a plurality of bumps made of insulating material are formed on the source of the pixel TFT to prevent the second reflective bump metal layer 140B from forming. When it is on a plurality of bumps of insulating material, it is connected to the gate electrode 124i of the TFT to reduce the resistance value on the scanning line (because the area becomes larger), but the metal layer 140B in the second reflective bump area is connected to the first pixel on the pixel A reflective bump region metal layer 140A is disconnected from each other.

For the process steps of the present invention, please refer to FIG. 1C to FIG. 1H , wherein the part related to the pixel is a schematic cross-sectional diagram along a-a' of FIG. 1A .

Please refer to the cross-sectional schematic diagram shown in FIG. 1C first. Its formation steps are as follows:

First, a metal layer 105 and a polysilicon layer 110 doped with n+ conductive impurities are sequentially formed on a transparent substrate 100 from bottom to top. Then pattern the aforementioned polysilicon layer 110 and metal layer 105 by lithography and etching processes to form the source electrode 120s/drain region 120d of the n-type TFT and the predetermined source region 122s of the p-type TFT in the driving circuit region 101 'and form the source 124s/drain region 124d of the pixel TFT and the predetermined region of the storage capacitor 125 in the pixel region 102.

Next, as shown in FIG. 1D , an undoped amorphous silicon layer 130 and a gate oxide layer 135 are sequentially deposited on all surfaces. Subsequently, a laser crystallization technique is implemented to crystallize the amorphous silicon layer 130 into a polysilicon layer. Next, a portion of the gate oxide layer 135 and the non-doped amorphous silicon layer 130 are selectively removed by lithography and etching techniques to define the LDD of the n-type TFT and the predetermined region 120 of the channel, and the LDD of the pixel TFT. And the predetermined region 124 of the channel, the source/drain region of the p-type TFT and the predetermined region 122 of the channel, and the capacitor dielectric layer 135 forming the storage capacitor 125 . Here, the undoped amorphous silicon layer 130 can also be regarded as a part of the capacitor dielectric layer 135 .

Still as shown in FIG. 1D , the predetermined region 120 is partially covered on the source electrode 120s and the drain electrode 120d except between the source electrode 120s and the drain electrode 120d. Similarly, the predetermined region 122 also covers part of the p-type TFT predetermined area. The drain 120d in the region and the drain predetermined region 122S' of the p-type TFT. The predetermined area 124 of the pixel area 102 is also the same; it includes the area between the drain 124d and the source 124s and includes the portion covering it.

Then referring to FIG. 1E , a photosensitive resin layer is formed on all regions and patterned to leave only bump prototypes in the pixel region 102 . Subsequently, a process of reflowing the photosensitive resin is applied to form the first reflective bump area 129A and the second reflective bump area 129B, wherein the first reflective bump area 129A includes a plurality of bumps, and the bottom of the bumps connected to each other. In order to increase the aperture ratio, a plurality of bumps can also be selectively formed in the second reflective bump region 129B, and make the plurality of bumps straddle the signal line 124s. In this embodiment, the plurality of bumps in the first reflective bump area 129A are the main reflective areas, covering most of the pixel area 102 . And the metal layer formed on the first reflective bump region 129A can simultaneously connect the drain region 124d of the pixel TFT to the top electrode of the storage capacitor 125 . Please note that the LDD predetermined area of the pixel TFT is exposed at this time, so that the LDD implantation can be performed, and please note that the first reflective bump area 129A and the second reflective bump area 129B are disconnected from each other.

Please continue to refer to FIG. 1F , and then, a gate metal layer is formed on the surface after patterning. Then use lithography and etching process to pattern the aforementioned gate metal layer to form the first reference electrode VSS, the gate 140n of the n-type TFT in the predetermined area 120, the gate 140p of the p-type TFT in the predetermined area 122, and the pixel The gate electrode 140i of the TFT is located in the predetermined region 124, the first reflective bump metal layer 140A, and the second reflective bump metal layer 140B. Wherein, the first reflective bump metal layer 140A is connected to the top electrode of the storage capacitor 125 and the drain region 124d of the pixel TFT; the second reflective bump metal layer 140B is formed on the second reflective bump region 129B. Please note that the second reflective bump metal layer 140B can be connected to the signal line 124s of the TFT, so the area of the signal line is increased, and the resistance value can be further reduced.

In addition, an LDD predetermined area 140L of appropriate length is reserved on both sides of the gate electrode 140n of the n-type TFT. The distance between the gate 140n and the source 120s/drain region 120d of the n-type TFT can be unequal, the distance from the source 120s is short and the distance from the drain 120d is long, so as to suppress the leakage current. The gate electrode 140p of the p-type TFT located in the predetermined area 122 is reserved a source/drain electrode predetermined area 122s and 122d of an appropriate length on both sides; similarly, the gate electrode 140i of the pixel TFT located in the predetermined area 124 , and an LCD predetermined area 144L of appropriate length is reserved on the drain side of the gate 140i of the pixel TFT. The gate 144i of the pixel TFT and its source region 124s/drain region 124d are not equidistant, the distance from the source region 124s is short and the distance from the drain region 124d is long to suppress leakage current.

Subsequently, using the patterned reference electrode VSS, gate electrodes 140n, 140p, 140i, first reflective bump metal layer 140A, and second reflective bump metal layer 140B as a mask, n-type conductive impurities are implanted in all exposed The surface is used to form the LDD region 140L of the n-type TFT under the polysilicon layer under the LDD predetermined 140L, and the lightly doped source/drain (LDD) of the pixel TFT is formed by the polysilicon layer under the LDD predetermined region 144L District 144L.

Referring to FIG. 1G , a photoresist pattern layer 145 is first formed to cover the area except the p-type TFT predetermined area 122 . Then do impurity doping with p-type conductive impurities, and use the gate electrode 140p of the p-type TFT and the photoresist pattern layer 145 as a mask to form the source/drain electrodes 122s and 122d. The dose of p-type impurities will be higher than that of the LDDn-type ion implantation. So that after electrical compensation, the source 122s/drain 122d region still has a sufficient concentration of p-type impurities.

Referring to FIG. 1H , after removing the photoresist pattern layer 145 , a protective layer 160 is then formed on all surfaces and planarized. The formation method of the protection layer 160 can have the following options: for example (1) deposit a silicon nitride layer comprehensively to cover all the components in the above-mentioned driving circuit and pixel area, and then continue to deposit for planarization. (2) It is also possible to deposit a silicon nitride layer first, and then deposit another silicon oxide layer. (3) A silicon nitride layer with a partial thickness is deposited first, and then another photosensitive resin layer is deposited. Or (4) all pure materials with photosensitive resin as protective layer. In the case of the latter two containing photosensitive resin, the photosensitive resin itself can be illuminated to form a pattern of contact holes as shown in FIG. 1E . No additional photoresist is required. However, photosensitive resin usually needs to be exposed to deep ultraviolet (UV) light after formation to remove inherent color and make it transparent. In the case of (1) and (2), an additional photoresist layer is required. Then use lithography and etching technology to transfer the photoresist pattern to the silicon nitride layer, but if (3) and (4) include photosensitive resin, the photosensitive resin itself can be patterned by lithography process, saving Go to the step of forming a photoresist layer.

In addition, please note that an annealing process needs to be performed before or after the formation of the protection layer 160 in order to activate the conductive impurity ions and make the n+ doped source/drain form an ohmic contact. According to the preferred embodiment of the present application, if the protection layer 160 is made of silicon oxide or silicon nitride. The annealing can be carried out in an atmosphere containing hydrogen, so as to reduce the possible problems caused by broken bonds on the polycrystalline silicon surface. However, if the material of the protective layer 160 includes photosensitive resin, it needs to be annealed before the photosensitive resin is formed.

Finally, the passivation layer 160 is patterned to expose the first reflective bump metal layer 140A and the second reflective bump metal layer 140B, and a contact hole pattern is formed to reserve wire connection plugs.

The present invention has been described above with preferred embodiments, and those skilled in the art may make some changes and modifications without departing from the spirit of the present invention, and the scope of patent protection shall be regarded as the scope of claims and their equivalents depends on the field.

Claims (11)

1, a kind of method of making reflective liquid-crystal display is characterized in that comprising at least following steps:

Form a metal level on a substrate;

Form one first conductivity type silicon layer on this metal level;

This metal level of patterning and this first conductivity type silicon layer, with the source/drain fate that in drive circuit area, forms one first conductivity type TFT, the source electrode fate of one second conductivity type TFT and the source/drain fate that in picture element region, forms a picture element TFT, and the storage capacitors fate;

Form on the surface of an active layer after patterned;

Form a gate pole oxidation layer on this active layer;

This gate pole oxidation layer of patterning and this active layer, to form one first reserved area, one second reserved area, and one the 3rd reserved area, wherein this first reserved area is the source/drain that also partly covers this first conductivity type TFT between the source/drain of this first conductivity type TFT, this second reserved area is between the source electrode of the drain of this first conductivity type TFT and this second conductivity type TFT and part covers the drain of this first conductivity type TFT and the source electrode of this second conductivity type TFT, and the 3rd reserved area is between the source/drain of this picture element TFT and partly covers the source/drain of this picture element TFT;

Form the surface of an insulation course behind above-mentioned patterning;

This insulation course of patterning is to form plurality of bump on this picture element region; Form a gate metal level on the surface behind the above-mentioned patterning;

This gate metal level of patterning, to form reference potential connection electrode, the gate of this first conductivity type TFT, the gate of this second conductivity type TFT, the top electrodes of this storage capacitors, and on the projection of this picture element region, forming a reflective metal layer, this reflective metal layer also connects the top electrodes of this picture element TFT drain and this storage capacitors;

Imposing and gently ooze assorted drain (LDD) cloth and plant, implant this first conductive-type impurity, serves as the cover curtain with this gate metal level after patterned, forms the LDD district in order to the gate both sides at this first conductivity type TFT, also forms the LDD district in the gate both sides of this picture element TFT;

Form a photoresist design layer on the All Ranges except that this second reserved area;

Implanting one second conductive-type impurity, serves as the cover curtain with the gate of this photoresist design layer and this second conductivity type TFT, to form the source/drain of this second conductivity type TFT;

Remove this photoresist design layer;

Form a protective seam on this exposed surface; And

This protective seam of patterning is in order to remove protective seam on this picture element region reflective metal layer to expose this reflective metal layer and in the terminal contact hole that forms of this drive circuit area and picture element region.

2, the method for claim 1 is characterized in that: this first conductivity type is the n type, and this second conductivity type is the p type, and this picture element TFT is n type TFT.

3, the method for claim 1 is characterized in that: the formation step of this active layer also comprises and forms earlier an amorphous silicon layer, again through the laser crystallization to be converted into polysilicon layer.

4, the method for claim 1 is characterized in that: this insulation course is to be photosensitive resin layer.

5, the method for claim 1 is characterized in that: reach before this gate metal level step of formation after also being included in this insulation course step of patterning, impose the hot reflux step earlier, so that this projection smoothing.

6, the method for claim 1 is characterized in that: also be included in and form one second reflection projection district on the source area of picture element TFT, with the enlarged openings rate, wherein this second reflection projection district is exposed the 3rd reserved area, forms the zone to keep LDD.

7, the method for claim 1, it is characterized in that: this picture element TFT gate metal and its source/drain distance are not equidistant, the gate metal of this first conductivity type TFT and its source/drain distance are also not equidistant, this equidistantly is not to make the distance of the distance of drain and gate greater than source electrode and gate, to reduce leakage current.

8, method as claimed in claim 1 is characterized in that: this protective seam is to be selected from photosensitive resin, silicon nitride layer, silicon oxide layer one of them or wherein combination arbitrarily.

9, the method for claim 1 is characterized in that: the step of the formation of this protective seam and this protective seam of patterning also comprises deposition one photosensitive resin layer earlier, again with light shield to this photosensitive resin irradiation to form contact hole pattern.

10, method as claimed in claim 9 is characterized in that: also be included in and anneal earlier before this photosensitive resin layer forms, to activate this second conductive-type impurity.

11, the method for claim 1 is characterized in that: the step of the formation of this protective seam and this protective seam of patterning also comprises:

Deposit a silicon nitride layer;

Impose annealing, to activate this second conductive-type impurity;

Deposit this photosensitive resin layer;

This photosensitive resin layer of patterning is with exposed this reflective metal layer and form contact hole pattern; Reaching with this photosensitive resin layer is the cover curtain, and this silicon nitride layer of patterning is to finish the structure in this contact hole.

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