CN1530716A - Method for manufacturing low temperature polysilicon thin film transistor liquid crystal display - Google Patents
Method for manufacturing low temperature polysilicon thin film transistor liquid crystal display Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 42
- 239000010409 thin film Substances 0.000 title claims abstract description 18
- 229920005591 polysilicon Polymers 0.000 title claims description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000004973 liquid crystal related substance Substances 0.000 title abstract description 3
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Abstract
A method for fabricating a low temperature poly-silicon thin film transistor liquid crystal display, first sequentially forming a buffer layer and a first metal layer on a substrate. Then, a first mask is used to perform a photolithography etching process on the first metal layer to define the gate structure. Then, an insulating layer and a semiconductor layer are sequentially formed on the substrate. Then, an ion implantation process is performed on the semiconductor layer. And then, forming a second metal layer on the semiconductor layer. Then, a second mask is used to perform a photolithography etching process on the second metal layer and the semiconductor layer to define an active region, a source structure and a drain structure. Then, a passivation layer is formed on the substrate, and a third mask is used to perform a photolithography etching process on the passivation layer to expose a portion of the drain structure. Finally, a transparent electrode layer is formed on the protective layer, and a fourth photomask is used to perform a photolithography etching procedure on the transparent electrode layer to define the pixel electrode on the surface of the protective layer and electrically connect to the drain structure.
Description
Technical field
The invention relates to a kind of LTPS (Low Temperature Poly Silicon, LTPS) membrane transistor LCD, particularly a kind of method for making of Low Temperature Poly Silicon Thin Film Transistor LCD.
Background technology
Along with book film electric crystal (Thin Film Transistor, TFT) the quick progress of manufacturing technology, LCD (Liquid Crystal Display, LCD) owing to have advantages such as volume is little, in light weight, consumed power is low, and a large amount of being applied in the various electronic products such as personal digital assistant (PDA), notebook computer, high image quality color TV, mobile phone.Especially LTPS (Low Temperature PolySilicon, LTPS) the membrane transistor LCD can embed the integrated circuit (IC) of difference in functionality on glass substrate, and then reduce the quantity of the IC that uses on the module engineering, and in other words, the minimizing of module contact and fiduciary level lifting.In addition, to also have the degree of excursion of carrier (electronics or electric hole) be 300 times of amorphous silicon (amorphous silicon), low power consumption, high brightness, high-res, compact, high-quality and perfect system combination to the characteristics of this display.
Please refer to Fig. 1, is the basic structure of a Low Temperature Poly Silicon Thin Film Transistor LCD.Its method for making at first forms cushion 12 and the first metal layer in regular turn on substrate 10, then use the first road light shield that the first metal layer is carried out the lithography program, with the gate structure 14 that defines membrane transistor.Depositing insulating layer 16 and semiconductor layer 18 in regular turn on substrate 10 then use the active region (island) of the second road light shield with the definition membrane transistor again.Use the 3rd road light shield to define the photoresistance pattern then, as the barrier layer of ion implantation.The then isolated dielectric layer of deposition (InterLayer Dielectric, ILD) 20, and use the 4th road light shield that isolated dielectric layer 20 is carried out etching program to expose the part drain zone of electric crystal, with the definition contact hole.Deposit second metal level 22 subsequently, fill and cover above-mentioned contact hole, re-use the 5th road light shield, second metal level 22 is carried out etching program, to define the drain structure of electric crystal.Then deposit protective seam 24, and use the 6th road light shield that protective seam 24 is carried out etching program, to expose part drain structure.At last, form transparency conducting layer on protective seam 24, then use the pixel electrode 26 of the 7th road light shield to define membrane transistor.
Wherein above-mentioned processing procedure has used the formality of seven road light shields altogether, and one light shield of every use not only increases cost, and the adjustment of process parameter expends time in especially, and one formality of every many increases is exactly to increase the source that may produce error.So, if can reduce the usage quantity of light shield as far as possible, for the producer, can not only reach simultaneously and retrench cost, shorten the processing procedure time, promote also to have much for the yield (yield) of product and benefit.And can effectively reduce the usage quantity of light shield by method for making provided by the invention.
Summary of the invention
Purpose of the present invention is for providing a kind of method of making the Low Temperature Poly Silicon Thin Film Transistor LCD.
A further object of the present invention can be made the manufacture method of Low Temperature Poly Silicon Thin Film Transistor LCD for a kind of minimizing micro-photographing process program is provided.
The object of the present invention is achieved like this, a kind of manufacture method that on substrate, forms the Low Temperature Poly Silicon Thin Film Transistor LCD, and this method comprises the following step at least:
Form a cushion on this substrate:
Form a first metal layer on this cushion;
Use one first light shield that this first metal layer is carried out the lithography program, with the gate structure of definition membrane transistor;
Form an insulation course on this cushion, this gate structure and this substrate surface;
Form semi-conductor layer on this insulation course, use as the passage area of this membrane transistor;
This semiconductor layer is carried out the ion implantation program;
Form one second metal level on this semiconductor layer;
Use one second light shield that this second metal level and this semiconductor layer are carried out the lithography program, with active area and source configuration and the drain structure that defines this membrane transistor;
Form a protective seam on this substrate;
Use one the 3rd light shield that this protective seam is carried out the lithography program, to expose the subregion of this drain structure;
Form a transparent electrode layer on this protective seam; And
Use one the 4th light shield that this transparent electrode layer is carried out the lithography program, in this protective seam surface, and be electrically connected to this drain structure with the definition pixel electrode.
More comprise this semiconductor layer is carried out excimer laser tempering program, make the amorphous silicon structure of this semiconductor layer transfer the polysilicon structure to.
Above-mentioned ion implantation program more comprises the following step:
Be coated with photoresistance on this semiconductor layer, and this substrate imposed the back-exposure program, define a photoresistance pattern:
With this photoresistance pattern is the cover curtain, and this substrate is imposed ion implantation; And remove this photoresistance pattern.
The second above-mentioned light shield is to use wherein a kind of of half tone light shield and slit light shield.
When this second metal level and this semiconductor layer are carried out the lithography program, more comprise the program of a removing photoresistance.
The present invention can also realize in following mode: a kind of manufacture method that on substrate, forms the Low Temperature Poly Silicon Thin Film Transistor LCD, and this method comprises the following step at least:
Form a cushion on this substrate;
Form a first metal layer on this cushion, and this first metal layer is carried out the first lithography program, with the gate structure of definition membrane transistor;
Form an insulation course on this cushion, this gate structure and this substrate surface;
Form semi-conductor layer on this insulation course, use as the passage area of membrane transistor;
Be coated with photoresistance in this semiconductor layer, and this substrate imposed the back-exposure program, define one first photoresistance pattern:
With this first photoresistance pattern is the cover curtain, and this substrate is imposed ion implantation; Remove this first photoresistance pattern;
Form one second metal level on this semiconductor layer, and this second metal level and this semiconductor layer are carried out the second lithography program, with active area and source configuration and the drain structure that defines this membrane transistor;
Form a protective seam on this substrate, and this protective seam is carried out the 3rd lithography program, to expose the subregion of this drain structure; And
Form a transparent electrode layer in this protective seam surface, and this transparent electrode layer carried out the 4th lithography program, in this protective seam surface, and be electrically connected to this drain structure with the definition pixel electrode:
The second wherein above-mentioned lithography program is after forming this second metal level, the coating photoresistance is in this first metal layer upper surface earlier, and utilize half tone light shield and wherein a kind of one second photoresistance pattern that defines of slit light shield, make this second photoresistance pattern top to should the gate structure place, has an opening, again through an etching program, with active area and source configuration and the drain structure that defines this membrane transistor.
More comprise this semiconductor layer is carried out excimer laser tempering program, make the amorphous silicon structure of this semiconductor layer transfer the polysilicon structure to.
When this second metal level and this semiconductor layer are carried out the first lithography program, more comprise the program of a removing photoresistance.
A kind of manufacture method that on substrate, forms the Low Temperature Poly Silicon Thin Film Transistor LCD, this method comprises the following step at least:
Form a cushion on this substrate;
Form a first metal layer on this cushion;
Use one first light shield that this first metal layer is carried out the lithography program, with the gate structure of definition membrane transistor;
Form an insulation course on this cushion, this gate structure and this substrate surface;
Form an amorphous silicon layer on this insulation course, use as the passage area of this membrane transistor;
This amorphous silicon layer is carried out excimer laser tempering program, make this amorphous silicon layer transfer a polysilicon layer to;
Be coated with photoresistance on this polysilicon layer, and this substrate is imposed the back-exposure program, to define one first photoresistance pattern on this polysilicon layer;
With this first photoresistance pattern is the cover curtain, and this substrate is imposed ion implantation; Remove this first photoresistance pattern;
Form one second metal level on this polysilicon layer;
Use one second light shield to define one second photoresistance pattern on this second metal level, wherein this second photoresistance pattern top has an opening to should the gate structure place;
With this second photoresistance pattern is etch mask, and this second metal level and this polysilicon layer are carried out etching program, with active area and source configuration and the drain structure that defines this membrane transistor;
Remove this second photoresistance pattern;
Form a protective seam on this substrate;
Use one the 3rd light shield that this protective seam is carried out the lithography program, to expose the subregion of this drain structure;
Form a transparent electrode layer on this protective seam; And
Use one the 4th light shield that this transparent electrode layer is carried out the lithography program, in this protective seam surface, and be electrically connected to this drain structure with the definition pixel electrode.
The second above-mentioned light shield is to use wherein a kind of of half tone light shield and slit light shield.
When this second metal level and this polysilicon layer are carried out the etching journey, more comprise the program of a removing photoresistance.
According to preferred embodiment of the present invention, provide a kind of manufacture method that on substrate, forms LTPS (LTPS) membrane transistor LCD (TFT-LCD).Deposit cushion, the first metal layer at first in regular turn on this substrate.Then, use first light shield that the first metal layer is carried out the lithography program, to define the gate structure of membrane transistor.Subsequently more in regular turn depositing insulating layer, amorphous silicon layer on substrate, and the amorphous silicon layer carried out excimer laser tempering (ELA) program, make amorphous silicon transfer polysilicon to, use with passage area as electric crystal.
Then be coated with photoresistance on the polysilicon layer, and substrate is imposed the back-exposure program, to define the first photoresistance pattern on the polysilicon layer.Serve as the cover curtain with the first photoresistance pattern again, substrate is imposed ion implantation.Then, deposit second metal level on the polysilicon layer, and use second light shield to define the second photoresistance pattern on second metal level.Be etch mask then, second metal level and polysilicon layer carried out etching program, to define active area, source configuration and drain structure with the second photoresistance pattern.Deposit protective seam on substrate, and use the 3rd light shield that protective seam is carried out the lithography program, to expose the subregion of drain structure.Then the sputter transparent electrode layer is on protective seam, and uses the 4th light shield that transparent electrode layer is carried out the lithography program, in the protective seam surface, and is electrically connected to the drain structure with the definition pixel electrode.
Utilize the present invention to make the Low Temperature Poly Silicon Thin Film Transistor LCD and have considerable advantage.At first, when carrying out the implanting ions of doped region, traditional way is the step that sees through micro-photographing process with one light shield, the polysilicon layer is carried out ion implant; And the rule of doing of the present invention is to utilize the program of back-exposure, under the formality and cost that must not increase by one light shield, can reach identical effect, What is more, see through the result that back-exposure also can reach autoregistration (self-align), contingent skew (shift) thereby cause critical size (Critical Dimension, error CD) in the time of can avoiding using light shield fully.In addition, nationality and is used the second road light shield in the present invention, can define the active area (island) of membrane transistor and source electrode, drain structure simultaneously; Compare traditional way, must use the formality of twice light shield respectively, the processing procedure of one light shield only according to the present invention can reach identical result.In sum, compared to the processing procedure of six to the seven road light shields of making the Low Temperature Poly Silicon Thin Film Transistor LCD traditionally, being reduced to only needs four road light shields can reach identical structure, and cost of being saved and processing procedure time can say so quite huge.
Description of drawings
Fig. 1 is the substrate sectional view that utilizes the formed Low Temperature Poly Silicon Thin Film Transistor LCD of conventional art;
Fig. 2 is the substrate sectional view that utilizes the present invention to deposit cushion and define the step of gate structure;
Fig. 3 utilizes the continue substrate sectional view of step of depositing insulating layer, semiconductor layer of the present invention;
Fig. 4 utilizes the present invention to be coated with the substrate sectional view of photoresistance in the step of semiconductor layer;
Fig. 5 serves as the cover curtain for utilizing the present invention with the first photoresistance pattern, the substrate sectional view of the step in definition semiconductor layer doped district;
Fig. 6 utilizes continue deposition second metal level and define the substrate sectional view of the step of the second photoresistance pattern of the present invention;
Fig. 7 utilizes the present invention to define the substrate sectional view of the step of source configuration and drain structure; And
Fig. 8 is the substrate sectional view that utilizes the step of pixel electrode of the present invention on protective seam.
The figure number explanation
10,30 substrates, 12,32 cushions
14,34 flashboard structures, 16,36 insulation courses
18,38 semiconductor layers, 20 exhausted dielectric layers
22,43 second metal levels, 24,50 protective seams
26,52 pixel electrodes, 40 photoresistances
42 first photoresistance patterns, 44 second photoresistance patterns
46 source configuration, 48 drain structures
50 protective seams, 52 pixel electrodes
Embodiment
Disclosed is a kind of manufacture method that forms LTPS (LTPS) membrane transistor LCD (TFT-LCD) on substrate.In order to make narration of the present invention more detailed and complete, can and cooperate that Fig. 2's to Fig. 8 is graphic with reference to following description.Relevant of the present invention be described in detail as follows described.
Please refer to Fig. 2, the preferred embodiment according to the present invention at first forms cushion (bufferlayer) 32 on substrate 30.Aforesaid substrate 30 can use glass, quartz or similar transparent insulation material.Can select general dielectric materials such as oxide or nitride as for 32 of cushions, its role is to avoid the impurity in the substrate 30 to diffuse out because of follow-up higher temperatures processing procedure.Then, form the first metal layer on this cushion 32.The deposition of the first metal layer then can be formed at metallic film on the surface of substrate 30 through such as physical vapour deposition (PVD) programs such as sputtering methods.Wherein, be used for constituting the material of the first metal layer, can select metal or alloy such as molybdenum, tantalum, chromium, tungsten, aluminium, titanium.Then use first light shield that this first metal layer is carried out the lithography program, with the gate structure 34 of definition membrane transistor.In preferred embodiment, can be coated with photoresist earlier on the first metal layer, and use first light shield to photoresist expose, the development supervisor, to define a photoresistance pattern, be etch mask with the photoresistance pattern again, the first metal layer is carried out etching program, as the universe etching of Wet-type etching or reactive ion etching (RIE), with the gate structure 34 of definition membrane transistor.As being familiar with known to this skill person, in the program of electrode structure 34, electric capacity storage electrode, the scan line structure (all not being shown among the figure) that can define substrate 30 surfaces usually simultaneously are general between definition.
Then please refer to Fig. 3, go up depositing insulating layer 36 with substrate 30 surfaces in cushion 32, gate structure 34.The material of insulation course 36 can adopt such as oxidation silicon (SiO
2), silicon nitride (SiN
x), nitrogen oxidation silicon suitable materials such as (SiNO), and nationality low temperature chemical vapor deposition method (PECVD) and is constituted.Subsequently, depositing semiconductor layers 38 is on insulation course 36, and semiconductor layer 38 carried out excimer laser tempering (ELA) program, and make that the structure crystalline transition of original amorphous silicon is the structure of polysilicon (poly-Si), use in order to passage (channel) zone as the subsequent thin film electric crystal.
Please refer to Fig. 4, then be coated with photoresistance 40 on semiconductor layer 38, and to substrate 30 sides with back-exposure (backside exposure) program, to define the first photoresistance pattern 42 on semiconductor layer 38.Wherein the back-exposure program be with a light source from substrate 30 bottoms projections and go out, through stopping of gate structure 34, make the photoresistance of gate structure 34 upper areas not be subjected to the irradiation of light, reach the effect of autoregistration (self-align).Behind a developing programs, the photoresistance of light area then can be dissociated into the material that is soluble in developer, and defines the first photoresistance pattern 42 (as shown in Figure 5) again.Then, please refer to Fig. 5, serves as cover curtain (mask) with the first photoresistance pattern 42, and substrate 30 is imposed implanting ions.With the n type, select to carry out ion implantation (ion implantation) as the foreign ion of pentavalents such as phosphorus, arsenic; With the p type, select foreign ion as trivalents such as boron, galliums.It then is removable this first photoresistance pattern 42.
Please refer to Fig. 6, sputter second metal level 43 is on semiconductor layer 38.Then, use second light shield to define the second photoresistance pattern 44 on second metal level 43.In preferred embodiment of the present invention, can be coated with photoresist earlier on second metal level 43, then use half tone light shield or slit light shield, make corresponding gate structure 34 places, photoresistance pattern 44 tops that win, have an open area.Then, be etch mask with this second photoresistance pattern 44, respectively second metal level 43 is carried out etching program with semiconductor layer 38, with the active area (island) that defines electric crystal.Again as shown in Figure 7, elder generation is through the program of removing photoresistance (ashing), and action is controlled at the first metal layer 43 of removing the passage area top exposes promptly and stop, be etch mask then with the first photoresistance pattern 44, second metal level 43 is carried out etching program, with source configuration 46 and the drain structure 48 that defines membrane transistor.Be the removable second photoresistance pattern 44 subsequently.
Please refer to Fig. 8, on substrate 30, form protective seam 50.Deposition protective seam 50 then uses the 3rd light shield that protective seam 50 is carried out the lithography program on substrate 30, with formation contact hole (comtact hole), and exposes part drain structure 48 surfaces, that is Metal Contact district (comtact area).In preferable enforcement was lived, protective seam 50 herein can be selected to be made of the silicon nitride material.Then, on protective seam 50, form transparent electrode layer again.Use the 4th light shield that transparent electrode layer is carried out the lithography program then, in protective seam 50 surfaces, and be electrically connected to this drain structure 48 with definition pixel electrode 52.Wherein the material of transparent electrode layer can be selected the electrically conducting transparent material, as: tin indium oxide (ITO) or indium zinc oxide (IZO) etc., its thin film-forming method have the resistance heated of universe formula or the methods such as wireless plating technology of vacuum vapour deposition, ionization vapour deposition method and sputtering method or wet type that electron beam heats to make.
Sum up above-mentionedly, method for making according to the present invention is as described in following about the use of light shield:
(1) use first light shield that the first metal layer is carried out the lithography program, to define the gate structure of membrane transistor;
(2) use first light shield that second metal level is carried out the lithography program, with source configuration and the drain structure that defines membrane transistor;
(3) use the 3rd light shield that protective seam is carried out the lithography program, to expose the subregion of drain structure;
(4) use the 4th light shield that transparent electrode layer is carried out the lithography program, defining pixel electrode, and be electrically connected to the drain structure in the protective seam surface.
Claims (11)
1, a kind of manufacture method that on substrate, forms the Low Temperature Poly Silicon Thin Film Transistor LCD, this method comprises the following step at least:
Form a cushion on this substrate:
Form a first metal layer on this cushion;
Use one first light shield that this first metal layer is carried out the lithography program, with the gate structure of definition membrane transistor;
Form an insulation course on this cushion, this gate structure and this substrate surface;
Form semi-conductor layer on this insulation course, use as the passage area of this membrane transistor;
This semiconductor layer is carried out the ion implantation program;
Form one second metal level on this semiconductor layer;
Use one second light shield that this second metal level and this semiconductor layer are carried out the lithography program, with active area and source configuration and the drain structure that defines this membrane transistor;
Form a protective seam on this substrate;
Use one the 3rd light shield that this protective seam is carried out the lithography program, to expose the subregion of this drain structure;
Form a transparent electrode layer on this protective seam; And
Use one the 4th light shield that this transparent electrode layer is carried out the lithography program, in this protective seam surface, and be electrically connected to this drain structure with the definition pixel electrode.
2, the method for claim 1 is characterized in that, more comprises this semiconductor layer is carried out excimer laser tempering program, makes the amorphous silicon structure of this semiconductor layer transfer the polysilicon structure to.
3, the method for claim 1 is characterized in that, above-mentioned ion implantation program more comprises the following step:
Be coated with photoresistance on this semiconductor layer, and this substrate imposed the back-exposure program, define a photoresistance pattern:
With this photoresistance pattern is the cover curtain, and this substrate is imposed ion implantation; And remove this photoresistance pattern.
4, the method for claim 1 is characterized in that, the second above-mentioned light shield is to use wherein a kind of of half tone light shield and slit light shield.
5, the method for claim 1 is characterized in that, when this second metal level and this semiconductor layer are carried out the lithography program, more comprises the program of a removing photoresistance.
6, a kind of manufacture method that on substrate, forms the Low Temperature Poly Silicon Thin Film Transistor LCD, this method comprises the following step at least:
Form a cushion on this substrate;
Form a first metal layer on this cushion, and this first metal layer is carried out the first lithography program, with the gate structure of definition membrane transistor;
Form an insulation course on this cushion, this flashboard structure and this substrate surface;
Form semi-conductor layer on this insulation course, use as the passage area of membrane transistor;
Be coated with photoresistance in this semiconductor layer, and this substrate imposed the back-exposure program, define one first photoresistance pattern:
With this first photoresistance pattern is the cover curtain, and this substrate is imposed ion implantation; Remove this first photoresistance pattern;
Form one second metal level on this semiconductor layer, and this second metal level and this semiconductor layer are carried out the second lithography program, with the active area and the source configuration that define this membrane transistor and draw plate structure;
Form a protective seam on this substrate, and this protective seam is carried out the 3rd lithography program, to expose the subregion of this drain structure; And
Form a transparent electrode layer in this protective seam surface, and this transparent electrode layer is carried out the 4th lithography program, in this protective seam surface, and be electrically connected to this drain structure with the definition pixel electrode;
The second wherein above-mentioned lithography program is after forming this second metal level, the coating photoresistance is in this first metal layer upper surface earlier, and utilize half tone light shield and wherein a kind of one second photoresistance pattern that defines of slit light shield, make this second photoresistance pattern top to should the flashboard structure place, has an opening, again through an etching program, with active area and source configuration and the drain structure that defines this membrane transistor.
7, method as claimed in claim 6 is characterized in that, more comprises this semiconductor layer is carried out excimer laser tempering program, makes the amorphous silicon structure of this semiconductor layer transfer the polysilicon structure to.
8, method as claimed in claim 6 is characterized in that, when this second metal level and this semiconductor layer are carried out the first lithography program, more comprises the program of a removing photoresistance.
9, a kind of manufacture method that on substrate, forms the Low Temperature Poly Silicon Thin Film Transistor LCD, this method comprises the following step at least:
Form a cushion on this substrate;
Form a first metal layer on this cushion;
Use one first light shield that this first metal layer is carried out the lithography program, with the gate structure of definition membrane transistor;
Form an insulation course on this cushion, this gate structure and this substrate surface;
Form an amorphous silicon layer on this insulation course, use as the passage area of this membrane transistor;
This amorphous silicon layer is carried out excimer laser tempering program, make this amorphous silicon layer transfer a polysilicon layer to;
Be coated with photoresistance on this polysilicon layer, and this substrate is imposed the back-exposure program, to define one first photoresistance pattern on this polysilicon layer;
With this first photoresistance pattern is the cover curtain, and this substrate is imposed ion implantation; Remove this first photoresistance pattern;
Form one second metal level on this polysilicon layer;
Use one second light shield to define one second photoresistance pattern on this second metal level, wherein this second photoresistance pattern top has an opening to should the gate structure place;
With this second photoresistance pattern is etch mask, and this second metal level and this polysilicon layer are carried out etching program, with active area and source configuration and the drain structure that defines this membrane transistor;
Remove this second photoresistance pattern;
Form a protective seam on this substrate;
Use one the 3rd light shield that this protective seam is carried out the lithography program, to expose the subregion of this drain structure;
Form a transparent electrode layer on this protective seam; And
Use one the 4th light shield that this transparent electrode layer is carried out the lithography program, in this protective seam surface, and be electrically connected to this drain structure with the definition pixel electrode.
10, method as claimed in claim 9 is characterized in that, the second above-mentioned light shield is to use wherein a kind of of halftone light shield and slit light shield.
11, method as claimed in claim 9 is characterized in that, when this second metal level and this polysilicon layer are carried out the etching journey, more comprises the program of a removing photoresistance.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031193307A CN1324388C (en) | 2003-03-14 | 2003-03-14 | Manufacturing method of low temperature polysilicon thin film transistor liquid crystal display |
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| CNB031193307A CN1324388C (en) | 2003-03-14 | 2003-03-14 | Manufacturing method of low temperature polysilicon thin film transistor liquid crystal display |
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| CN1530716A true CN1530716A (en) | 2004-09-22 |
| CN1324388C CN1324388C (en) | 2007-07-04 |
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| CN100359399C (en) * | 2005-01-31 | 2008-01-02 | 广辉电子股份有限公司 | Method for manufacturing thin film transistor of liquid crystal display |
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Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW540828U (en) * | 1991-08-23 | 2003-07-01 | Semiconductor Energy Lab | Semiconductor device |
| JP3146113B2 (en) * | 1994-08-30 | 2001-03-12 | シャープ株式会社 | Method of manufacturing thin film transistor and liquid crystal display device |
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| JP4715016B2 (en) * | 2001-02-15 | 2011-07-06 | ソニー株式会社 | Method for evaluating polysilicon film |
| US20020117718A1 (en) * | 2001-02-28 | 2002-08-29 | Apostolos Voutsas | Method of forming predominantly <100> polycrystalline silicon thin film transistors |
| CN1154174C (en) * | 2001-05-30 | 2004-06-16 | 友达光电股份有限公司 | Method for manufacturing flat panel display |
| CN1391269A (en) * | 2001-06-07 | 2003-01-15 | 矽统科技股份有限公司 | Method and structure for preventing via from overetching |
-
2003
- 2003-03-14 CN CNB031193307A patent/CN1324388C/en not_active Expired - Lifetime
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| CN100359399C (en) * | 2005-01-31 | 2008-01-02 | 广辉电子股份有限公司 | Method for manufacturing thin film transistor of liquid crystal display |
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| CN104157609A (en) * | 2014-08-20 | 2014-11-19 | 深圳市华星光电技术有限公司 | Manufacture method of TFT substrate, and structure of the TFT substrate |
| TWI660075B (en) * | 2017-12-01 | 2019-05-21 | 財團法人金屬工業研究發展中心 | Method for manufacturing polysilicon layer, heterojunction solar cell and manufacturing method thereof |
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