JP2013084977A - Method for manufacturing thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a TFT having high light resistance with suppressed light leakage current at a low cost by simplifying a manufacturing process.
A TFT 100 includes a light shielding film 113 formed on a glass substrate as an insulating substrate 107, an insulating film 112 formed on the light shielding film 113, a semiconductor film 111 formed on the insulating film 112, and A gate insulating film 104 formed over the semiconductor film 111 is basically included. In the stacked body 100a including the light shielding film 113, the insulating film 112, and the semiconductor film 111, each layer is patterned at the same time. Each layer of the stacked body 100a is made of silicon or a material containing silicon.
[Selection] Figure 1

Description

  The present invention relates to a method for manufacturing a thin film transistor, and more particularly to a method for manufacturing a thin film transistor having a semiconductor thin film having photosensitivity and used under light irradiation.

  As a driving device for an active matrix liquid crystal display panel, it is widely known that a thin film transistor (hereinafter referred to as “TFT (Thin Film Transistor)”) is formed on an insulating substrate such as a glass substrate. In recent years, TFTs having high durability and reliability have been required due to multifunctionalization and miniaturization of semiconductor devices including TFTs. In addition, with the increase in image quality of liquid crystal displays and the expansion of general-purpose applications, there is an increasing demand for increasing the brightness of backlights mounted on liquid crystal displays.

  In general, an amorphous silicon thin film or a polycrystalline silicon thin film is used for the TFT. In these semiconductor materials typified by silicon, electron-hole pairs are excited and generated by light energy under light irradiation. This electron-hole pair is observed as an increase in off-leakage current, particularly by functioning as a carrier when the TFT is turned off. In such a case, in the charge holding type element such as a liquid crystal display element, the charge to be held changes due to the leakage current, and thus there is a problem that the image quality such as the contrast reduction and the crosstalk image is deteriorated. there were.

  In order to cope with such a problem, Patent Document 1 discloses a technique for blocking light irradiated to an active layer of a TFT with a film having a light blocking function.

  FIG. 9 is a cross-sectional view showing the TFT of Patent Document 1. As shown in FIG. Hereinafter, description will be given based on this drawing. In the following description, polycrystalline silicon and amorphous silicon are abbreviated as “poly-Si” and “a-Si”, respectively.

The TFT 200 is formed on a glass substrate 207, and includes a WSi film 221, an insulating film 223, an a-Si film 222, an insulating film 212, a poly-Si film 211, a gate SiO ₂ film 204, a gate Cr / n ⁺ film 210, and an interlayer. An SiO ₂ film 203, a wiring Ti / Al film 209, a SiN protective film 202, a planarizing film 201, a pixel ITO (Indium Tin Oxide) film 208, and the like are included. Here, the configuration from the WSi film 221 to the gate Cr / n ⁺ film 210 is referred to as a TFT 200.

  According to this TFT, a first light-shielding film, a first insulating film, a second light-shielding film, and a second insulating film are provided below the semiconductor film to try to block light. That is, as shown in FIG. 9, below the poly-Si film 211, a WSi film 221 that is one light shielding film, an insulating film 223, an a-Si film 222 that is the other light shielding film, and an insulating film 212 are provided from below. ing. Each light shielding film is patterned in an area larger than that of the poly-Si film 211, and has a function of reducing the amount of light reaching the poly-Si film 211 with respect to incident light from the glass substrate 207 side.

  Moreover, in the TFT described in Patent Document 2, a laminated body including three layers of a light shielding film, an insulating film, and a semiconductor film is simultaneously patterned. Here, the light shielding film is a metal such as Cr, the insulating film is silicon oxide, and the semiconductor film is poly-Si.

Japanese Patent Laying-Open No. 2004-302475 (FIG. 2B, etc.) Japanese Patent Laid-Open No. 9-213964 (FIG. 1B, etc.)

  However, the TFT disclosed in Patent Document 1 has the following problems. As described above, since the first light shielding film, the first insulating film, the second light shielding film, and the second insulating film are provided under the semiconductor film, the first light shielding film is formed and patterned. (Lithography and etching), film formation of the second insulating film, film formation of the second light-shielding film, patterning thereof, and further formation of the second insulating film are required. That is, when trying to obtain a TFT with high light resistance, there is a problem that the manufacturing process is complicated, resulting in an increase in manufacturing cost.

  On the other hand, in the TFT of Patent Document 2, the light shielding film is a metal such as Cr, while the insulating film and the semiconductor film are silicon-based materials. Therefore, after forming the light shielding film by sputtering or vapor deposition, it is necessary to form the insulating film and the semiconductor film by plasma CVD. As described above, since the TFT of Patent Document 2 uses two or more kinds of film forming apparatuses for forming the laminate, the manufacturing process is complicated, which increases the manufacturing cost. In addition, since each layer of the stacked body is patterned at the same time, the step around the periphery of the stacked body is considerably larger than when the layers are individually patterned. Therefore, the step coverage of the gate insulating film covering the step on the periphery of the stacked body is extremely deteriorated, which causes a problem that a gate leakage current is likely to occur.

  Therefore, an object of the present invention is to provide a TFT manufacturing method that solves such problems and realizes high light resistance with suppressed light leakage current at a low cost by simplifying the manufacturing process. .

  A method for manufacturing a TFT according to the present invention includes a method for manufacturing a thin film transistor, a light shielding film formed on an insulating substrate, an insulating film formed on the light shielding film, a semiconductor film formed on the insulating film, A method of manufacturing a thin film transistor having a gate insulating film formed on a semiconductor film, wherein the light shielding film, the insulating film, and the semiconductor film are made of silicon or a material containing silicon, and are formed in the same CVD apparatus. The light shielding film, the insulating film, and the semiconductor film are successively formed on the insulating substrate, and then the light shielding film, the insulating film, and the semiconductor film are simultaneously patterned in the same etching apparatus.

  According to the present invention, each layer of the stacked body including the light shielding film, the insulating film, and the semiconductor film is made of silicon or a material containing silicon, so that each layer can be continuously formed by the same film forming apparatus and the same etching apparatus. Since the patterning can be performed collectively, the manufacturing process can be greatly simplified. Therefore, a TFT having high light resistance with suppressed light leakage current can be realized at low cost.

It is sectional drawing which shows the 1st and 3rd Example of TFT which concerns on this invention. It is sectional drawing (the 1) which shows the 1st and 2nd Example of the manufacturing method of TFT which concerns on this invention, and a process progresses in order of FIG. 2 [1]-FIG. 2 [3]. It is sectional drawing (the 2) which shows the 1st and 2nd Example of the manufacturing method of TFT which concerns on this invention, and a process progresses in order of FIG. 3 [1] and FIG. 3 [2]. FIG. 4 is a chart showing optical characteristics of a-Si and poly-Si used in the TFT of FIG. 1, in which FIG. 4 [1] is a-Si and FIG. 4 [2] is poly-Si. FIG. 5 is a graph showing the Vg-Id characteristics of the TFT of FIG. 1, in which FIG. 5 [1] is an n-channel TFT and FIG. 5 [2] is a p-channel TFT. FIGS. 6A and 6B are cross-sectional views illustrating a second embodiment of a TFT according to the present invention, in which FIG. 6 [1] is an example of a taper shape, and FIG. 6 [2] is an example of a step shape. 1 is a perspective view showing a first embodiment of an active matrix substrate according to the present invention. 1 is a perspective view showing a first embodiment of an electronic device according to the present invention. It is sectional drawing which shows TFT of patent document 1. FIG.

  FIG. 1 is a sectional view showing a first embodiment of a TFT according to the present invention. Hereinafter, description will be given based on this drawing.

The TFT 100 of this embodiment includes a light shielding film 113 formed on a glass substrate as the insulating substrate 107, an insulating film 112 formed on the light shielding film 113, a semiconductor film 111 formed on the insulating film 112, A gate insulating film 104 formed over the semiconductor film 111 is basically included. In the stacked body 100a including the light shielding film 113, the insulating film 112, and the semiconductor film 111, each layer is patterned at the same time. Each layer of the stacked body 100a is made of silicon or a material containing silicon. The light shielding film 113 is made of a-Si and has a film thickness of 10 nm, for example. The insulating film 112 is made of SiO ₂ and has a thickness of 10 nm, for example. The semiconductor film 111 is made of poly-Si and has a thickness of 50 nm, for example. The gate insulating film 104 made of SiO _2.

  Light irradiated from the insulating substrate 107 side is blocked by the light shielding film 113 on the way to the semiconductor film 111. On the other hand, the insulating film 112 prevents an electrical influence on the semiconductor film 111 by the light shielding film 113. As a result, the light leakage current of the TFT 100 is suppressed by the light shielding film 113 and the insulating film 112. Here, each layer of the stacked body 100a is made of silicon or a material containing silicon. Therefore, for example, by using the same film forming gas for each layer, it becomes easy to continuously form each layer with the same film forming apparatus. Further, for example, by using the same etching gas for each layer, it becomes easy to perform patterning in a lump with the same etching apparatus. Therefore, the manufacturing process can be greatly simplified as compared with the case where each layer is formed separately and patterned separately. When the layers of the stacked body 100a are simultaneously patterned, the stacked body 100a has side surfaces that are symmetric in the cross-sectional shape in the film thickness direction. If each layer is patterned separately, the cross-sectional shape in the film thickness direction of the laminate becomes asymmetrical due to the positional deviation of the alignment accuracy level of the exposure apparatus.

The material containing silicon may be a material mainly containing silicon. Examples of the material containing silicon as a main component include silicon oxide, silicon nitride, and silicide. Silicide is a compound consisting of metal and silicon. For example, refractory metal silicides such as WSi ₂ , MoSi ₂ , TiSi ₂ , TaSi ₂ can be used.

  As in this embodiment, the semiconductor film 111 and the light shielding film 113 may be made of silicon, and the insulating film 112 may be made of silicon oxide. In this case, since it is easy to use the same film forming gas (for example, silane) for each layer, it is more preferable to continuously form each layer with the same film forming apparatus (for example, plasma CVD apparatus). It becomes easy. Further, since it is easy to use a similar etching gas (for example, carbon tetrafluoride) for each layer, it becomes easier to perform patterning in a batch with the same etching apparatus (for example, a plasma etching apparatus). .

  In other words, if the light shielding film 113 is made of silicon, the insulating film 112 is made of silicon oxide, and the semiconductor film 111 is made of silicon, the film forming apparatus can be shared in the film forming process, that is, continuous film forming in one film forming apparatus. This also facilitates batch processing with a dry etching apparatus for patterning a semiconductor film during etching.

  As in this embodiment, the semiconductor film 111 may be made of poly-Si, and the light shielding film 113 may be made of a-Si. Since poly-Si has a higher carrier mobility than a-Si, it is suitable for the semiconductor film 111 of the TFT, and a-Si has a better light absorption rate than poly-Si, and is therefore suitable for the light-shielding film 113.

  In addition, the total sum of the thicknesses of the layers of the stacked body 100a is preferably equal to or less than the thickness of the gate insulating film 104. In this case, since the height of the step on the periphery of the stacked body 100a is equal to or less than the film thickness of the gate insulating film 104, the step is easily covered with the gate insulating film 104. Therefore, the step coverage of the gate insulating film 104 is reduced. Can be improved.

  Next, the TFT 100 of this embodiment will be described in more detail. Hereinafter, material names are written in parentheses on each film as necessary.

In the TFT 100 of the present embodiment, a base film (SiN) 106, a base film (SiO ₂ ) 105, a light shielding film (a-Si) 113, and an insulating film (SiO ₂ ) 112 are provided on an insulating substrate (glass) 107. A semiconductor film (poly-Si) 111 is provided. The semiconductor film 111 includes a source region 111a, an LDD (Lightly Doped Drain) region 111b, a channel region 111c, an LDD region 111d, and a drain region 111e from the left in the drawing. The source region 111 a and the drain region 111 e are a pair of impurity regions connected to a pair of wiring films (Ti / Al) 109. The channel region 111 c is located immediately below the gate electrode (Cr / n ⁺ ) 110. The LDD regions 111b and 111d are a pair of low-concentration impurity regions formed between the channel region 111c and the source region 111a and drain region 111e. Here, a configuration from the light shielding film 113 to the gate electrode 110 is referred to as a TFT 100.

In addition, a gate insulating film 104 is provided so as to cover the semiconductor film 111, a gate electrode 110 and an interlayer insulating film (SiO ₂ ) 103 are provided thereon, and a source electrode is formed thereon via a contact hole 109a. A wiring film 109 is provided as a drain electrode. Further, a protective film (SiN) 102 and a planarizing film 101 are provided thereon, and a pixel film (ITO) 108 is provided thereon via a contact hole 108a. The pixel film 108 functions as a pixel electrode of the liquid crystal display.

  Unlike a single crystal silicon, a poly-Si thin film has a polycrystalline grain boundary. Therefore, when a high electric field is applied to the drain end, a leak current flows between bands via defects present in the grain boundary. For this reason, the off-leakage current of a TFT composed of a poly-Si thin film increases depending on the drain-gate voltage. Therefore, by adopting an LDD structure, the electric field at the drain end is relaxed, and the drain-gate voltage dependence of the off-leakage current is eliminated.

  In this way, it is possible to reduce the off-leak current in the dark state of the TFT 100. However, when the semiconductor film 111 is irradiated with light, the leakage current increases according to the amount of light. In this embodiment, since the light shielding film 113 is disposed under the semiconductor film 111 via the insulating film 112, the amount of light reaching the semiconductor film 111 due to reflection and absorption by the light shielding film 113 is reduced. The optical off-leakage current is reduced as compared with the case where there is no light.

  2 and 3 are cross-sectional views showing a first embodiment of a TFT manufacturing method according to the present invention. Hereinafter, description will be given based on this drawing. Note that the same parts as those in FIG.

  The manufacturing method of this example is a method of manufacturing the TFT 100 of FIG. 1, and after each layer of the stacked body 100 a is continuously formed in the same film forming apparatus on the insulating substrate 107, each layer of the stacked body 100 a is manufactured. Are patterned at the same time.

  Here, in the stacked body 100a, each layer is made of silicon or a material containing silicon. Therefore, for example, by using the same film-forming gas (for example, silane) for each layer, it becomes easy to continuously form each layer with the same film-forming apparatus (for example, a plasma CVD apparatus). In addition, by using, for example, the same etching gas (for example, carbon tetrafluoride) for each layer, it becomes easy to perform patterning in a batch with the same etching apparatus (for example, a plasma etching apparatus). Therefore, the manufacturing process can be greatly simplified as compared with the case where each layer is formed separately and patterned separately.

  Next, the manufacturing method of the present embodiment will be described in more detail.

First, as shown in FIGS. 2 [1] and [2], after cleaning the insulating substrate (glass) 107, a base film (SiN) 106 and a lower layer are formed on the insulating substrate 107 using a plasma CVD (Chemical Vapor Deposition) apparatus. A ground film (SiO ₂ ) 105, a light shielding film (a-Si) 113, an insulating film (SiO ₂ ) 112, and an a-Si film 111f are formed in succession. The a-Si film 111f existing on the surface is changed to a semiconductor film (poly-Si) 111 in the crystallization process. For the crystallization step, a solid phase growth method using heat, a laser crystallization method using an excimer laser or a YAG (Yttrium Aluminum Garnet) laser, a crystal growth method using a catalyst, or the like can be used.

Subsequently, as shown in FIG. 2 [3], after the crystallization process is completed, the semiconductor film 111, the insulating film 112, and the light-shielding film 113 are collectively patterned in the photoresist process and the dry etching process, thereby obtaining a stacked body. 100a is obtained. Since these are all silicon-based materials, they can be processed continuously by dry etching using a mixed gas of CF ₄ and oxygen.

  As described above, since the film forming process can be performed by a single film forming apparatus, it is possible to omit the cleaning and transport necessary for forming each layer separately. In addition, since the etching process can also be performed with a single etching apparatus, it is possible to omit the cleaning and transport necessary for etching each layer separately. Therefore, an increase in the number of steps for imparting light resistance to the TFT 100 can be minimized.

Subsequently, as shown in FIG. 3, a source region 111a and a drain region 111e which are a pair of impurity regions connected to the wiring film (Ti / Al) 109 are formed in the semiconductor film 111 by an ion doping method. Further, the channel region 111c located immediately below the gate electrode 110 is cleaned using functional water or acid so as to form a clean interface with the gate insulating film (SiO ₂ ) 104. The pair of LDD regions 111b and 111d between the channel region 111c and the pair of source region 111a and drain region 111e are ion-implanted in a self-aligned manner after forming the gate insulating film 104 and the gate electrode (Cr / n ⁺ ) 110. Form by law.

Subsequently, after an interlayer insulating film (SiO ₂ ) 103 is formed, heat treatment is performed inside the electric furnace to electrically activate the impurities. Subsequently, after forming the contact hole 109a, a wiring film (Ti / Al) 109 is formed and patterned (FIG. 3 [1]). Subsequently, after passivation with a protective film (SiN) 102, a planarizing film 101 is applied to planarize the surface. Further, a pixel film (ITO) 108 is provided through the contact hole 108a to form a pixel electrode (FIG. 3 [2]).

  FIG. 4 is a chart showing optical characteristics of a-Si and poly-Si used in the TFT of FIG. Hereinafter, description will be given based on FIG. 1 and FIG.

  Since the backlight used for the liquid crystal display is a white light source, light having a wavelength of 400 to 700 nm is irradiated onto the TFT 100. In particular, light corresponding to blue and green on the short wavelength side has high energy, and thus it is easy to excite optical carriers in poly-Si. In addition, the absorption coefficient of poly-Si increases on the short wavelength side. In the case of an LED (Light Emitting Diode) backlight, there are many light intensity peaks at wavelengths of about 450 nm and 550 nm. Therefore, it is effective to improve the light shielding performance for wavelengths of 400 nm to 500 nm.

  On the other hand, the light shielding film 113 and the insulating film 112 are desirably thin from the viewpoint of productivity and cost. It is clear that the thicker one can improve the light shielding performance, but if the necessary light shielding performance can be obtained with a thin film as much as possible, the film forming process and the etching process can be shortened.

  According to FIG. 4, in order to halve the amount of light transmitted with respect to light having a wavelength near 450 nm, a film thickness of 10 nm to 20 nm is required for an a-Si thin film, and a film thickness of 50 nm or more is required for a poly-Si thin film. It is.

  Further, when the total thickness of the light shielding film 113, the insulating film 112, and the semiconductor film 113 is increased, the step coverage (step coverage) performance of the gate insulating film 104 is required. This is because if the step coverage is weak, a gate leakage current through the gate insulating film 104 is likely to be generated, which hinders essential transistor operation. Therefore, as shown in FIG. 4, it is desirable to use a-Si for the light-shielding film 113 which can obtain high light-shielding performance even if it is thinner than poly-Si.

  Even a-Si may be crystallized at the same time as the poly-Si film on it is crystallized. Therefore, for example, in the case of using a solid phase growth method, the amorphousness is increased in advance than the a-Si thin film to be poly-Si so that the incubation time until the generation of crystal nuclei is sufficiently long, or It is preferable to take a method of increasing the impurity concentration so that crystallization is inhibited. On the other hand, when utilizing a light crystallization process such as excimer laser annealing, light is prevented from reaching the light shielding film a-Si by using short wavelength light, or the thermal conductivity of the insulating film 112 is increased. It is desirable to keep the a-Si state from being heated, for example, by keeping it low.

  In addition, a polyi-Si film can be used as the light shielding film 113. Since the poly-Si thin film has higher translucency at a shorter wavelength than the a-Si thin film, for example, the thickness is 50 nm and the insulating film 112 is 10 nm. At this time, the light shielding film 113 may be formed by depositing a poly-Si film in advance, or may be polycrystallized at the same time as the semiconductor film 111 is crystallized after depositing a-Si. In the latter case, it is desirable that the insulating film 112 is as thin as possible so as to maintain the insulating property in order to improve heat conduction.

  FIG. 5 is a graph showing the Vg-Id characteristics of the TFT of FIG. 1. FIG. 5 [1] is an n-channel TFT and FIG. 5 [2] is a p-channel TFT. Hereinafter, a description will be given based on FIGS. 1 and 5.

On the insulating substrate 107, the base film (SiN) 106 is 50 nm, the base film (SiO ₂ ) 105 is 100 nm, the a-Si film is 20 nm as the light shielding film 113, the SiO ₂ film is 30 nm as the insulating film 112, and the semiconductor film 111 is A TFT 100 was manufactured by forming a polyi-Si film at 50 nm and other layers. In the TFTs (A2) and (B2) having the light shielding structure of this example, the light leakage current was significantly reduced as compared with the TFTs (A1) and (B1) not employing the light shielding structure as a comparative example. In the liquid crystal display using these TFTs (A2) and (B2) of this example, the amount of vertical crosstalk could be reduced from 3% to 1%.

  FIG. 6 is a cross-sectional view showing a second embodiment of the TFT according to the present invention. Hereinafter, a description will be given based on FIGS. 1 and 6. In FIG. 6, the description of the same parts as those in FIG. 1 is omitted by omitting illustration or attaching the same reference numerals.

  Since the layers 100a of FIG. 1 are patterned at the same time, the step around the periphery of the layered product 100a is larger than when the layers are individually patterned. Therefore, the step coverage of the gate insulating film 104 can be improved by gently tapering or stepping the periphery of the stacked body 100a. Note that the tapered shape or the step shape includes a combination of the taper shape and the step shape.

  The stacked body 100 a including the light shielding film 113, the insulating film 112, and the semiconductor film 111 is patterned at the same time as the semiconductor film 111. These film thicknesses are such that the gate insulating film 104 can be sufficiently covered. The characteristics of the TFT 100, that is, the on-state current and the threshold voltage are determined by the film quality and thickness of the gate insulating film 104 as well as the material and film quality of the semiconductor film 111. Since the gate insulating film 104 is made thinner in accordance with the demand for higher performance of the TFT 100, it is necessary to devise a technique for maintaining step coverage in order to meet the demand, and it is tapered or stepped from the lower layer to the upper layer. As a result, the step coverage can be improved.

  That is, the laminated body 100a 'in FIG. 6 [1] is patterned in a tapered shape so that the cross-sectional shape in the film thickness direction becomes smaller as it goes upward. The stacked body 100a ″ in FIG. 6 [2] is patterned in a stepped manner so that the cross-sectional shape in the film thickness direction becomes smaller as it goes upward. Thereby, even when the gate insulating film 104 is thinned, sufficient step coverage can be realized.

  Further, it is desirable that the thickness of the light shielding film 113 is equal to or smaller than the thickness of the semiconductor film 111, and the sum of the thicknesses of the light shielding film 113 and the insulating film 112 is equal to or smaller than the thickness of the semiconductor film 111. It is desirable to be thinner. In addition, when the total thickness of the light shielding film 113, the insulating film 112, and the semiconductor film 111 is equal to or smaller than the thickness of the gate insulating film 104, sufficient step coverage can be obtained. The same applies to the light shielding films 113 ′ and 113 ″, the insulating films 112 ′ and 112 ″, and the semiconductor films 111 ′ and 111 ″ in FIG. 6.

  Regarding the taper shape, since the taper angle of each layer is determined by the film type and etching conditions of each layer, each layer may be a straight line having the same taper angle, or the angle may be changed for each layer. Further, in this embodiment, the film type and shape (stepped shape, tapered shape) are shown in combination, but the present invention is not limited to this combination, and the total thickness of the light shielding film, insulating film and semiconductor film is the gate. A semiconductor device with higher reliability can be realized by making the thickness equal to or less than the thickness of the insulating film and adding a device with the above shape.

Next, a method for manufacturing the tapered laminate 100a ′ of FIG. It is assumed that the light shielding film 113 ′ is a-Si, the insulating film 112 ′ is SiO ₂ , and the semiconductor film 111 ′ is polyi-Si. Then, a photoresist film having a predetermined shape is formed on the semiconductor film 111 ′, and plasma etching is performed using a mixed gas of carbon tetrafluoride and oxygen. In general, the higher the carbon tetrafluoride ratio, the higher the SiO ₂ etching rate, and the higher the oxygen ratio, the higher the Si etching rate. Therefore, the etching rate of SiO ₂ and Si can be made substantially equal by optimizing the mixing ratio of carbon tetrafluoride and oxygen. When plasma etching is performed under these optimum conditions, a tapered laminate 100a ′ as shown in the figure is obtained by isotropic etching. As described above, in this embodiment, since the light shielding film 113 ′, the insulating film 112 ′, and the semiconductor film 111 ′ are made of silicon or a material containing silicon, the entire three layers can be easily tapered.

Next, a method for manufacturing the stepped laminate 100a ″ of FIG. 6 [2] will be described. It is assumed that the light shielding film 113 ″ is a-Si, the insulating film 112 ″ is SiO ₂ , and the semiconductor film 111 ″ is polyi-Si. Then, a photoresist film having a predetermined shape is formed on the semiconductor film 111 ″, and plasma etching is performed using a mixed gas of carbon tetrafluoride and oxygen. In general, the higher the carbon tetrafluoride ratio, the higher the SiO ₂ etching rate, and the higher the oxygen ratio, the higher the Si etching rate. Further, the photoresist film decreases in thickness as the etching progresses, and its peripheral edge is missing. Therefore, when the conditions for etching Si earlier than SiO ₂ are set first and the recession of the periphery of the photoresist film is used, the semiconductor film 111 ″ recedes and a flat surface of the insulating film 112 ″ appears. Subsequently, when the SiO ₂ is etched faster than Si, the insulating film 112 ″ recedes and the flat surface of the light shielding film 113 ″ appears. As a result, a step-like stacked body 100a ″ as shown in the drawing is obtained. As described above, in this embodiment, since the light shielding film 113 ″, the insulating film 112 ″, and the semiconductor film 111 ″ are made of silicon or a material containing silicon, stepwise etching of the entire three layers is easy. .

  Next, a second embodiment of the TFT manufacturing method according to the present invention will be described with reference to FIGS. In the present embodiment, description will be made using numerical values and the like more specifically than the first embodiment.

First, a silicon oxide film having a thickness of 150 nm is formed as a base film (SiO ₂ ) 105 on an insulating substrate (glass) 107 (FIG. 2 [1]). In this embodiment, the base film (SiN) 106 is omitted.

Then, an a-Si film to be the light shielding film 113 is formed to 30 nm on the base film 105. Further, a silicon oxide film to be the insulating film 112 is formed to 20 nm, and an a-Si film to be the semiconductor film 111 is formed to 30 nm (FIG. 2 [2]). Since each layer is made of silicon or a material containing silicon, these layers can be continuously formed using a gas such as silane as a raw material using, for example, a plasma CVD apparatus. At this time, for the purpose of controlling the threshold voltage Vth, impurities such as boron and phosphorus of a very small amount (for example, a concentration of about 1 × 10 ¹² cm ⁻² ) are mixed at the time of film formation, The impurity is introduced by an ion implantation method. Furthermore, the a-Si film is irradiated with an excimer laser or the like to form a poly-Si film having excellent characteristics. The poly-Si film functioning as the semiconductor film 111 is desirably thin because the generation of optical carriers is suppressed when the volume is small.

Note that silicide may be used as the light shielding film 113 as described above. At this time, for example, WSi ₂ can be continuously formed together with other films by a plasma CVD apparatus by using a mixed gas of tungsten hexafluoride and silane.

Subsequently, the poly-Si film and the underlying silicon oxide film and a-Si film are patterned into a desired shape by lithography and dry etching (FIG. 2 [3]). At this time, the poly-Si film is patterned using CF ₄ / O ₂ gas at a flow rate of 180 sccm / 100 sccm, a gas pressure of 30 Pa, and a discharge power of 500 W, and then the gas type and flow rate CF ₄ / O ₂ = 120 sccm / 30 sccm, gas The lower layer is etched at a pressure of 10 Pa, a discharge power of 2000 W, or a gas type and flow rate CHF ₃ / CO = 120 sccm / 30 sccm, a gas pressure of 2 Pa, and a discharge power of 2000 W.

  As the gate insulating film 104, a silicon oxide film is formed by a plasma CVD method. At this time, the heat treatment is performed at 600 ° C. or lower, which is lower than the temperature at which the insulating substrate (glass) 107 is greatly deformed. At this time, a mixed gas containing an organic silane having an ethoxy group and at least an oxygen gas such as tetraethoxysilane (hereinafter referred to as “TEOS”) is used as a material gas.

When the gate insulating film 104 is formed, decomposition of organosilane such as TEOS can be promoted by controlling the RF power density of the plasma CVD apparatus. Furthermore, by controlling the flow ratio of the organic silane and oxygen gas during the formation, an intermediate product containing oxygen necessary for the reaction with the decomposed organic silane can be sufficiently supplied. Therefore, the RF power density at the time of formation is 0.690 to 1.553 W / cm ² , and the ratio (F0 / F1) between the flow rate of oxygen gas (F0) and the flow rate of organic silane (F1) at the time of formation is 50 to 50 It is preferable to set these to 500 and control them simultaneously. By controlling in the range of these RF power density and gas flow ratio, organosilane such as TEOS can be sufficiently decomposed, so the content of CO ₂ and H ₂ O in the formed silicon oxide film is controlled. Easy to do.

  In addition, when forming the gate insulating film 104, it is preferable to form the entire gate insulating film 104 under the same formation conditions. When the formation conditions are not the same and the gate insulating film 104 having a uniform film quality cannot be obtained when divided into two or more stages, there may be a case where a TFT with small fluctuations in electrical characteristics cannot be obtained. In addition, there is a high possibility that the variation between elements becomes large.

Subsequently, a gate electrode film to be a gate electrode (Cr / n ⁺ ) 110 is formed on the gate insulating film 104. As the gate electrode film, a metal film formed by a sputtering method, a silicon film mixed with impurities formed by a CVD method or the like, or a stacked film thereof is used. Impurities here are boron and phosphorus, which are mixed at different concentrations and types in order to control the threshold. Then, after forming a photoresist pattern on the gate electrode film, the gate electrode 110 is formed using dry etching, wet etching, or both.

  Subsequently, in order to form the source region 111a and the drain region 111e, a photoresist pattern is formed thereon, and then, using this photoresist pattern as a mask, a high-concentration impurity is ion-doped or ion-implanted. To introduce. As this impurity, boron is used when forming a p-channel TFT, and phosphorus is used when forming an n-channel TFT. Thereafter, the photoresist pattern is peeled off.

  Further, in order to form the LDD regions 111b and 111d, impurities are introduced so that the concentration is lower than that of the source region 111a and the drain region 111 using the gate electrode 110 as a mask. As this impurity, boron is used when forming a p-channel TFT, and phosphorus is used when forming an n-channel TFT. Note that in this embodiment, the source region 111a and the drain region 111e are formed after the gate electrode 110 is formed, but the effect is the same even when the gate electrode 110 is formed.

  Subsequently, a silicon oxide film, a silicon nitride film, or a laminated film thereof is formed as the interlayer insulating film 103 by using a plasma CVD method or the like. Subsequently, heat treatment for activating the impurities is performed in a furnace at a relatively high temperature (for example, 300 ° C. or higher). For the activation of the impurities, an excimer laser irradiation method may be used.

  Thereafter, contact holes 109,... Are formed on the source region 111a, the drain region 111e, and the gate electrode 110 by using lithography, dry etching, wet etching, or both.

  Subsequently, a metal film for obtaining contacts with the source region 111a, the drain region 111e, and the gate electrode 110 is formed by a sputtering method. Further, the wiring film (Ti / Al) 109 is formed by patterning using lithography and dry etching or wet etching or both (FIG. 3 [1]).

  Thereby, the basic configuration of the TFT 100 is completed. In some cases, hydrogen plasma treatment is performed to terminate dangling bonds existing at the interface between the poly-Si film or the poly-Si film and the gate insulating film with hydrogen. The hydrogen plasma treatment may be performed at the final stage, or may be performed after the heat treatment for activating the impurities.

  Thereafter, another electrode film, a passivation film, an interlayer insulating film, a planarizing film, a capacitor insulating film, and the like are appropriately formed thereon depending on the use of the TFT 100 (FIG. 3 [2]). In addition, the active matrix substrate according to the present invention can be formed by performing the above-described steps so that the TFT according to the present invention is disposed at a desired position.

  Next, a third embodiment of the TFT according to the present invention will be described with reference to FIG.

  In the present invention, since the step covered by the gate insulating film 104 is larger than the case where only the semiconductor film 111 is covered, the gate insulating film 104 is required to have high insulating performance.

When an organic silane such as TEOS is used when forming the silicon oxide film as the gate insulating film 104, the silicon oxide film contains an intermediate product including carbon remaining due to insufficient decomposition of the organic silane. Further, when a silicon oxide film is formed by a chemical vapor deposition method such as a plasma CVD method or a low pressure CVD method, a relatively large amount of H ₂ O is contained in the silicon oxide film. If many of these substances are present in the gate insulating film 104 of the TFT 100, the operation reliability of the TFT 100 is deteriorated. Thus, by applying the gate insulating film 104 containing CO ₂ to the TFT 100, the operation reliability of the TFT 100 can be improved.

At present, this cause is not fully understood, but is estimated as follows. Intermediate products containing H ₂ O and carbon remaining due to insufficient decomposition of organosilane are easily taken into the pores (pores) in the silicon oxide film. When CO ₂ is adsorbed on the pores in the silicon oxide film, the content of H ₂ O and intermediate products in the silicon oxide film can be reduced.

Further, since CO ₂ is a stable compound, when a silicon oxide film containing CO ₂ is used for the gate insulating film 104, it is not easily influenced by hot carriers generated during the operation of the TFT 100, and thus the electrical characteristics of the TFT 100 are obtained. It is possible to suppress fluctuations in the above. In particular, since carriers (charges) injected into the gate insulating film 104 during the operation of the TFT 100 are injected into the vicinity of the poly-Si film, the characteristics of the gate insulating film 104 located in the vicinity of the poly-Si film are large. Affect. Therefore, it is desirable that CO _{2 be present} in the vicinity of the poly-Si film, that is, in a region about 10% of the thickness of the gate insulating film 104 and in contact with the poly-Si film.

In the infrared absorption spectrum of the silicon oxide film, a large peak attributed to Si—O is observed near the wave number of 1060 cm ⁻¹ . When the silicon oxide film contains CO ₂ , a peak is observed in the infrared absorption spectrum near a wave number of 2340 cm ⁻¹ . When the peak area intensity near the wave number of 2340 cm ⁻¹ is 8 × 10 ⁻⁴ times or more than the peak area intensity near the wave number of 1060 cm ^{−1 in the} infrared absorption spectrum, a voltage is applied to the gate electrode 110 of the TFT 100. The silicon oxide film contains CO ₂ to a degree that suppresses fluctuations in electrical characteristics when applied for a long time.

Furthermore, if the H ₂ O contained in the silicon oxide film in the vicinity of the poly-Si film as the gate insulating film 104 is 9 × 10 ²⁰ pieces / cc or less, the electrical characteristics of the TFT 100 when a voltage is applied for a long time. In addition to suppressing variations in the above, variation in electrical characteristics of the TFT 100 due to H ₂ O, for example, variation in threshold voltage Vth between substrates, is also suppressed.

Since the TFT 100 using the above-described silicon oxide film containing CO ₂ as the gate insulating film 104 has high operation reliability, it exhibits high step coverage performance. Therefore, the active matrix substrate on which the TFT 100 is mounted has high operation reliability.

  FIG. 7 is a perspective view showing a first embodiment of an active matrix substrate according to the present invention. Hereinafter, description will be given based on this drawing.

  The active matrix substrate 21 of the present embodiment is formed by providing a large number of TFTs 100 (partially indicated by black dots in the drawing) vertically and horizontally on an insulating substrate 107. The TFT 100 may be any of the TFTs disclosed in the above embodiments. By using the TFT 100, an active matrix substrate 21 that is inexpensive and excellent in light resistance can be obtained.

  This will be described in more detail. In this embodiment, the active matrix substrate 21 is applied to the liquid crystal display panel 31. In the disassembled liquid crystal display panel 31, an active matrix substrate 21 (also referred to as a TFT substrate) and a counter substrate 26 are provided so as to be separated from each other and in parallel. A liquid crystal layer 25 is provided between the active matrix substrate 21 and the counter substrate 26. In the active matrix substrate 21, the pixel circuit 22, the data circuit 23, and the scanning circuit 24 are formed on the side of the insulating substrate 107 facing the counter substrate 26.

  According to the present embodiment, since the liquid crystal display panel 31 includes the TFT 100 with reduced light leakage current, the liquid crystal display panel 31 can be stably operated even when a high luminance backlight is used. For this reason, the display performance of the liquid crystal display panel 31 is enhanced.

  FIG. 8 is a perspective view showing a first embodiment of the electronic apparatus according to the present invention. Hereinafter, description will be given based on this drawing.

  A cellular phone 33 as an electronic apparatus of the present embodiment includes the active matrix substrate 21 of FIG. By using the active matrix substrate 21 of FIG. 7, it is possible to obtain a mobile phone 33 that is inexpensive and excellent in light resistance.

  This will be described in more detail. The mobile phone 33 is provided with a housing 32, and a liquid crystal display panel 31 is mounted on the housing 32 as a display unit. The liquid crystal display panel 31 uses an active matrix substrate including any of the TFTs of the above-described embodiments.

  According to the present embodiment, since the light leakage current of the TFT included in the liquid crystal display panel 31 is suppressed, the liquid crystal display can be used even when a high-brightness backlight capable of using the mobile phone 33 under external light is used. The phenomenon that the operation of the panel 31 becomes unstable can be suppressed. For this reason, the user can enjoy the high display quality of the mobile phone 33.

  Needless to say, the present invention is not limited to the above embodiments. For example, the electronic apparatus according to the present invention is not limited to a mobile phone, and may be, for example, a personal computer, a PDA (Personal Digital Assistance), a digital video, or the like.

[Appendix 1] A light shielding film formed on an insulating substrate, an insulating film formed on the light shielding film, a semiconductor film formed on the insulating film, and a gate insulating film formed on the semiconductor film A thin film transistor in which each layer of a multilayer structure including the light shielding film, the insulating film, and the semiconductor film is simultaneously patterned,
Each layer of the laminate is made of silicon or a material containing silicon,
A thin film transistor.

[Appendix 2] The laminate has side surfaces that are symmetric in the cross-sectional shape in the film thickness direction.
The thin film transistor according to appendix 1, wherein:

[Appendix 3] The laminate has side surfaces patterned in a tapered shape so that the cross-sectional shape in the film thickness direction becomes smaller as it goes upward.
The thin film transistor according to appendix 1 or 2, wherein:

[Appendix 4] The laminate has side surfaces patterned stepwise so that the cross-sectional shape in the film thickness direction becomes smaller as it goes upward.
The thin film transistor according to appendix 1 or 2, wherein:

[Supplementary Note 5] The laminate has side surfaces that are patterned in a tapered and stepped manner so that the cross-sectional shape in the film thickness direction becomes smaller as it goes upward.
The thin film transistor according to appendix 1 or 2, wherein:

[Appendix 6] The sum of the thicknesses of the respective layers is equal to or less than the thickness of the gate insulating film.
The thin film transistor according to any one of appendices 1 to 5, characterized in that:

[Appendix 7] The material containing silicon is a material mainly containing silicon.
The thin film transistor according to any one of appendices 1 to 6, wherein:

[Appendix 8] The semiconductor film and the light shielding film are made of silicon, and the insulating film is made of silicon oxide.
The thin film transistor according to appendix 7, wherein:

[Appendix 9] The semiconductor film is made of polycrystalline silicon, and the light shielding film is made of amorphous silicon.
The thin film transistor according to appendix 8, wherein:

[Appendix 10] A method of manufacturing the thin film transistor according to any one of appendices 1 to 9,
After each layer of the laminate is continuously formed in the same film forming apparatus on the insulating substrate, each layer of the laminate is simultaneously patterned.
A method for manufacturing a thin film transistor.

[Appendix 11] In an active matrix substrate in which a number of thin film transistors are provided vertically and horizontally on an insulating substrate,
The thin film transistor is the thin film transistor according to any one of appendices 1 to 9,
An active matrix substrate characterized by that.

[Appendix 12] In an electronic device comprising an active matrix substrate,
The active matrix substrate is the active matrix substrate according to appendix 11,
An electronic device characterized by that.

100 TFT
100a Laminated body 104 Gate insulating film 107 Insulating substrate 111, 111 ′, 111 ″ Semiconductor film 112, 112 ′, 112 ″ Insulating film 113, 113 ′, 113 ″ Light shielding film 21 Active matrix substrate 33 Mobile phone

Claims (4)

A thin film transistor having a light shielding film formed on an insulating substrate, an insulating film formed on the light shielding film, a semiconductor film formed on the insulating film, and a gate insulating film formed on the semiconductor film A method of manufacturing
Using a material containing silicon or silicon for the light shielding film, the insulating film, and the semiconductor film,
After continuously forming the light shielding film, the insulating film and the semiconductor film on the insulating substrate in the same CVD apparatus,
Simultaneously patterning the light-shielding film, the insulating film, and the semiconductor film in the same etching apparatus;
A method for manufacturing a thin film transistor. In the manufacturing method of the thin-film transistor of Claim 1,
The CVD apparatus is a plasma CVD apparatus, and the etching apparatus is a plasma etching apparatus.
A method for manufacturing a thin film transistor. In the manufacturing method of the thin-film transistor of Claim 1 or 2,
The semiconductor film and the light shielding film are made of silicon, and the insulating film is made of silicon oxide.
A method for manufacturing a thin film transistor. In the manufacturing method of the thin-film transistor of Claim 1, 2, or 3,
The semiconductor film is made of polycrystalline silicon, and the light shielding film is made of amorphous silicon.
A method for manufacturing a thin film transistor.

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