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CN110634847A - 半导体器件和方法 - Google Patents

半导体器件和方法 Download PDF

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Publication number
CN110634847A
CN110634847A CN201811544219.2A CN201811544219A CN110634847A CN 110634847 A CN110634847 A CN 110634847A CN 201811544219 A CN201811544219 A CN 201811544219A CN 110634847 A CN110634847 A CN 110634847A
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CN
China
Prior art keywords
layer
integrated circuit
conductive
circuit device
photosensitive adhesive
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CN201811544219.2A
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CN110634847B (zh
Inventor
余振华
余国宠
余俊辉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN110634847A publication Critical patent/CN110634847A/zh
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Abstract

在实施例中，一种器件包括：第一器件，包括：具有第一连接件的集成电路器件；第一光敏粘合层，位于集成电路器件上；以及第一导电层，位于第一连接件上，第一光敏粘合层围绕第一导电层；第二器件，包括：具有第二连接件的内插器；第二光敏粘合层，位于内插器上，第二光敏粘合层物理连接至第一光敏粘合层；以及第二导电层，位于第二连接件上，第二光敏粘合层围绕第二导电层；以及导电连接件，接合第一导电层和第二导电层，通过气隙围绕导电连接件。本发明实施例涉及半导体器件和方法。

Description

半导体器件和方法
技术领域
本发明实施例涉及半导体器件和方法。
背景技术
随着集成电路(IC)的发展，由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断提高，半导体产业已经经历了快速增长。在大多数情况下，集成密度的这种改进来自最小部件尺寸的不断减小，这允许更多的组件集成到给定区域内。
这些集成改进本质上是二维的(2D)，因为集成组件占据的区域基本上是半导体晶圆的表面上。集成电路的密度的增加和面积的相应减小通常超过了将集成电路芯片直接接合到衬底上的能力。内插器已经用于将来自芯片的球接触区重新分配到内插器的更大区域。此外，内插器已经允许包括多个芯片的三维(3D)封装件。也已经开发其他封装件来结合3D的各个方面。
发明内容
根据本发明的一些实施例，提供了一种半导体器件，包括：第一器件，包括：集成电路器件，具有第一连接件；第一光敏粘合层，位于所述集成电路器件上；以及第一导电层，位于所述第一连接件上，所述第一光敏粘合层围绕所述第一导电层；第二器件，包括：内插器，具有第二连接件；第二光敏粘合层，位于所述内插器上，所述第二光敏粘合层物理连接至所述第一光敏粘合层；以及第二导电层，位于所述第二连接件上，所述第二光敏粘合层围绕所述第二导电层；以及导电连接件，接合所述第一导电层和所述第二导电层，通过气隙围绕所述导电连接件。
根据本发明的另一些实施例，还提供了一种形成半导体器件的方法，包括：在第一光敏粘合层中形成第一开口，所述第一光敏粘合层与第一集成电路器件的第一侧相邻；在所述第一开口中镀第一可回流层；在第二光敏粘合层中形成第二开口，所述第二光敏粘合层与第二集成电路器件的第一侧相邻；在所述第二开口中镀第二可回流层；将所述第一光敏粘合层和所述第二光敏粘合层压在一起，从而物理连接所述第一集成电路器件和所述第二集成电路器件；以及回流所述第一可回流层和所述第二可回流层，从而形成电连接所述第一集成电路器件和所述第二集成电路器件的导电连接件。
根据本发明的另一些实施例，还提供了一种形成半导体器件的方法，包括：用第一模塑料密封多个第一集成电路器件；在所述第一集成电路器件上方形成第一光敏粘合层；在所述第一光敏粘合层中图案化第一开口；在所述第一开口中镀第一导电层；在所述第一导电层上镀第一可回流层，所述第一导电层和所述第一可回流层的组合厚度小于所述第一光敏粘合层的第一厚度，所述第一导电层和所述第一可回流层电连接至所述第一集成电路器件；将第二集成电路器件压至所述第一光敏粘合层，以物理连接所述第一集成电路器件和所述第二集成电路器件；以及回流所述第一可回流层以形成电连接所述第一集成电路器件和所述第二集成电路器件的导电连接件。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1A至图2B是根据一些实施例的在集成电路器件的处理期间的中间步骤的各个图。
图3A至图4B是根据一些实施例的晶圆的处理期间的中间步骤的各个图。
图5A至图18是根据一些实施例的在形成器件封装件的工艺期间的中间步骤的各个图。
图19是根据一些实施例的器件封装件的图。
图20示出根据一些其他实施例的器件封装件。
图21示出根据其他实施例的器件封装件。
图22至图33是根据一些实施例的在用于形成器件封装件的工艺期间的中间步骤的各个图。
图34示出根据一些其他实施例的器件封装件。
图35示出根据又一些其他实施例的器件封装件。
图36示出根据又一些其他实施例的器件封装件。
图37至图46是根据一些实施例的在用于形成器件封装件的工艺期间的中间步骤的各个图。
图47至图57是根据一些实施例的在用于形成器件封装件的工艺期间的中间步骤的各个图。
图58A至图58F示出根据另一实施例的用于形成导电连接件的工艺。
图59A至图59K示出根据另一实施例的用于形成导电连接件的工艺。
图60A至图60F示出根据另一实施例的用于形成导电连接件的工艺。
图61A和图61B是根据一些其他实施例的器件封装件的各个图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
根据一些实施例，形成导电连接件。在管芯和晶圆上形成光敏粘合膜。在光敏粘合膜中形成开口，从而暴露管芯和晶圆的连接件。在开口中镀导电层和可回流层。值得注意的是，每个开口中的导电层和可回流层的组合厚度小于光敏粘合膜的厚度。通过光敏粘合膜将管芯和晶圆彼此物理连接，并且然后通过回流可回流层将管芯和晶圆彼此电连接以形成导电连接件。因为开口底部填充有可回流材料，所以在所得到的导电连接件周围形成气隙。气隙的形成可以在导电连接件周围提供缓冲，避免了在相邻的导电连接件之间的间距减小时形成短路的风险。
图1A至图2B是根据一些实施例的在集成电路器件50的处理期间的中间步骤的各个图。图1A至图2B是截面图，其中，以“A”标记结尾的图示出整体图，以及以“B”标记结尾的图示出来自相应“A”图的区域R1的详细图。
集成电路器件50可以是逻辑管芯(例如，中央处理单元(CPU)、图形处理单元(GPU)、芯片上系统(SoC)、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等，或它们的组合。集成电路器件50可以形成在晶圆中，其中，晶圆可以包括在后续步骤中分割以形成多个集成电路器件50的不同器件区。集成电路器件50包括衬底52和连接件54。
衬底52可以包括块状半导体衬底、绝缘体上半导体(SOI)衬底、多层半导体衬底等。衬底52的半导体材料可以是硅、锗、包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体；或它们的组合。还可以使用诸如多层衬底或梯度衬底的其他衬底。衬底52可以是掺杂的或未掺杂的。可以在衬底52的有源表面(例如，面向上的表面)中和/或上形成诸如晶体管、电容器、电阻器、二极管等的器件。
在衬底52的有源表面上形成具有介电层和相应的金属化图案的互连结构。介电层可以是金属间介电(IMD)层。例如，可以通过本领域内已知的任何合适的方法(诸如，旋涂、化学汽相沉积(CVD)、等离子体增强CVD(PECVD)、高密度等离子体化学汽相沉积(HDP-CVD)等)由低K介电材料(诸如，未掺杂的硅酸盐玻璃、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等)形成IMD层。介电层中的金属化图案可以例如通过使用通孔和/或迹线在器件之间路由电信号，并且还可以包括诸如电容器、电阻器、电感器等的各个电子器件。可以互连各个器件和金属化图案以实施一个或多个功能。功能可以包括存储器结构、处理结构、传感器、放大器、功率分配、输入/输出电路等。额外地，诸如导电柱或接触焊盘的连接件54形成在互连结构中和/或上，以提供至电路和器件的外部电连接。本领域的普通技术人员将会理解，提供上述实例是为了说明的目的。可以适当使用其他电路以用于给定应用。
在图1A和图1B中，在衬底52的有源表面上形成光敏粘合膜56。光敏粘合膜56可以由诸如苯并环丁烯(BCB)、环氧树脂膜(SU-8)、ShinEtsu SINRTM、聚酰亚胺等的有机光敏聚合物层(PSPL)形成，并且可以通过旋涂等形成。光敏粘合膜56也可以称为粘合层。在形成之后，可以将光敏粘合膜56曝光以用于图案化。光敏粘合膜56的图案对应于连接件54。图案化形成穿过光敏粘合膜56的开口58的图案，从而暴露连接件54的部分。每个开口58的宽度W1可以小于连接件54的宽度，诸如宽度W1为从约1μm至约40μm。宽度W1也可以大于或等于连接件54的宽度。在形成和图案化光敏粘合膜56之后，通过例如退火工艺使其固化，其中，该退火工艺可以在低于约200的℃温度下在烘箱中进行。形成的光敏粘合膜56具有从约1μm至约10μm的厚度T1。开口58的深度等于厚度T1。
在图2A和图2B中，在位于连接件54上的开口58中形成导电层60。导电层60由诸如镍、铜、金等或它们的组合的导电材料形成，并且使用连接件54代替晶种层通过诸如化学镀的镀工艺来形成。然后在位于开口58中的导电层60上形成可回流层62。可回流层62由诸如焊料、锡等或它们的组合的可回流材料形成，并且使用导电层60代替晶种层通过镀工艺来形成。
导电层60和可回流层62具有从约1μm至约10μm的组合厚度T2。厚度T2小于厚度T1。根据宽度W1计算可回流层62的厚度，从而使得形成足够的可回流材料以用于后续形成的导电连接件。这样，光敏粘合膜56的顶面在可回流层62的顶面之上延伸。形成间隙G1，其中，间隙G1的深度等于厚度T1和T2之间的差。
图3A至图4B是根据一些实施例的在晶圆70的处理期间的中间步骤的各个图。图3A至图4B是截面图，其中，以“A”标记结尾的图示出整体图，以及以“B”标记结尾的图示出来自相应“A”图的区域R2的详细图。
晶圆70包括多个器件区100A和100B，其中，将附接集成电路器件50以形成多个器件。形成在晶圆70中的器件可以是内插器、集成电路管芯等。晶圆70包括衬底72、贯通孔74和连接件76。
衬底72可以是块状半导体衬底、SOI衬底、多层半导体衬底等。衬底72的半导体材料可以是硅、锗、包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体；或它们的组合。还可以使用诸如多层衬底或梯度衬底的其他衬底。衬底72可以是掺杂的或未掺杂的。在其中内插器形成在晶圆70中的实施例中，衬底72通常不包括位于其中的有源器件，但是内插器可以包括形成在衬底72的正面(例如，面向上的表面)中和/或上的无源器件。在其中集成电路管芯形成在晶圆70中的实施例中，可以在衬底72的正面中和/或上形成诸如晶体管、电容器、电阻器、二极管等的器件。
贯通孔74形成为从衬底72的正面延伸到衬底72中。当衬底72是硅衬底时，贯通孔74有时也称为贯衬底通孔或贯硅通孔(TSV)。可以通过例如蚀刻、铣削、激光技术、它们的组合等在衬底72中形成凹槽来形成贯通孔74。可以诸如通过使用氧化技术在凹槽中形成薄的介电材料。可以诸如通过CVD、ALD、PVD、热氧化、它们的组合等在衬底72的正侧上方且在开口中共形地沉积薄的阻挡层74a。阻挡层74a可以由诸如氮化钛、氮氧化钛、氮化钽、氮氧化钽、氮化钨、它们的组合等的氧化物、氮化物或氮氧化物形成。可以在阻挡层74a上方且在开口中沉积导电材料74b。可以通过电化学镀工艺、CVD、ALD、PVD、它们的组合等形成导电材料74b。导电材料74b的实例是铜、钨、铝、银、金、它们的组合等。通过例如CMP从衬底72的正侧去除多余的导电材料74b和阻挡层74a。贯通孔74共同地包括阻挡层74a和导电材料74b，其中，阻挡层74a位于导电材料74b和衬底72之间。
互连结构形成在衬底72的正面上方，并且用于将集成电路器件(如果有的话)和/或贯通孔74电连接在一起和/或电连接至外部器件。互连结构可以包括介电层和位于介电层中的相应的金属化图案。金属化图案可以包括通孔和/或迹线，以将任何器件和/或贯通孔74互连在一起和/或互连至外部器件。介电层可以由氧化硅、氮化硅、碳化硅、氮氧化硅、诸如PSG、BPSG、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等的低K介电材料形成。可以通过诸如旋涂、CVD、PECVD、HDP-CVD等的本领域已知的任何合适的方法沉积介电层。例如，通过使用光刻技术在介电层上沉积并图案化光刻胶材料以暴露将变为金属化图案的介电层的部分，可以在每个介电层中形成金属化图案。诸如各向异性干蚀刻工艺的蚀刻工艺可用于在介电层中创建与介电层的暴露部分相对应的凹槽和/或开口。凹槽和/或开口可以内衬有扩散阻挡层并填充有导电材料。扩散阻挡层可以由通过ALD等沉积的一层或多层TaN、Ta、TiN、Ti、CoW等形成，以及导电材料可以由铜、铝、钨、银、它们的组合等形成，并且可以通过CVD、PVD等沉积。诸如通过使用CMP，可以去除介电层上的任何多余的扩散阻挡层和/或导电材料。额外地，诸如导电柱或接触焊盘的连接件76形成在互连结构中和/或上，以提供至贯通孔74和互连结构的金属化图案的外部电连接。
在图3A和图3B中，在衬底72的正面上形成光敏粘合膜78。光敏粘合膜78可以由与光敏粘合膜56类似的材料形成，并且可以通过与用于形成光敏粘合膜56的方法类似的方法形成。在形成之后，可以将光敏粘合膜78曝光以用于图案化。光敏粘合膜78的图案对应于连接件76。图案化形成穿过光敏粘合膜78的开口80的图案，从而暴露连接件76的部分。每个开口80的宽度W2可以小于连接件76的宽度，诸如宽度W2为从约1μm至约40μm。宽度W2也可以大于或等于连接件76的宽度。形成的光敏粘合膜78具有从约1μm至约5μm的厚度T3。开口80的深度等于厚度T3。在一些实施例中，光敏粘合膜78在形成后不立即固化，而是在实施后续的处理步骤之后进行固化(参见例如图6A和图6B)。
在图4A和图4B中，在位于连接件76上的开口80中形成导电层82。导电层82可以由与导电层60的材料类似的材料形成，并且可以通过与用于形成导电层60的方法类似的方法形成。然后在位于开口80中的导电层82上形成可回流层84。可回流层84可以由与可回流层62的材料类似的材料形成，并且可以通过与用于形成可回流层62的方法类似的方法形成。
导电层82和可回流层84具有从约1μm至约5μm的组合厚度T4。厚度T4小于厚度T3。这样，光敏粘合膜78的顶面在可回流层84的顶面之上延伸。形成间隙G2，其中，间隙G2的深度等于厚度T3和T4之间的差。
根据一些实施例，通过将集成电路器件50接合至晶圆70的正侧来形成集成电路器件封装件。在接合之前，可以根据上述工艺处理集成电路器件50和晶圆70。可以使用这种器件形成各种集成电路器件封装件。
图5A至图18是根据一些实施例的在用于形成器件封装件200的工艺期间的中间步骤的各个图。在图5A至图11中，通过将集成电路器件50接合至晶圆70的正侧来形成中间封装件100。分割中间封装件100。在图12至图18中，实施进一步处理以形成器件封装件200。在实施例中，器件封装件200是晶圆上芯片(CoW)封装件，但是应当理解，该实施例可以应用于其他3DIC封装件。图19是根据一些实施例的器件封装件300的图。图5A至图19是截面图，其中，以“A”标记结尾的图示出整体图，以及以“B”标记结尾的图示出来自相应“A”图的区域R3的详细图。特别地，区域R3示出导电连接件102(图6B中示出)的形成，其中，该导电连接件102将集成电路器件50的连接件54连接至晶圆70的连接件76。
在图5A和图5B中，多个集成电路器件50附接至晶圆70。集成电路器件50位于器件区100A和100B中，其中，将在后续步骤中分割器件区100A和100B以形成中间封装件100。可以使用例如拾取和放置工具将集成电路器件50附接至晶圆70。
集成电路器件50通过面至面接合附接至晶圆70。将集成电路器件50压在晶圆70上，从而使得光敏粘合膜56和78彼此粘附。在光敏粘合膜78形成后不立即固化的实施例中，光敏粘合膜56和78在粘合时共享固化的-未固化的接合界面，其中，光敏粘合膜56是固化的并且光敏粘合膜78是未固化的。未固化的光敏粘合膜78可以在放置期间更好地共形于固化的光敏粘合膜56的形状。当将光敏粘合膜56和78压在一起时，它们混合并形成聚合物键，从而成为一个连续的PSPL。与诸如混合接合和熔融接合的其他接合技术相比，使用光敏粘合膜56和78允许集成电路器件50以较少的退火和清洁工艺粘附至晶圆70，从而降低了制造成本。
在集成电路器件50附接至晶圆70之后，在位于可回流层62和84之间的区域中形成气隙104。因此，集成电路器件50物理地连接至晶圆70，但是可以不电连接。气隙104包括由间隙G1和G2界定的区域(分别在图2B和图4B中示出)。气隙104均具有两个宽度：一个由开口58的宽度W1限定，以及一个由开口80的宽度W2限定。气隙104也均具有等于间隙G1和G2的高度之和的高度H1，其也等于等式1。
H1＝(T1+T3)-(T2+T4) (1)
在图6A和图6B中，实施回流工艺，从而将可回流层62和84重新成形为导电连接件102。导电连接件102包括可回流层62和84的材料，并且可以在导电连接件102与导电层60和82的界面处形成金属间化合物(IMC)。在回流工艺期间，可回流层62和84的材料可能由于回流材料的表面张力而改变形状。可回流层62和84的新形状合并，从而使得可回流层62和84接触并形成导电连接件102。保留对应于间隙G2的气隙106。气隙106形成在导电连接件102的上部周围，并且在气隙106和连接件76之间设置导电连接件102的下部。形成气隙106在相邻的导电连接件102之间形成缓冲空间，从而允许导电连接件102以更精细的间距形成。在光敏粘合膜78在形成后不立即固化的实施例中，来自回流工艺的热量也可使光敏粘合膜78固化。
在图7中，在各个组件上形成密封剂108。密封剂108可以是模塑料、环氧树脂等，并且可以通过压缩模制、传递模制等来施加。可以在晶圆70上方形成密封剂108，从而使得掩埋或覆盖集成电路器件50。也在光敏粘合膜78上形成密封剂108。然后固化密封剂108。在一些实施例中，削薄密封剂108，从而使得密封剂108和集成电路器件50的顶面齐平。
在图8中，削薄衬底72以暴露贯通孔74，从而使得贯通孔74从衬底72的背侧突出。可以在两步削薄工艺中完成贯通孔74的暴露。首先，可以实施研磨工艺直到暴露贯通孔74。研磨工艺可以是例如CMP或其他可接受的去除工艺。在研磨工艺之后，衬底72的背侧和贯通孔74齐平。其次，可以实施凹进工艺以凹进贯通孔74周围的衬底72。凹进工艺可以是例如合适的回蚀刻工艺。在削薄期间，也可以去除导电材料74b的一些部分。
在图9中，在贯通孔74的突出部分上形成导电柱110。导电柱110可以通过例如合适的光刻和镀工艺形成，并且可以由铜、铝、钨、银、它们的组合等形成。然后，在衬底72的背侧上，围绕贯通孔74的突出部分和导电柱110形成绝缘层112。在一些实施例中，绝缘层112由诸如氮化硅、氧化硅、氮氧化硅等的含硅绝缘体形成，并且可以通过诸如旋涂、CVD、PECVD、HDP-CVD等的合适的沉积方法形成。在沉积之后，可以实施诸如CMP的平坦化工艺以去除多余的介电材料，从而使得绝缘层112和导电柱110的表面齐平。
在一些实施例中，绝缘层112包括多个层。可以在衬底72的背侧上，围绕贯通孔74的突出部分形成第一绝缘层。利用暴露贯通孔74的开口图案化第一绝缘层。在第一绝缘层上且在开口中形成晶种层，以及在晶种层上形成光刻胶。利用与导电柱110的图案相对应的开口图案化光刻胶，并且实施镀工艺，从而在开口中形成导电柱110。去除光刻胶和晶种层的暴露部分。然后在第一绝缘层上和导电柱110周围形成第二绝缘层。
在图10中，沿着划线区114在相邻的器件区100A和100B之间分割晶圆70，以形成中间封装件100。可以通过锯切、切割等来实施分割。
图11示出分割之后的中间封装件100。在分割工艺期间，形成内插器116，其中，内插器116包括晶圆70和绝缘层112的分割部分。在一些实施例中，内插器116没有有源器件。在其他实施例中，内插器116包括有源器件。每个中间封装件100包括内插器116。在内插器116上形成光敏粘合膜78的分割部分。作为分割工艺的结果，内插器116、密封剂108和光敏粘合膜78的边缘具有共同的边界。换言之，内插器116的外侧壁具有与密封剂108和光敏粘合膜78的外侧壁相同的宽度。
在图12中，分割的中间封装件100粘附至载体衬底118。载体衬底118可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底118可以是晶圆，从而使得可以在载体衬底118上同时形成多个封装件。载体衬底118包括多个器件区200A和200B，其中，通过粘合剂120附接中间封装件100。
粘合剂120位于中间封装件100的背侧，并且将中间封装件100粘附至载体衬底118。粘合剂120可以是任何合适的粘合剂、环氧树脂、管芯附接膜(DAF)等。粘合剂120可以施加至中间封装件100的背侧，诸如施加至相应的密封剂108的背侧或者可以施加在载体衬底118的表面上方。可以使用例如拾取和放置工具通过粘合剂120将中间封装件100粘附至载体衬底118。
在图13中，在各个组件上形成密封剂122。密封剂122可以是模塑料、环氧树脂等，并且可以通过压缩模制、传递模制等来施加。可以在中间封装件100上方形成密封剂122，从而使得掩埋或覆盖导电柱110。在固化之后，密封剂122可以经历研磨工艺以暴露导电柱110。研磨工艺还可以研磨绝缘层112。在研磨工艺之后，导电柱110、绝缘层112和密封剂122的顶面是共面的。研磨工艺可以是例如化学机械抛光(CMP)。在一些实施例中，例如，如果已经暴露导电柱110，则可以省略研磨。
在图14中，在密封剂122和中间封装件100上形成再分布结构124。再分布结构124包括多个介电层和金属化图案。应当理解，再分布结构124的图示是示意性的。例如，再分布结构124实际上被图案化为通过相应的介电层彼此分离的多个分立部分。再分布结构124可以是例如再分布层(RDL)，并且可以包括金属迹线(或金属线)以及位于金属迹线下方并连接至金属迹线的通孔。作为形成再分布结构124的实例，可以沉积每个相应的介电层，并且可以在沉积的介电层中形成开口。可以通过例如可接受的光刻和镀工艺在沉积的介电层上且在开口中形成金属迹线和通孔。
在图15中，导电连接件126形成为连接至再分布结构124。可以在位于再分布结构124的外侧上的焊盘上形成导电连接件126。焊盘可以形成为接触再分布结构124中的金属化图案，并且可以将其称为凸块下金属(UBM)。导电连接件126可以是球栅阵列(BGA)连接件、焊球、金属柱、可控坍塌芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯-浸金技术(ENEPIG)形成的凸块等。导电连接件126可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。在一些实施例中，首先通过诸如蒸发、电镀、印刷、焊料转移、球放置等通常使用的方法形成焊料层来形成导电连接件126。一旦已经在结构上形成焊料层，就可以实施回流，以将材料成形为期望的凸块形状。在另一实施例中，导电连接件126是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以没有焊料并且具有大致垂直的侧壁。
在图16中，实施载体衬底脱粘以将载体衬底118从密封剂122和中间封装100的背侧脱粘(去接合)。根据一些实施例，脱粘包括将诸如激光或UV光的光投射到粘合剂120上，从而使得粘合剂120在光的热量下分解，并且可以去除载体衬底118。
在图17中，沿着划线区160分割相邻的器件区200A和200B以形成器件封装件200。可以通过锯切、切割等来实施分割。图18示出分割后得到的器件封装件200。
在图19中，通过将器件封装件200安装到封装衬底202来形成器件封装件300。在实施例中，器件封装件300是衬底上晶圆上芯片(CoWoS)封装件，但是应当理解，实施例可以应用于其他3DIC封装件。
封装衬底202可以由诸如硅、锗等的半导体材料制成。可选地，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、它们的组合等的化合物材料。额外地，封装衬底202可以是SOI衬底。通常，SOI衬底包括诸如外延的硅、锗、硅锗、SOI、SGOI或它们的组合的半导体材料层。在一个可选实施例中，封装衬底202基于诸如玻璃纤维增强的树脂芯的绝缘芯。一种示例性芯材料是诸如FR4的玻璃纤维树脂。用于芯材料的可选材料包括双马来酰亚胺-三嗪BT树脂，或者可选地，其他PCB材料或膜。诸如ABF或其他层压件的构建膜可用于封装衬底202。
封装衬底202可以包括有源器件和无源器件。本领域中的普通技术人员将意识到，诸如晶体管、电容器、电阻器、这些的组合等的多种器件可以产生用于器件封装件200的设计的结构和功能需求。可以使用任何合适的方法来形成器件。在一些实施例中，封装衬底202基本上没有有源器件和无源器件。
封装衬底202还可以包括金属化层和通孔以及位于金属化层和通孔上方的接合焊盘。金属化层可以形成在有源器件和无源器件上方并且设计为连接各个器件以形成功能电路。金属化层可以由介电材料(例如，低k介电材料)和导电材料(例如，铜)的交替层形成，其中，通孔互连导电材料层，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)来形成。
回流导电连接件126以将器件封装件200附接至封装衬底202。导电连接件126将封装衬底202(包括封装衬底202中的金属化层)电连接且物理连接至器件封装件200。可以在器件封装件200和封装衬底202之间，围绕导电连接件126形成底部填充物204。底部填充物204可以在附接器件封装件200之后通过毛细管流动工艺形成，或者可以在附接器件封装件200之前通过合适的沉积方法形成。
在一些实施例中，在封装衬底202上，在与导电连接件126相对的一侧上形成导电连接件206。导电连接件206可以是例如BGA连接件，并且可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。
应当理解，器件封装件300可以形成有其他变型。图20示出根据一些其他实施例的器件封装件300。图21示出根据其他实施例的器件封装件300。
在图20的实施例中，中间封装件100不单独分割并且粘附至载体衬底118。而是，在暴露贯通孔74之后，在晶圆70上形成再分布结构124。可以省略导电柱110、绝缘层112和密封剂122，并且可以在晶圆70上直接形成再分布结构124，例如，再分布结构124的底部介电层可以物理地接触衬底72。然后，同时分割晶圆70和再分布结构124以形成器件封装件200。
在图21的实施例中，中间封装件100形成为包括多个堆叠的集成电路器件50，诸如第一和第二集成电路器件50A和50B。例如，第一集成电路器件50A可以形成为包括位于两侧上的连接件54，并且可以在连接件54之间形成贯通孔64。可以在第一集成电路器件50A的两侧上形成光敏粘合膜56。第二集成电路器件50B可以包括连接件132和光敏粘合膜134，并且可以粘附至第一集成电路器件50A。在连接件54和132之间形成具有气隙138的额外的导电连接件136。可以在中间封装件100中堆叠更多或更少的集成电路器件50。
现在将根据一些实施例说明用于形成器件封装件的额外工艺。可以以与上面讨论的类似命名的部件类似的方式形成后续工艺和器件的一些部件。因此，这里不再重复形成细节。
图22至图33是根据一些实施例的在用于形成器件封装件500的工艺期间的中间步骤的各个图。在以下实施例的描述中，相同的参考标号表示来自先前描述的实施例的相同参考标号。在图22至图27中，通过将集成电路器件50接合至晶圆70的正侧来形成中间封装件400。分割中间封装件400。在图28至图33中，实施进一步处理以形成器件封装件500。图22至图33是截面图，其中，以“A”标记结尾的图示出整体图，以及以“B”标记结尾的图示出来自相应“A”图的区域R4的详细图。
在图22中，图案化光敏粘合膜78以形成开口402，从而暴露一些连接件76。可以与开口80的图案化同时图案化开口402。开口80和402可以是相同的尺寸，或可以是不同的尺寸。
在图23A和图23B中，在位于连接件76上的开口80中形成导电层82。然后在位于开口80中的导电层82上形成可回流层84。导电层82和可回流层84形成在开口80中，并且不形成在开口402中。
在图24中，形成贯通孔404。作为形成贯通孔404的实例，在光敏粘合膜78上方且在开口402中形成晶种层。在一些实施例中，晶种层是金属层，其中，该金属层可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。例如，可以使用PVD等形成晶种层。在晶种层上形成并且图案化光刻胶。可通过旋涂等形成光刻胶并且可将光刻胶暴露于光从而用于图案化。光刻胶的图案对应于贯通孔。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中且在晶种层的暴露部分上形成导电材料。可通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括诸如铜、钛、钨、铝等的金属。去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成贯通孔404。可以在每个集成电路器件50周围对称或不对称地形成贯通孔404。
在图25A和图25B中，多个集成电路器件50附接至晶圆70。在附接之前，可以如本文所述处理集成电路器件50。例如，在集成电路器件50的有源侧上形成连接件54，并且可以在集成电路器件50中形成通孔64。光敏粘合膜56形成在集成电路器件50上并被图案化。然后使用光敏粘合膜56和78作为粘合剂以面至面的方式将集成电路器件50接合至晶圆70，以及进行回流工艺以形成由气隙106围绕的导电连接件102。
在图26中，沿着划线区406在相邻的器件区400A和400B之间分割晶圆70，以形成中间封装件400。可以通过锯切、切割等来实施分割。图27示出分割之后的中间封装件400。
在图28中，将分割的中间封装件400粘附至载体衬底408。载体衬底408可以类似于载体衬底118。载体衬底408包括多个器件区500A和500B，其中，通过粘合剂410附接中间封装件400。粘合剂410位于中间封装件400的背侧上。
在图29中，在各个组件上形成密封剂412。密封剂412可以类似于密封剂122。可以在中间封装件400上方形成密封剂412，从而使得掩埋或覆盖贯通孔404。在固化之后，密封剂412可以经受研磨工艺以暴露贯通孔64和404。在研磨工艺之后，贯通孔64和404以及密封剂412的顶面是共面的。
在图30中，在密封剂412和中间封装件100上形成再分布结构414。再分布结构414可以类似于再分布结构124。然后形成连接至再分布结构414的导电连接件416。导电连接件416可以类似于导电连接件126。
在图31中，实施载体衬底脱粘以将载体衬底408从密封剂412和中间封装400的背侧脱粘(去接合)。
在图32中，沿着划线区418分割相邻的器件区500A和500B以形成器件封装件500。可以通过锯切、切割等来实施分割。图33示出分割后得到的器件封装件500。
应当理解，器件封装件500可以形成有其他变型。图34示出根据一些其他实施例的器件封装件500。图35示出根据其他实施例的器件封装件500。图36示出根据其他实施例的器件封装件500。
在图34的实施例中，中间封装件400不单独分割并且粘附至载体衬底408。相反，在附接集成电路器件50之后，在晶圆70上直接形成密封剂412。密封剂412可以掩埋集成电路器件50。然后平坦化集成电路器件50和密封剂412，并且在集成电路器件50和密封剂412上形成再分布结构414。然后，同时分割晶圆70和再分布结构414以形成器件封装件500。
图35的实施例类似于图34的实施例，但是在介电层420上放置中间封装件400并且将中间封装件400密封在密封剂412中。可以穿过密封剂412，邻近中间封装件400形成贯通孔422。在中间封装件400和贯通孔420上形成再分布结构414。在介电层420中成开口424，从而暴露贯通孔422。
图36的实施例类似于图34的实施例，除了中间封装件400形成为包括多个堆叠的集成电路器件50，诸如第一和第二集成电路器件50A和50B。与本文描述的其他实施例类似，可以在一些堆叠的集成电路器件50中形成贯通孔64。
图37至图46是根据一些实施例的在用于形成器件封装件600的工艺期间的中间步骤的各个图。在实施例中，器件封装件600是集成扇出(InFO)封装件，但是应当理解，实施例可以应用于其他3DIC封装件。图37至图46是截面图，其中，以“A”标记结尾的图示出整体图，以及以“B”标记结尾的图示出来自相应“A”图的区域R5的详细图。
在图37中，提供载体衬底602，并且在载体衬底602上形成背侧再分布结构604。背侧再分布结构604包括多个介电层和金属化图案。可以以与背侧再分布结构124类似的方式形成背侧再分布结构604。
在图38中，在背侧再分布结构604上形成贯通孔606。贯通孔606可以类似于贯通孔404。
在图39中，通过粘合剂610将集成电路管芯608粘附至背侧再分布层604。在其他实施例中，多个集成电路管芯608可以粘附至背侧再分布结构604。诸如导电柱(例如，包括诸如铜的金属)的管芯连接件612位于集成电路管芯608的有源侧上，并且介电材料614位于集成电路管芯608的有源侧上，位于管芯连接件612周围。
在图40中，在贯通孔606和集成电路管芯608上和周围形成密封剂616。密封剂616可以类似于密封剂122。可以平坦化密封剂616，从而使得贯通孔606、管芯连接件612、介电材料614和密封剂616的顶面齐平。
在图41中，在贯通孔606、集成电路管芯608和密封剂616上形成正侧再分布结构618。正侧再分布结构618包括多个介电层620和金属化图案622。正侧再分布结构618的最顶层是光敏粘合膜624，并且形成在最顶部金属化图案622上。图案化光敏粘合膜624以形成开口626，从而暴露金属化图案622。
在图42A和图42B中，在位于金属化图案622上的开口626中形成导电层82。然后在位于开口626中的导电层82上形成可回流层84。在其他实施例中，导电层82和可回流层84可以形成在该位置处。
在图43A和图43B中，集成电路器件50附接至正侧再分布结构618。在附接之前，可以如本文所述处理集成电路器件50；例如，集成电路器件可以是处理器、存储器等。例如，在集成电路器件50的有源侧上形成连接件54。光敏粘合膜56形成在集成电路器件50上并被图案化。集成电路器件50压在正侧再分布结构618上，从而使得光敏粘合膜56和624彼此粘附。因此在可回流层62和84之间形成气隙104。
在图44A和图44B中，实施回流工艺以回流可回流层62和84，从而形成导电连接件102。在导电连接件102周围形成气隙106。
在图45中，实施载体衬底脱粘以使载体衬底602与背侧再分布结构604脱粘(去接合)。
在图46中，导电连接件628形成为连接至背侧再分布结构604。可以在背侧再分布结构604的背侧中形成开口，从而暴露背侧再分布结构604的金属化图案。然后在开口中形成导电连接件628。
图47至图57是根据一些实施例的在用于形成器件封装件700的工艺期间的中间步骤的各个图。在实施例中，器件封装件700是多堆叠(MUST)封装件，但是应当理解，实施例可以应用于其他3DIC封装件。图47至图57是截面图，其中，以“A”标记结尾的图示出整体图，以及以“B”标记结尾的图示出来自相应“A”图的区域R6的详细图。
在图47中，提供载体衬底702，并且通过粘合剂706将集成电路管芯704粘附至载体衬底702。诸如导电柱(例如，包括诸如铜的金属)的管芯连接件708位于集成电路管芯704的有源侧上，并且介电材料710位于集成电路管芯704的有源侧上，位于管芯连接件708周围。
在图48中，在集成电路管芯704上和周围形成密封剂712。可以平坦化密封剂712，从而使得管芯连接件708、介电材料710和密封剂712的顶面齐平。
在图49中，在集成电路管芯704和密封剂712上形成光敏粘合膜714。图案化光敏粘合膜714以形成开口716和718，从而暴露管芯连接件708。开口716和718位于集成电路管芯704的不同区域中。
在图50A和图50B中，在位于管芯连接件708上的开口716中形成导电层82。然后在位于开口716中的导电层82上形成可回流层84。不在开口718中形成导电层82和可回流层84。
在图51中，在光敏粘合膜714上形成贯通孔720。贯通孔720可以类似于贯通孔404。
在图52A和图52B中，集成电路器件50附接至光敏粘合膜714。在附接之前，可以如本文所述处理集成电路器件50。例如，在集成电路器件50的有源侧上形成连接件54。光敏粘合膜56形成在集成电路器件50上并被图案化。将集成电路器件50压在光敏粘合膜714上，从而使得光敏粘合膜56和714彼此粘附。因此在可回流层62和84之间形成气隙104。
在图53A和图53B中，实施回流工艺以回流可回流层62和84，从而形成导电连接件102。在导电连接件102周围形成气隙106。
在图54中，在光敏粘合膜714上并且在集成电路器件50和贯通孔720周围形成密封剂722。可以平坦化密封剂722，从而使得集成电路器件50、贯通孔720和密封剂722的顶面齐平。
在图55中，在贯通孔720、集成电路器件50和密封剂722上形成正侧再分布结构724。正侧再分布结构724包括多个介电层和金属化图案。
在图56中，实施载体衬底去接合以将载体衬底702与集成电路管芯704和密封剂712脱粘(去接合)。
在图57中，导电连接件726形成为连接至正侧再分布结构724。可以在正侧再分布结构724的正侧中形成开口，从而暴露正侧再分布结构724的金属化图案。然后在开口中形成导电连接件726。
应当理解，可以以其他方式形成导电连接件102。图58A至图58F示出根据一些其他实施例的用于形成导电连接件102的工艺。图59A至图59K示出根据其他实施例的用于形成导电连接件102的工艺。图60A至图60F示出根据其他实施例的用于形成导电连接件102的工艺。根据后续描述形成的导电连接件102可以用在任何上述实施例中。
在图58A至图58F的实施例中，在光敏粘合膜78的开口80中形成晶种层802。在光敏粘合膜78上形成光刻胶804，并且利用暴露连接件76的开口进行图案化。在位于光刻胶804中且位于连接件76上的开口中形成导电层82和可回流层84。这样，导电层82沿开口80的侧面延伸。去除光刻胶804，并且通过例如CMP工艺去除开口80外部的导电层82和可回流层84的多余材料。可以在光敏粘合膜56的开口58中重复该工艺。后续地，如上图5A至图6B所述，接合光敏粘合膜56和78，并且回流可回流层62和84。
在图59A至图59K的实施例中，在光敏粘合膜56的开口58中形成晶种层902。然后在晶种层902上形成光刻胶904。光刻胶904沿着光敏粘合膜56延伸，并且一些部分形成在开口58中。利用开口图案化光刻胶904，其中，该开口暴露连接件54上的晶种层902的部分。在用于形成导电层60的镀工艺中，并且在用于形成可回流层62的镀工艺中使用晶种层902。晶种层902、导电层60和可回流层62的组合厚度T5可以大于光敏粘合膜56的厚度T1。在形成导电层60和可回流层62之后，去除光刻胶904和晶种层902的暴露部分。值得注意的是，可回流层62的宽度小于开口58的宽度，并且因此当去除开口58中的光刻胶904时，暴露连接件54的部分。
在衬底72上形成光刻胶906，并且利用暴露连接件76的开口进行图案化。实施诸如干蚀刻或湿蚀刻的金属蚀刻工艺，以在连接件76中形成开口908。然后在开口908中形成导电层82和可回流层84。导电层82和可回流层84的组合厚度可以大于或小于开口908的深度，但是不延伸到后续形成的光敏粘合膜78的顶面之上。在所示实施例中，通过化学镀工艺在开口908中镀导电层82和可回流层84，但是应当理解，可以在其他镀工艺中形成晶种层。然后去除光刻胶906，并且形成光敏粘合膜78以及用暴露导电层82的开口进行图案化。
然后将集成电路器件50附接至晶圆70。由于晶种层902、导电层60和可回流层62的厚度T5(参见图59E)，可回流层62延伸到位于光敏粘合膜56中的开口58中。在实施例中，在固化光敏粘合膜56之后但在固化光敏粘合膜78之前，附接集成电路器件50。如上图5A至图6B所述，实施回流工艺，从而形成由气隙106围绕的导电连接件102。回流工艺还可以固化光敏粘合膜78，从而将光敏粘合膜56和78接合在一起。
在图60A至图60F的实施例中，在集成电路器件50的正侧上形成晶种层952。然后在晶种层952上形成光刻胶954。利用开口图案化光刻胶954，其中，开口暴露连接件54上的晶种层952的部分。在用于形成导电层60的镀工艺中，并且在用于形成可回流层62的镀工艺中，使用晶种层952。在形成导电层60和可回流层62之后，去除光刻胶954和晶种层952的暴露部分。然后，在衬底52上形成光敏粘合膜56，并且特别地，在可回流层62上方形成光敏粘合膜56。然后在光敏粘合膜56中形成开口58，从而暴露导电层60和可回流层62。值得注意的是，可回流层62的宽度小于开口58的宽度，并且当形成开口58时，暴露连接件54的一些部分。晶种层952、导电层60和可回流层62的组合厚度T6可以大于光敏粘合膜56的厚度T1。
然后将集成电路器件50附接至晶圆70。类似于上述实施例，可以在晶圆70的连接件76中形成开口。由于晶种层952、导电层60和可回流层62的厚度T6，可回流层62延伸到位于光敏粘合膜56中的开口58中。在所示实施例中，在形成在连接件76中的开口中镀导电层82和可回流层84。在实施例中，在固化光敏粘合膜56之后但在固化光敏粘合膜78之前，附接集成电路器件50。然后固化光敏粘合膜78，从而将光敏粘合膜56和78粘附在一起。如上图5A至图6B所述，实施回流工艺，从而形成由气隙106围绕的导电连接件102。
图61A至图61B示出根据一些其他实施例的用于形成导电连接件102的工艺。图61B是图61A的结构的顶视图。在所示实施例中，图案化光敏粘合膜56和78，从而使得它们仅形成在集成电路器件50的周边周围。这样，在接合和回流之后，形成腔1002，其中，每个导电连接件102暴露于腔1002。腔1002可以形成为具有围绕周边的开口1004，从而提供空气移动路径。开口1004可具有从约5μm至约50μm的宽度。在一些实施例中，在顶视图中开口1004可以形成为具有弯曲，以防止密封剂108流入到腔1002中。
实施例可以实现优势。形成气隙106在相邻的导电连接件102之间创建缓冲空间，从而允许导电连接件102以更精细的间距形成。使用光敏粘合膜56和78可以简化面对面接合，从而降低制造成本。
在实施例中，一种器件包括：第一器件，包括：具有第一连接件的集成电路器件；第一光敏粘合层，位于集成电路器件上；以及第一导电层，位于第一连接件上，第一光敏粘合层围绕第一导电层；第二器件，包括：具有第二连接件的内插器；第二光敏粘合层，位于内插器上，第二光敏粘合层物理连接至第一光敏粘合层；以及第二导电层，位于第二连接件上，第二光敏粘合层围绕第二导电层；以及导电连接件，接合第一导电层和第二导电层，通过气隙围绕导电连接件。
在器件的一些实施例中，第一导电层的第一宽度小于第二导电层的第二宽度。在该器件的一些实施例中，导电连接件具有与第一集成电路器件相邻的第一部分和与第二集成电路器件相邻的第二部分，第一部分具有第一宽度，第二部分具有第二宽度。在该器件的一些实施例中，气隙将导电连接件的第二部分与第一光敏粘合层分离。在该器件的一些实施例中，在第一连接件和第一导电层之间或第一导电层和导电连接件之间不形成晶种层。在一些实施例中，该器件还包括：第一晶种层，形成在第一连接件和第一导电层之间，其中，在第一导电层和导电连接件之间不形成晶种层。
在实施例中，一种方法包括：在第一光敏粘合层中形成第一开口，第一光敏粘合层与第一集成电路器件的第一侧相邻；在第一开口中镀第一可回流层；在第二光敏粘合层中形成第二开口，第二光敏粘合层与第二集成电路器件的第一侧相邻；在第二开口中镀第二可回流层；将第一和第二光敏粘合层压在一起，从而物理连接第一和第二集成电路器件；以及回流第一和第二可回流层，从而形成电连接第一和第二集成电路器件的导电连接件。
在一些实施例中，该方法还包括：用模塑料密封第一集成电路器件，模塑料与第二集成电路器件的第一侧相邻；分割第一集成电路器件；形成与第二集成电路器件的第二侧相邻的再分布结构；以及在再分布结构上形成导电球。在一些实施例中，该方法还包括：使用导电球将第二集成电路器件接合至封装衬底。在一些实施例中，该方法还包括：在第三光敏粘合层中形成第三开口，第三光敏粘合层与第一集成电路器件的第二侧相邻；在第三开口中镀第三可回流层；以及使用第三光敏粘合层和第三可回流层将第三集成电路器件物理连接至第一集成电路器件。在一些实施例中，该方法还包括：在第二集成电路器件的第一侧上形成第一通孔；形成与第二集成电路器件的第二侧相邻的再分布结构，再分布结构电连接至第一通孔；在再分布结构上形成导电连接件；以及分割第一集成电路器件和再分布结构。在一些实施例中，该方法还包括：形成与第一和第二集成电路器件相邻的第二通孔；以及用模塑料密封第一通孔和第二通孔。在该方法的一些实施例中，在回流第一可回流层之后，通过气隙围绕导电连接件。
在实施例中，一种方法包括：用第一模塑料密封多个第一集成电路器件；在第一集成电路器件上方形成第一光敏粘合层；在第一光敏粘合层中图案化第一开口；在第一开口中镀第一导电层；在第一导电层上镀第一可回流层，第一导电层和第一可回流层的组合厚度小于第一光敏粘合层的第一厚度，第一导电层和第一可回流层电连接至第一集成电路器件；将第二集成电路器件压至第一光敏粘合层，以物理连接第一和第二集成电路器件；以及回流第一可回流层以形成电连接第一和第二集成电路器件的导电连接件。
在一些实施例中，该方法还包括：在第一集成电路器件上方形成第一再分布结构，第一光敏粘合层是第一再分布结构的最顶层，第二集成电路器件在回流第一可回流层之后接合至第一再分布结构。在一些实施例中，该方法还包括：将第一集成电路器件放置在第二再分布结构上。在一些实施例中，该方法还包括：形成延伸穿过第一模塑料的通孔，该通孔电连接第一和第二再分布结构。在一些实施例中，该方法还包括：用第二模塑料密封第二集成电路器件；以及在第二集成电路器件和第二模塑料上方形成第一再分布结构。在一些实施例中，该方法还包括：形成延伸穿过第二模塑料的通孔，该通孔电连接第一再分布结构和第一集成电路器件。在该方法的一些实施例中，在回流第一可回流层之后，通过气隙围绕导电连接件。
根据本发明的一些实施例，提供了一种半导体器件，包括：第一器件，包括：集成电路器件，具有第一连接件；第一光敏粘合层，位于所述集成电路器件上；以及第一导电层，位于所述第一连接件上，所述第一光敏粘合层围绕所述第一导电层；第二器件，包括：内插器，具有第二连接件；第二光敏粘合层，位于所述内插器上，所述第二光敏粘合层物理连接至所述第一光敏粘合层；以及第二导电层，位于所述第二连接件上，所述第二光敏粘合层围绕所述第二导电层；以及导电连接件，接合所述第一导电层和所述第二导电层，通过气隙围绕所述导电连接件。
在上述半导体器件中，所述第一导电层的第一宽度小于所述第二导电层的第二宽度。
在上述半导体器件中，所述导电连接件具有与第一集成电路器件相邻的第一部分和与第二集成电路器件相邻的第二部分，所述第一部分具有第一宽度，所述第二部分具有大于所述第一宽度的第二宽度。
在上述半导体器件中，所述气隙将所述导电连接件的第二部分与所述第一光敏粘合层分离。
在上述半导体器件中，在所述第一连接件和所述第一导电层之间或所述第一导电层和所述导电连接件之间不形成晶种层。
在上述半导体器件中，还包括：第一晶种层，形成在所述第一连接件和所述第一导电层之间，其中，在所述第一导电层和所述导电连接件之间不形成晶种层。
根据本发明的另一些实施例，还提供了一种形成半导体器件的方法，包括：在第一光敏粘合层中形成第一开口，所述第一光敏粘合层与第一集成电路器件的第一侧相邻；在所述第一开口中镀第一可回流层；在第二光敏粘合层中形成第二开口，所述第二光敏粘合层与第二集成电路器件的第一侧相邻；在所述第二开口中镀第二可回流层；将所述第一光敏粘合层和所述第二光敏粘合层压在一起，从而物理连接所述第一集成电路器件和所述第二集成电路器件；以及回流所述第一可回流层和所述第二可回流层，从而形成电连接所述第一集成电路器件和所述第二集成电路器件的导电连接件。
在上述方法中，还包括：用模塑料密封所述第一集成电路器件，所述模塑料与所述第二集成电路器件的第一侧相邻分割所述第一集成电路器件；形成与所述第二集成电路器件的第二侧相邻的再分布结构；以及在所述再分布结构上形成导电球。
在上述方法中，还包括：使用所述导电球将所述第二集成电路器件接合至封装衬底。
在上述方法中，还包括：在第三光敏粘合层中形成第三开口，所述第三光敏粘合层与所述第一集成电路器件的第二侧相邻；在所述第三开口中镀第三可回流层；使用所述第三光敏粘合层和所述第三可回流层将第三集成电路器件物理连接至所述第一集成电路器件。
在上述方法中，还包括：在所述第二集成电路器件的第一侧上形成第一通孔；形成与所述第二集成电路器件的第二侧相邻的再分布结构，所述再分布结构电连接至所述第一通孔；在所述再分布结构上形成导电连接件；以及分割所述第一集成电路器件和所述再分布结构。
在上述方法中，还包括：形成与所述第一集成电路器件和所述第二集成电路器件相邻的第二通孔；用模塑料密封所述第一通孔和所述第二通孔。
在上述方法中，在回流所述第一可回流层之后，通过气隙围绕所述导电连接件。
根据本发明的另一些实施例，还提供了一种形成半导体器件的方法，包括：用第一模塑料密封多个第一集成电路器件；在所述第一集成电路器件上方形成第一光敏粘合层；在所述第一光敏粘合层中图案化第一开口；在所述第一开口中镀第一导电层；在所述第一导电层上镀第一可回流层，所述第一导电层和所述第一可回流层的组合厚度小于所述第一光敏粘合层的第一厚度，所述第一导电层和所述第一可回流层电连接至所述第一集成电路器件；将第二集成电路器件压至所述第一光敏粘合层，以物理连接所述第一集成电路器件和所述第二集成电路器件；以及回流所述第一可回流层以形成电连接所述第一集成电路器件和所述第二集成电路器件的导电连接件。
在上述方法中，还包括：在所述第一集成电路器件上方形成第一再分布结构，所述第一光敏粘合层是所述第一再分布结构的最顶层，所述第二集成电路器件在回流所述第一可回流层之后接合至所述第一再分布结构。
在上述方法中，还包括：在第二再分布结构上放置所述第一集成电路器件。
在上述方法中，还包括：形成延伸穿过所述第一模塑料的通孔，所述通孔电连接所述第一再分布结构和所述第二再分布结构。
在上述方法中，还包括：用第二模塑料密封所述第二集成电路器件；以及在所述第二集成电路器件和所述第二模塑料上方形成第一再分布结构。
在上述方法中，还包括：形成延伸穿过所述第二模塑料的通孔，所述通孔电连接所述第一再分布结构和所述第一集成电路器件。
在上述方法中，在回流所述第一可回流层之后，通过气隙围绕所述导电连接件。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，包括：
第一器件，包括：
集成电路器件，具有第一连接件；
第一光敏粘合层，位于所述集成电路器件上；以及
第一导电层，位于所述第一连接件上，所述第一光敏粘合层围绕所述第一导电层；
第二器件，包括：
内插器，具有第二连接件；
第二光敏粘合层，位于所述内插器上，所述第二光敏粘合层物理连接至所述第一光敏粘合层；以及
第二导电层，位于所述第二连接件上，所述第二光敏粘合层围绕所述第二导电层；以及
导电连接件，接合所述第一导电层和所述第二导电层，通过气隙围绕所述导电连接件。
2.根据权利要求1所述的半导体器件，其中，所述第一导电层的第一宽度小于所述第二导电层的第二宽度。
3.根据权利要求2所述的半导体器件，其中，所述导电连接件具有与第一集成电路器件相邻的第一部分和与第二集成电路器件相邻的第二部分，所述第一部分具有第一宽度，所述第二部分具有大于所述第一宽度的第二宽度。
4.根据权利要求3所述的半导体器件，其中，所述气隙将所述导电连接件的第二部分与所述第一光敏粘合层分离。
5.根据权利要求1所述的半导体器件，其中，在所述第一连接件和所述第一导电层之间或所述第一导电层和所述导电连接件之间不形成晶种层。
6.根据权利要求1所述的半导体器件，还包括：
第一晶种层，形成在所述第一连接件和所述第一导电层之间，其中，在所述第一导电层和所述导电连接件之间不形成晶种层。
7.一种形成半导体器件的方法，包括：
在第一光敏粘合层中形成第一开口，所述第一光敏粘合层与第一集成电路器件的第一侧相邻；
在所述第一开口中镀第一可回流层；
在第二光敏粘合层中形成第二开口，所述第二光敏粘合层与第二集成电路器件的第一侧相邻；
在所述第二开口中镀第二可回流层；
将所述第一光敏粘合层和所述第二光敏粘合层压在一起，从而物理连接所述第一集成电路器件和所述第二集成电路器件；以及
回流所述第一可回流层和所述第二可回流层，从而形成电连接所述第一集成电路器件和所述第二集成电路器件的导电连接件。
8.根据权利要求7所述的方法，还包括：
用模塑料密封所述第一集成电路器件，所述模塑料与所述第二集成电路器件的第一侧相邻；
分割所述第一集成电路器件；
形成与所述第二集成电路器件的第二侧相邻的再分布结构；以及
在所述再分布结构上形成导电球。
9.根据权利要求8所述的方法，还包括：
使用所述导电球将所述第二集成电路器件接合至封装衬底。
10.一种形成半导体器件的方法，包括：
用第一模塑料密封多个第一集成电路器件；
在所述第一集成电路器件上方形成第一光敏粘合层；
在所述第一光敏粘合层中图案化第一开口；
在所述第一开口中镀第一导电层；
在所述第一导电层上镀第一可回流层，所述第一导电层和所述第一可回流层的组合厚度小于所述第一光敏粘合层的第一厚度，所述第一导电层和所述第一可回流层电连接至所述第一集成电路器件；
将第二集成电路器件压至所述第一光敏粘合层，以物理连接所述第一集成电路器件和所述第二集成电路器件；以及
回流所述第一可回流层以形成电连接所述第一集成电路器件和所述第二集成电路器件的导电连接件。
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