CN115498999B

CN115498999B - Phase tracking loop and method based on frequency division and clock acceleration and electronic equipment

Info

Publication number: CN115498999B
Application number: CN202211129085.4A
Authority: CN
Inventors: 刘览琦; 把傲; 柯毅; 马可铮
Original assignee: Wuhan Silicon Integrated Co Ltd
Current assignee: Wuhan Silicon Integrated Co Ltd
Priority date: 2022-09-16
Filing date: 2022-09-16
Publication date: 2023-08-29
Anticipated expiration: 2042-09-16
Also published as: CN115498999A

Abstract

The invention relates to a phase tracking loop and method based on frequency division and clock acceleration and an electronic device. A phase tracking loop may include: the frequency divider is used for carrying out frequency division processing on the first clock signal to obtain a carrier signal; a phase detector for comparing the phases of the carrier signal and a reference clock signal to generate a phase indication signal; a phase tuning module for adjusting the phase of the first clock signal based on the phase indication signal such that the phase of the carrier signal is closer to the phase of the reference clock signal; and a control module for controlling an operating clock of the phase tuning module and a frequency division ratio of the frequency divider based on the phase indication signal.

Description

Phase tracking loop and method based on frequency division and clock acceleration and electronic equipment

Technical Field

The present invention relates to a phase tracking loop and a phase tracking method based on a combination of frequency division acceleration and clock acceleration, and an electronic apparatus including the phase tracking loop.

Background

In the field of wireless communications, phase tracking is sometimes required for received signals. For example, in a Near Field Communication (NFC) scenario, since amplitude modulation is used, the reader needs to track the phase of the signal read from the NFC card, and when the phase difference between the two is large, amplitude information may be lost. The signal read by the card reader from the NFC card comes from the signal generated by the load modulation of the NFC card, and the NFC card can generally adopt one of two schemes of Passive Load Modulation (PLM) and Active Load Modulation (ALM). When the passive load modulation scheme is adopted, the NFC card is completely dependent on the radio frequency signal provided by the card reader to generate a passive reading signal, so that no phase difference exists, but the generated passive reading signal has smaller energy, the communication distance is limited, and the NFC card is easy to interfere. When an active load modulation scheme is employed, an NFC device (e.g., a cell phone) in a card emulation role may simulate the load modulation process, actively transmitting a carrier signal that is phase-aligned with the reader device. Active load modulation schemes can provide greater signal power and better anti-interference characteristics, but may present phase bias issues because the carrier signal actively transmitted by the NFC device is not the same source as the reader signal.

Disclosure of Invention

The present invention generally provides a phase tracking loop and method based on frequency division and clock acceleration, and an electronic device including such a phase tracking loop. The phase tracking loop and method can adjust the signal phase at a variety of different speeds to track the target phase quickly and with high accuracy over a large range of phase differences and also save power consumption.

According to an embodiment, a phase tracking loop may comprise: the frequency divider is used for carrying out frequency division processing on the first clock signal to obtain a carrier signal; a phase detector for comparing the phases of the carrier signal and a reference clock signal to generate a phase indication signal; a phase tuning module for adjusting the phase of the first clock signal based on the phase indication signal such that the phase of the carrier signal is closer to the phase of the reference clock signal; and a control module for controlling an operating clock of the phase tuning module and a frequency division ratio of the frequency divider based on the phase indication signal.

In an embodiment, the phase detector is a binary phase detector, and the phase indication signal output by the binary phase detector indicates that the phase of the carrier signal is either advanced or retarded relative to the phase of the reference clock signal.

In one embodiment, the phase tuning module comprises: a digital loop filter for generating a first clock selection signal based on the phase indication signal; and a first clock selection unit for selecting one clock signal from among the multiphase clock signals as the first clock signal based on the first clock selection signal.

In one embodiment, the control module includes: a dynamic detection adjustment unit for detecting the phase indication signal generated by the phase detector and generating a second clock selection signal and a frequency division ratio adjustment signal; a second clock selection unit configured to select one of a plurality of second clock signals as an operation clock of the digital loop filter based on the second clock selection signal; and a frequency division ratio control unit for controlling the frequency division ratio of the frequency divider based on the frequency division ratio adjustment signal.

In an embodiment, the plurality of second clock signals includes one or more divided signals provided by the divider.

In an embodiment, the plurality of second clock signals further includes the first clock signal provided by the first clock selection unit.

In an embodiment, when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the second clock selection signal generated by the dynamic detection adjustment unit indicates that the second clock selection unit selects a clock signal of a higher frequency than the currently selected clock signal from the plurality of second clock signals, and the frequency division ratio adjustment signal generated by the dynamic detection adjustment unit indicates that the frequency division ratio control unit increases the frequency division gear of the frequency divider. When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the second clock selection signal generated by the dynamic detection adjustment unit instructs the second clock selection unit to select a frequency division signal of a lower frequency than the currently selected clock signal from the plurality of second clock signals, and the frequency division ratio adjustment signal generated by the dynamic detection adjustment unit instructs the frequency division ratio control unit to lower the frequency division gear of the frequency divider. The frequency divider has a basic gear having a basic frequency division ratio N, and at least one higher gear having a higher frequency division ratio n+x or a lower frequency division ratio N-x, N being a preset positive integer, x being a smaller positive integer than N and the higher the gear, the larger the value of x, the higher gear having the higher frequency division ratio n+x when the phase indication signal indicates that the phase of the carrier signal is more advanced than the phase of the reference clock signal, and the lower frequency division ratio N-x when the phase indication signal indicates that the phase of the carrier signal is more retarded than the phase of the reference clock signal.

In an embodiment, the carrier signal is a frequency-divided signal having a lowest frequency among a plurality of frequency-divided signals provided by the frequency divider, and the base frequency-dividing ratio N is such that the frequency of the carrier signal is equal to the frequency of the reference clock signal.

In an embodiment, the multiphase clock signal includes M clock signals of different phases, M is an integer greater than one, and the first clock selection signal generated by the digital loop filter represents one of M index values to instruct the first clock selection unit to select a corresponding clock signal from the M clock signals of different phases as the first clock signal.

In one embodiment, the first clock selection signal generated by the digital loop filter instructs the first clock selection unit to select a clock signal from the multiphase clock signals that is more retarded than the currently selected clock signal phase when the phase indication signal generated by the phase detector indicates that the carrier signal is advanced in phase than the reference clock signal for a predetermined period. When the phase indication signal generated by the phase detector indicates that the phase of the carrier signal lags behind the phase of the reference clock signal and lasts for a predetermined period, the first clock selection signal generated by the digital loop filter indicates that the first clock selection unit selects one clock signal from the multiphase clock signals, which is more advanced than the currently selected clock signal.

In one embodiment, the digital loop filter includes: a proportional path for generating a first proportional signal that is a first proportion to the phase indication signal; an integrating path for generating a second proportional signal at a second ratio to the phase indication signal, and integrating the second proportional signal using an integrator to generate an integrated signal; an adder for adding the first proportional signal and the integral signal to output a sum of the two; and a remainder unit for performing a remainder operation on the sum value received from the adder with respect to a predetermined value to generate the first clock selection signal representing a remainder.

In an embodiment, the second clock signal selected by the second clock selection unit is used as an operation clock of an integrator in the integration path, and the predetermined value is equal to the number of clock signals having different phases included in the multiphase clock signal.

In an embodiment, the digital loop filter further comprises at least one of: a first proportion adjusting unit provided in the proportion path for adjusting the first proportion; and a second proportion adjusting unit provided in the integrating path for adjusting the second proportion.

In an embodiment, the first and second ratio adjustment units use the same adjustment coefficient to perform an equal ratio adjustment of the first and second ratios.

In an embodiment, the phase tracking loop further comprises: and a coefficient control unit configured to control an adjustment coefficient that adjusts at least one of the first ratio and the second ratio based on the coefficient adjustment signal generated by the dynamic detection adjustment unit. When the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the coefficient adjustment signal generated by the dynamic detection adjustment unit instructs the coefficient control unit to increase the adjustment coefficient to increase the at least one of the first ratio and the second ratio. When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the coefficient adjustment signal generated by the dynamic detection adjustment unit instructs the coefficient control unit to decrease the adjustment coefficient to decrease the at least one of the first ratio and the second ratio.

In an embodiment, when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the dynamic detection adjustment unit generates the coefficient adjustment signal to increase the at least one of the first ratio and the second ratio until a maximum ratio is reached, then generates the second clock selection signal to increase the frequency of the second clock signal selected by the second clock selection unit until a maximum frequency is reached, and then generates the division ratio adjustment signal to increase the division gear of the frequency divider. When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit first generates the frequency division ratio adjustment signal to decrease the frequency division shift of the frequency divider until a basic shift is reached, then generates the second clock selection signal to decrease the frequency of the second clock signal selected by the second clock selection unit until a minimum frequency is reached, and then generates the coefficient adjustment signal to decrease the at least one of the first ratio and the second ratio.

In an embodiment, when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the dynamic detection adjustment unit generates the coefficient adjustment signal to increase the at least one of the first ratio and the second ratio until a maximum ratio is reached, then generates the second clock selection signal to increase the frequency of the second clock signal selected by the second clock selection unit until a maximum frequency is reached, then generates a minimum second clock setting signal to set the frequency of the second clock signal selected by the second clock selection unit to a minimum frequency, and generates the frequency division ratio adjustment signal to increase the frequency division gear of the frequency divider. When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit generates the frequency division ratio adjustment signal to decrease the frequency division shift range of the frequency divider until a base shift range is reached, and generates a maximum second clock setting signal to set the frequency of the second clock signal selected by the second clock selection unit to the highest frequency when the frequency division shift range reaches the base shift range, and then generates the second clock selection signal to decrease the frequency of the second clock signal selected by the second clock selection unit until the lowest frequency is reached, and then generates the coefficient adjustment signal to decrease the at least one of the first proportion and the second proportion.

According to another embodiment, a phase tracking method may include: the frequency divider performs frequency division processing on the first clock signal to obtain a carrier signal; a phase detector compares the phases of the carrier signal and a reference clock signal to generate a phase indication signal; a phase tuning module adjusts a phase of the first clock signal based on the phase indication signal such that the phase of the carrier signal is closer to a phase of the reference clock signal; and a control module controls an operating clock of the phase tuning module and a frequency division ratio of the frequency divider based on the phase indication signal.

In an embodiment, the phase tuning module adjusting the phase of the first clock signal based on the phase indication signal comprises: generating a first clock selection signal based on the phase indication signal with a digital loop filter; and selecting one clock signal from among the multiphase clock signals as the first clock signal based on the first clock selection signal by using a first clock selection unit.

In an embodiment, the control module controlling the operating clock of the phase tuning module and the frequency division ratio of the frequency divider based on the phase indication signal comprises: detecting the phase indication signal generated by the phase detector by using a dynamic detection adjustment unit, and generating a second clock selection signal and a frequency division ratio adjustment signal; selecting one of a plurality of second clock signals as an operation clock of the digital loop filter based on the second clock selection signal by a second clock selection unit; and controlling the frequency division ratio of the frequency divider based on the frequency division ratio adjustment signal with a frequency division ratio control unit.

In an embodiment, the digital loop filter generates the first clock selection signal that instructs the first clock selection unit to select a clock signal from the multiphase clock signals that is more retarded than the currently selected clock signal in phase when the phase indication signal indicates that the phase of the carrier signal is advanced than the phase of the reference clock signal for a predetermined period. When the phase indication signal indicates that the phase of the carrier signal lags behind the phase of the reference clock signal and lasts for a predetermined period, the first clock selection signal generated by the digital loop filter instructs the first clock selection unit to select one clock signal from the multiphase clock signals, which is more advanced than the currently selected clock signal.

In an embodiment, generating the first clock selection signal based on the phase indication signal using a digital loop filter comprises: generating a first proportional signal in a first proportion to the phase indication signal using a proportional path; generating a second proportional signal at a second proportion to the phase indication signal with an integrating path, and performing an integrating process on the second proportional signal using an integrator provided in the integrating path to generate an integrated signal; adding the first proportional signal and the integral signal by an adder to output a sum of the first proportional signal and the integral signal; and performing a remainder operation on the sum value with respect to a predetermined value using a remainder unit to generate the first clock selection signal representing a remainder.

In an embodiment, the second clock signal selected by the second clock selection unit is used as an operation clock of an integrator in the integration path to control a speed of integrating the second proportional signal, and the predetermined value is equal to the number of clock signals having different phases included in the multiphase clock signal.

In an embodiment, generating the first clock selection signal based on the phase indication signal using a digital loop filter further comprises at least one of: adjusting the first ratio with a first ratio adjusting unit provided in the ratio path; and adjusting the second ratio with a second ratio adjustment unit provided in the integration path.

In an embodiment, the method further comprises: an adjustment coefficient for adjusting at least one of the first proportion and the second proportion is controlled by a coefficient control unit based on the coefficient adjustment signal generated by the dynamic detection adjustment unit. When the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the coefficient adjustment signal generated by the dynamic detection adjustment unit instructs the coefficient control unit to increase the adjustment coefficient to increase the at least one of the first ratio and the second ratio. When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the coefficient adjustment signal generated by the dynamic detection adjustment unit instructs the coefficient control unit to decrease the adjustment coefficient to decrease the at least one of the first ratio and the second ratio.

According to a further embodiment, an electronic device may comprise the phase tracking loop described above.

The foregoing and other features and advantages of the invention will be apparent from the following description of exemplary embodiments, as illustrated in the accompanying drawings.

Drawings

Fig. 1 shows a schematic diagram of a phase tracking loop according to an embodiment of the invention.

Fig. 2 shows a schematic diagram of a phase tracking loop according to an embodiment of the invention.

Fig. 3 shows a schematic diagram of a digital loop filter according to an embodiment of the invention.

Fig. 4 shows a schematic diagram of an integrated signal in a digital loop filter according to an embodiment of the invention.

Fig. 5 shows a schematic diagram of adjusting phase by changing the frequency division ratio according to an embodiment of the invention.

Fig. 6 shows a schematic diagram of a frequency-divided gear design according to an embodiment of the invention.

Fig. 7 shows a flow chart of a phase tracking method according to an embodiment of the invention.

Fig. 8 shows a flowchart of a phase adjustment process of the first clock signal according to an embodiment of the invention.

Fig. 9 shows a flowchart of a frequency adjustment process and a division ratio adjustment process of the second clock signal according to an embodiment of the present invention.

Fig. 10 shows a flowchart of a process of generating a second clock selection signal and a division ratio adjustment signal according to an embodiment of the present invention.

Fig. 11 shows a flowchart of a process of generating a first clock selection signal according to an embodiment of the invention.

Fig. 12 shows a flow chart of the combined use of coefficient adjustment, integral clock frequency adjustment and divider ratio adjustment according to an embodiment of the invention.

Fig. 13 shows a flow chart of the combined use of coefficient adjustment, integral clock frequency adjustment and divider position adjustment according to an embodiment of the invention.

Fig. 14 shows a schematic diagram of an electronic device according to an embodiment of the invention.

Detailed Description

Some exemplary embodiments of the present invention will be described below with reference to the accompanying drawings. In order to clearly and fully describe these exemplary embodiments, the following description provides some specific details. It should be understood, however, that the invention is not limited to the specific details of these exemplary embodiments. Rather, embodiments of the invention may be practiced without these specific details or in other alternative ways, without departing from the spirit and principles of the invention, which are defined by the claims.

Currently, phase tracking techniques for NFC card analog devices in Active Load Modulation (ALM) mode include passive matching network based solutions and solutions using an all-digital phase locked loop (ADPLL). The adjustment of the passive matching network is not linear, the steps of phase adjustment are inconsistent at different resistance values, and high-precision adjustment is difficult to realize within a large phase difference range (for example, 0 degrees to 180 degrees). In addition, the impedance of the chip can be changed by adjusting the resistance value, so that certain adverse effects are generated on wireless communication. The all-digital phase-locked loop has a complex design and high cost, and the frequency and phase information generated in the card analog mode comes entirely from the clock recovered from the reader signal, which is often intermittent. For example, when the reader transmits a signal, the magnetic field disappears when the data is at a low level; also, for example, when the NFC card emulation device itself transmits a signal, an excessive transmitted signal will drown out the magnetic field signal of the reader. Thus, under intermittent reference clock conditions, the loop lock speed requirement for a phase locked loop is very high, as only a very short time is used for frequency and phase locking, which is difficult to solve. In conventional designs, fast locking means that the loop bandwidth is larger, bringing more phase noise introduced by the reference clock, which can affect circuit performance; on the other hand, reducing the loop bandwidth, while partially improving the phase noise performance, is difficult to achieve with fast lock requirements.

An ideal phase tracking technique requires fast phase tracking and locking over a large phase difference range, and high tracking accuracy is desired. Furthermore, in view of the application in battery-powered portable electronic devices, it is also desirable to have small power consumption during phase tracking and locking, which presents challenges to existing phase tracking techniques.

Fig. 1 shows a schematic diagram of a phase tracking loop 100 according to an embodiment of the application. As shown in fig. 1, the phase tracking loop 100 includes a frequency divider 110, a phase detector 120, a phase tuning module 130, and a control module 140.

The frequency divider 110 may divide a high frequency clock signal (hereinafter referred to as a first clock signal) to obtain a divided low frequency clock signal, which may be used as a carrier signal and at the same clock frequency as recovered from the reader magnetic field. The frequency of the high frequency signal input to the frequency divider 110 may be N times the frequency of the divided signal output from the frequency divider 110, where N is the division ratio of the frequency divider 110. It should be understood that in the present application both "high frequency" and "low frequency" are relative concepts describing the relative magnitude of the frequencies, but the absolute magnitude of the frequencies, i.e. the frequency range, is not limited in any sense.

The phase detector 120 may compare phases of the carrier signal and the reference clock signal output from the frequency divider 110 and output a phase indication signal. Here, the reference clock signal may be a clock signal recovered from the NFC reader, and the phase tracking loop 100 is used to track or approximate the phase of the carrier signal to the phase of the reference clock signal.

The phase tuning module 130 may adjust the phase of the first clock signal provided to the divider 110 based on the phase indication signal output by the phase detector 120 such that the phase of the carrier signal output by the divider 110 tracks/is closer to the phase of the reference clock signal.

The control module 140 may adjust the frequency of an operation clock signal (hereinafter, referred to as a second clock signal) of the phase tuning module 130 based on the phase indication signal output from the phase detector 120 and adjust the frequency division ratio of the frequency divider 110, thereby controlling the phase adjustment speed of the phase tuning module 130, which will be described in further detail below.

Fig. 2 illustrates an exemplary embodiment of the phase tracking loop 100, wherein an exemplary configuration of the phase tuning module 130 and the control module 140 is shown. Referring to fig. 2, the phase tuning module 130 may include a Digital Loop Filter (DLF) 132 and a first clock selection unit 134, and may optionally further include a coefficient control unit 136. The control module 140 may include a dynamic detection adjustment unit 142, a second clock selection unit 144, and a division ratio control unit 146.

In an embodiment, the phase detector 120 may be a binary phase detector (BBPD), and the phase indication signal output by the phase detector 120 may be a high level "1" when the phase of the carrier signal (or referred to as the divided clock signal) is advanced from the phase of the reference clock signal; when the phase of the carrier signal lags the phase of the reference clock signal, the phase indication signal output by the phase detector 120 may be a low level "-1", or vice versa. When the enable signal of the phase detector 120 is turned off (e.g., en=0, not shown), the phase detector 120 may output "0".

A Digital Loop Filter (DLF) 132 may detect the phase indication signal output by the phase detector 120 and generate a first clock selection signal to control the first clock selection unit 134 to select a corresponding clock signal from the multiphase clock signals based on the relative phase relationship of the carrier signal and the reference clock signal it indicates. For example, when the phase detector 120 indicates that the phase of the carrier signal is advanced from the phase of the reference clock signal, the digital loop filter 132 may instruct the first clock selection unit 134 to select a clock signal having a more retarded phase from among the multiphase clock signals; when the phase detector 120 indicates that the phase of the carrier signal lags the phase of the reference clock signal, the digital loop filter 132 may instruct the first clock selection unit 134 to select a clock signal having a phase that is more advanced from among the multiphase clock signals. When the phase indication signal output by the phase detector 120 indicates that the phase of the carrier signal transitions back and forth between leading and lagging phases of the reference clock signal, the clock signal selected by the first clock selection unit 134 transitions back and forth between the two signals, which is generally equivalent to a phase invariant, and the loop reaches a locked state.

Fig. 3 shows a schematic diagram of a digital loop filter 200 according to an embodiment of the invention, the digital loop filter 200 may be used for the digital loop filter 132 in the phase tracking loop 100 shown in fig. 2.

Referring to fig. 3, the digital loop filter 200 may include a proportional path 210 and an integral path 220 that receive as inputs the phase indication signal output by the phase detector 120 at a first input port In-1. The proportional path 210 and the integral path 220 may generate a first proportional signal at a first proportion "a" to the phase indication signal and a second proportional signal at a second proportion "p" to the phase indication signal, respectively. For example, the proportional path 210 may include a first register 212 in which a first proportional coefficient "a" is stored to output a first proportional signal; the integrating path 220 may include a second register 222 in which a second scaling factor "p" is stored to output a second scaling signal. For example, when the output of the phase detector 120 is "1", the first proportional signal generated by the proportional path 210 is "a", and the second proportional signal generated by the integral path 220 is "p"; when the output of the phase detector 120 changes from "1" to "-1", the first proportional signal changes from "a" to "-a" and the second proportional signal changes from "p" to "-p" by a change of "-2a" and a change of "-2 p". Similarly, when the output of the phase detector 120 changes from "-1" to "1", the first proportional signal produces a change in "+2a" from "-a" to "a", and the second proportional signal produces a change in "+2p" from "-p" to "p".

In an embodiment, the first scaling signal generated by scaling path 210 and the second scaling signal generated by integrating path 220, or the first scaling factor "a" and the second scaling factor "p", may also be adjusted. For example, the scaling path 210 may include a first scaling unit, such as a multiplier 214, that multiplies the first scaling signal using an adjustment factor to generate an adjusted first scaling signal; the integrating path 220 may include a second scaling unit, such as a multiplier 224, that multiplies the second scaling signal using an adjustment factor to generate an adjusted second scaling signal. In the embodiment shown In fig. 3, the first and second scaling units 214 and 224 may receive the same scaling factor from the second input port In-2 to perform an equal ratio adjustment on the first and second scaling signals. In other embodiments, the first and second scaling units 214 and 224 may also receive different adjustment factors to differently adjust the first and second scaling signals, or only any one of the first and second scaling units 214 and 224 may be provided to adjust one of the first and second scaling signals.

In the integrating path 220, the adjusted second proportional signal may be subjected to an integrating process in an integrator 226 to generate an integrated signal. The integrator 226 may receive the integration clock signal from the third input port In-3 to integrate the adjusted second proportional signal according to the integration clock. Fig. 4 shows a schematic diagram of the integrated signal generated by integrator 226. As shown In fig. 4, integrator 226 integrates the adjusted second scaling signal "px" or "-px" based on the integrated clock signal received at third input port In-3, where p is the second scaling factor and x is the adjustment factor. When the adjusted second proportional signal is "px", assuming that p is a positive number (p may also be a negative number), the integral signal gradually increases with the integration period and increases stepwise to "px". When the adjusted second proportional signal is "-px", the integral signal gradually decreases with the integration period and decreases stepwise to "-px". It will be appreciated that when the adjusted second proportional signal changes from "px" to "-px", the integral signal changes from increasing to decreasing; when the adjusted second proportional signal changes from "-px" to "px", the integral signal changes from decreasing to increasing. As can be appreciated from fig. 3, the rate of increase or decrease of the integrated signal is related to the second geographical factor p, the adjustment factor x and the frequency of the integrated clock signal.

With continued reference to fig. 3, the integrated signal output by integrator 226 in integrating path 220 and the first proportional signal output by proportional path 210 may be added in adder 232 to obtain a sum of the two. It will be appreciated that when the phase indication signal output by the phase detector 120 remains unchanged, the integrated signal output by the integrator 226 increases or decreases over time, and the first proportional signal output by the proportional path 210 remains unchanged over time, such that the sum value output by the adder 232 increases or decreases over time.

The sum value output by adder 232 may be subjected to a remainder operation with respect to a predetermined value M in a remainder (Mod) unit 234, thereby generating a first clock selection signal representing the remainder, which is output at an output port Out. As the integrated value output by the integrator 226 increases, the remainder value represented by the first clock selection signal output by the remainder unit 234 increases from 0 to 1, continues to increase until M-1, and then continues to increase to 0, thus cyclically changing. Alternatively, when the integrated value outputted from the integrator 226 decreases, the remainder value indicated by the first clock selection signal outputted from the remainder unit 234 decreases from 0 to M-1 and then decreases to M-2 until decreasing to 0, and so on cyclically. Here, the remainder value represented by the first clock selection signal is used as an index for the first clock selection unit 134 to select one clock signal corresponding to the index value from the M clock signals of different phases as the first clock signal supplied to the frequency divider 110.

In some embodiments, the proportional path 210 may be omitted and only the integral path 220 may be used, as may the first clock selection signal containing the index value (i.e., remainder) for selecting a corresponding clock signal from the multiphase clock signals. It will be appreciated that by providing the proportional path 210, which corresponds to introducing a reference zero in the loop, the loop is prevented from ringing and generating noise. Thus, the phase tracking loop 100 may have improved phase noise performance after introducing the proportional path 210.

As can be understood from the above description, the change speed of the index value represented by the first clock selection signal outputted from the digital loop filter 200, that is, the phase change speed of the first clock signal selected from the multiphase clock signals by the first clock selection unit 134, depends on the integration speed of the integrator 226, that is, the frequency of the integrated clock signal, the values of the first scaling factor a and the second scaling factor p, and the value of the adjustment factor x. Thus, by adjusting the frequency of the integrated clock signal and the value of the adjustment factor x, the phase adjustment speed of the phase tracking loop 100 may be adjusted, as will be described in further detail below.

Referring back to fig. 2, the first clock selection unit 134 selects one clock signal from M clock signals of different phases as the first clock signal supplied to the frequency divider 110 based on the first clock selection signal output from the digital loop filter 132. The M clock signals of different phases may have a phase difference of 360 °/M, for example, when m=12, the phases of the M clock signals may be 0 °, 30 °, 60 °, 90 °, 120 °, 150 °, 180 °, 210 °, 240 °, 270 °, 300 ° and 330 °, respectively, and of course, may have other phase values uniformly distributed in a range of 360 °.

For example, when the output of the phase detector 120 is "1", it indicates that the phase of the carrier signal (i.e., the divided signal) provided by the frequency divider 110 is advanced from the phase of the reference clock signal. At this time, as the integrated value output from the integrator 226 gradually increases, the remainder represented by the first clock selection signal output from the digital loop filter 132 gradually increases, for example, the remainder value increases by one after a predetermined integration period, so that the first clock selection unit 134 selects a clock signal with a more retarded phase from M (M is an integer greater than 1) clock signals with different phases, whereby the phase of the carrier signal supplied from the frequency divider 110 also moves backward. When the phase of the carrier signal becomes more retarded than the phase of the reference clock signal, the output of the phase detector 120 becomes "-1". At this time, the integrated value output from the integrator 226 gradually decreases with time, and the remainder represented by the first clock selection signal output from the digital loop filter 132 also gradually decreases, for example, the remainder value decreases by one after a predetermined integration period, so that the first clock selection unit 134 selects a clock signal having a more advanced phase from the M clock signals having different phases, and thus the phase of the carrier signal supplied from the frequency divider 110 also moves forward. When the output of the phase detector 120 toggles between "1" and "-1", indicating that the clock signal selected by the first clock selection unit 134 toggles between a clock signal that is phase-advanced from the reference clock signal and a clock signal that is phase-retarded from the reference clock signal, the overall equivalent is that the phase of the carrier signal is equal to or closest to the phase of the reference clock signal, and the loop reaches a locked state.

Here, the phase step between the M clock signals selected by the first clock selection unit 134 is 360 °/M, but when the frequency divider 110 performs the frequency division process, the phase step (i.e., the phase difference) between adjacent frequency-divided signals becomes 360 °/(m×n), where N is the frequency division ratio of the frequency divider 110, because the pulse width of the frequency-divided signal is N times the pulse width of the clock signal before the frequency division. For example, the signal frequency of the NFC reader is 13.56MHz, the frequency of the multiphase clock signal is 867.84MHz, and the frequency divider 110 with the frequency division ratio of n=64 may be used. Of course, other frequency division ratios may be used, such as a frequency division ratio of n=40 when the frequency of the multiphase clock signal is 542.4 MHz.

For example, when m=12, the phase step between multiphase clock signals is 30 °, and then the phase step of the divided signal becomes 0.46875 °, so that accurate phase adjustment and tracking can be achieved. When the index value represented by the first clock selection signal increases from 0 to 11, the phase of the clock signal selected by the first clock selection unit 134 is delayed by 330 °, and the phase of the divided clock signal is delayed by 5.15625 °; then the index value changes from 11 to 0, the phase of the clock signal selected by the first clock selection unit 134 continues to be delayed by 30 °, and the phase of the divided clock signal continues to be delayed by 0.46875 °. Thus, cyclically increasing the index value can cause the phase of the divided signal to be continually shifted backwards; similarly, cyclically reducing the index value may cause the phase of the divided signal to be continually shifted forward. In this way, the phase of the divided signal (i.e., the carrier signal) can be changed over a wide range.

This scheme greatly improves the accuracy of the phase adjustment, i.e., the phase tracking accuracy of the phase tracking loop 100, by employing a frequency division process. However, the speed of adjusting the phase is slow, and the step of each adjustment is 360 °/(m×n), so it may take a longer time to achieve loop lock, and the higher the phase adjustment accuracy, the longer the phase adjustment time required for a given phase difference. In order to shorten the phase lock time, embodiments of the present invention also increase the phase adjustment speed by adjusting the scaling factor and the integration frequency of the digital loop filter 132 and the division ratio of the divider 110, as will be described in further detail below.

With continued reference to fig. 2, the dynamic detection adjustment unit 142 may detect the phase indication signal generated by the phase detector 120, and generate a coefficient adjustment signal provided to the coefficient control unit 136 to control an adjustment coefficient for adjusting the first scaling coefficient a and the second scaling coefficient p of the digital loop filter 132, a second clock selection signal provided to the second clock selection unit 144 to control the frequency of the second clock signal selected by the second clock selection unit 144, and a division ratio adjustment signal to control the division ratio of the frequency divider 110, as will be described in detail below.

As previously described, the phase adjustment speed of the first clock signal selected by the first clock selection unit 134 may be changed by adjusting at least one of the first scaling factor a and the second scaling factor p in the digital loop filter 132, preferably at least the second scaling factor p (since it can change the sum value output from the adder 232 more quickly by the integration operation). Referring to fig. 2 and 3, the coefficient control unit 136 may control the magnitude of an adjustment coefficient provided to the second input port In-2 of the digital loop filter 132/200 for adjusting at least one of the first scaling coefficient a and the second scaling coefficient p In response to the coefficient adjustment signal provided by the dynamic detection adjustment unit 142. For example, when the dynamic detection adjustment unit 142 detects that the phase detector 120 indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal (the phase indication signal is "1" or "-1") and continues for a predetermined number of periods, the phase difference between the carrier signal and the reference clock signal may be considered to be large, at which time the dynamic detection adjustment unit 142 may generate a coefficient adjustment signal to instruct the coefficient control unit 136 to increase the adjustment coefficient to increase at least one of the first and second scaling coefficients a and p, thereby increasing the phase adjustment speed. This operation may be repeated until the maximum scaling factor is reached. When the dynamic detection adjustment unit 142 detects that the phase detector 120 indicates that the phase of the carrier signal transitions between being more advanced and more retarded than the phase of the reference clock signal (the phase indication signal transitions between "1" and "-1") and the transition reaches the predetermined number of times, the phase of the carrier signal may be considered to have been adjusted to be close to the phase of the reference clock signal, at which time the dynamic detection adjustment unit 142 may generate a coefficient adjustment signal to instruct the coefficient control unit 136 to decrease the adjustment coefficient, thereby decreasing at least one of the first and second scaling coefficients a and p, decreasing the phase adjustment speed until the lowest scaling coefficient is reached. It will be appreciated that increasing and decreasing the scaling factors a and p may change the phase adjustment speed, but does not affect the phase adjustment accuracy.

The second clock selection unit 144 may select one clock signal from the plurality of second clock signals as an operation clock of the digital loop filter 132, or more specifically, as an operation clock of the integrator 226 in the digital loop filter 132, based on the second clock selection signal provided by the dynamic detection adjustment unit 142. Here, the plurality of second clock signals selected by the second clock selection unit 144 may include one or more divided signals provided by the frequency divider 110. For example, divider 110 may be a multi-stage 2/3 divider comprising a cascade of a plurality of 2/3 dividing units, each stage may provide a divide-by-2 signal or a divide-by-3 signal, such that multiple stages of divider 110 may provide a plurality of divided signals of different division ratios. The frequency-divided signal provided by the frequency divider 110 as the carrier signal to the phase detector 120 may be the frequency-divided signal having the largest frequency division ratio (i.e., the lowest frequency), that is, the frequency-divided signal output by the final stage of the frequency divider 110. In an embodiment, the plurality of second clock signals selected by the second clock selection unit 144 may further include the first clock signal provided by the first clock selection unit 134, which has a higher frequency than the frequency division signal provided by the frequency divider 110. Of course, the plurality of second clock signals selected by the second clock selection unit 144 may be provided by other circuits. It is understood that the second clock selection unit 144 is not limited to the embodiments described herein. For example, the second clock selection unit 144 may also be implemented as a Voltage Controlled Oscillator (VCO) that adjusts the frequency of the output signal according to the voltage signal provided by the dynamic detection adjustment unit 142.

In an embodiment, when the phase detector 120 indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal (the phase indication signal is "1" or "-1") and is for a predetermined number of cycles (which may be the same or different from the predetermined number of cycles used for scaling), the phase difference between the carrier signal and the reference clock signal may be considered to be larger, at which time the second clock selection signal generated by the dynamic detection adjustment unit 142 may indicate that the second clock selection unit 144 selects a higher frequency clock signal, so that the integration operation in the digital loop filter 132 may be accelerated, so that the digital loop filter 132 adjusts the phase of the first clock signal selected by the first clock selection unit 134 faster. This operation may be repeated to continuously increase the frequency of the clock signal selected by the second clock selection unit 144 until the highest frequency is reached. When the phase detector 120 indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal (the phase indication signal jumps between "1" and "-1") and the jump reaches a predetermined number of times (which may be the same or different from the predetermined number of jumps for scaling factor adjustment), the phase of the carrier signal may be considered to have been adjusted around the phase of the reference clock signal, at which time the second clock selection signal generated by the dynamic detection adjustment unit 142 may instruct the second clock selection unit 144 to select a clock signal of a lower frequency, so that the integration operation in the digital loop filter 132 may be slowed down, such that the speed at which the digital loop filter 132 adjusts the phase of the first clock signal selected by the first clock selection unit 134 may be slowed down. This operation may be repeated to continuously decrease the frequency of the clock signal selected by the second clock selection unit 144 until the lowest frequency is reached. It will be appreciated that as the integration frequency increases, the power consumption of the digital loop filter 132 increases as well; as the integration frequency decreases, the power consumption of the digital loop filter 132 decreases.

Fig. 5 schematically shows the effect of the phase of the carrier signal output by the divider 110 when the division ratio N of the divider 110 is changed. Referring to fig. 5, it is assumed that the frequency division ratio n=64 of the system design, at which time the high level and the low level correspond to 32 pulses of the high-frequency clock signal before frequency division, respectively. Here, the system design frequency division ratio is a frequency division ratio such that the frequency of the carrier signal is equal to the frequency of the reference clock signal, and thus is also referred to as a base frequency division ratio. When the frequency division ratio is changed from 64 to 63, then the start of the 63-divided signal of the next period is advanced by one short/high frequency pulse from the start of the 64-divided signal, that is, 1/64 of the period of the 64-divided signal, and thus the phase is advanced by 360 °/64=5.625 °; the next cycle, the frequency divided signal 63 is 11.25 degrees earlier than the frequency divided signal 64, and so on. When the division ratio is changed from 64 to 65, then the start of the 65 divided signal of the next period is one short/high frequency pulse after the start of the 64 divided signal, that is, 1/64 of the period of the 64 divided signal, and thus the phase is retarded by 360 °/64=5.625 °; the next cycle, the divide by 65 signal is phase retarded by 11.25 from the divide by 64 signal, and so on. It will be appreciated that when the division ratio is changed from N to n±x, the value of x may be set as desired, as compared to (360×x)/N, which is a step forward or backward. Therefore, by changing the frequency division ratio, the phase of the carrier signal can be quickly adjusted, thereby increasing the phase adjustment speed.

The frequency division ratio control unit 144 may control the frequency division ratio of the frequency divider 110 based on the frequency division ratio adjustment signal provided by the dynamic detection adjustment unit 142. In an embodiment, the division ratio of divider 110 may be set to a plurality of gears, an example of which is shown in fig. 6. Fig. 6 shows a total of four gears 0-3, but more or fewer gears may be used, such as two gears, three gears, five gears, etc. Gear 0 is also referred to as a basic gear, which corresponds to a basic frequency division ratio N, i.e., a frequency division ratio that equalizes the frequency of the carrier signal and the frequency of the reference signal. When the locked state is reached, the frequency division ratio of divider 110 should be the base frequency division ratio N. The frequency division ratio of the higher gear is N+/-x, and the higher the gear is, the larger the value of x is, wherein N and x are positive integers, and N is larger than x. For example, the frequency division ratio for gear 1 may be n±1, the frequency division ratio for gear 2 may be n±2, the frequency division ratio for gear 3 may be n±3, and so on. When the phase indication signal indicates that the phase of the carrier signal is advanced from the phase of the reference clock signal, the frequency division ratio of the gear may be n+x to use a larger frequency division ratio so that the phase of the carrier signal is retarded; when the phase indication signal indicates that the phase of the carrier signal lags the phase of the reference clock signal, the frequency division ratio of the gear may be N-x to use a smaller frequency division ratio so that the phase of the carrier signal is advanced.

In an embodiment, when the phase detector 120 indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal (the phase indication signal is "1" or "-1") and continues for a predetermined number of cycles (which may be the same or different from the predetermined number of cycles used for the scaling factor adjustment and the integration clock frequency adjustment), indicating that the phase difference between the carrier signal and the reference clock signal is large, the dynamic detection adjustment unit 142 may generate the frequency division ratio adjustment signal to instruct the frequency division ratio control unit 144 to increase the frequency division gear of the frequency divider 110. This operation may be repeated to continuously increase the phase adjustment step of the carrier signal until the highest gear is reached. When the phase detector 120 indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal (the phase indication signal jumps between "1" and "-1") and the jump reaches a predetermined number of times (which may be the same or different from the predetermined number of jumps for the scaling factor adjustment and the integration clock frequency adjustment), indicating that the phase of the carrier signal has been adjusted around the phase of the reference clock signal, the dynamic detection adjustment unit 142 may generate a frequency division ratio adjustment signal to instruct the frequency division ratio control unit 144 to decrease the frequency division gear of the frequency divider 110 to decrease the phase adjustment step of the carrier signal until the base gear is reached. It will be appreciated that dynamic detection adjustment unit 142, in addition to directing frequency division ratio control unit 144 to frequency division ratio adjustment signal to increase or decrease the frequency division gear of frequency divider 110, directs frequency division ratio control unit 144 to the current carrier signal phase state, i.e., whether to advance or retard the phase of the reference clock signal, so that frequency division ratio control unit 144 can control whether the frequency division ratio of frequency divider 110 at each frequency division gear is n+x or N-x.

The following exemplifies the adjustment process of the frequency division shift stage. For example, initially, divider 110 is in a base gear (gear 0), at which time the division ratio is 64. When the dynamic detection adjustment unit 142 detects that the output of the phase detector 120 is "1" and continues for, for example, 4 cycles, it instructs the division ratio control unit 144 to increase the division ratio of the frequency divider 110 to the gear 1, at which time the division ratio of the frequency divider 110 becomes 65. When the dynamic detection adjustment unit 142 again detects that the output of the phase detector 120 is still "1" and continues for, for example, 4 cycles, it instructs the division ratio control unit 144 to increase the division ratio of the frequency divider 110 to the gear 2, at which point the division ratio of the frequency divider 110 becomes 66. This operation may be repeated until the frequency divider 110 reaches the highest gear 3, at which point the frequency division ratio of the frequency divider 110 becomes 67 and the phase adjustment step reaches the maximum. Through the above operation, the phase of the carrier signal is continuously shifted backward, and when it becomes later than the phase of the reference clock signal, the output of the phase detector 120 is changed from "1" to "-1", while the frequency divider 110 is still kept at the highest gear 3, but the frequency division ratio is changed from 67 to 61, the phase of the carrier signal is shifted forward, resulting in that the phase thereof again becomes earlier than the phase of the reference clock signal, the output of the phase detector 120 is changed from "-1" to "1", and the frequency division ratio of the frequency divider 110 is changed from 61 to 67. When the dynamic detection adjustment unit 142 detects that the output of the phase detector 120 jumps between "1" and "-1" a predetermined number of times, for example, 6 times, it instructs the division ratio control unit 144 to decrease the division gear of the frequency divider 110, changing from gear 3 to gear 2, the phase adjustment step decreases. This operation may be repeated until divider 110 reaches the base gear, the division ratio is 64, at which point the division ratio no longer affects the phase of the carrier signal, and the frequency of the carrier signal is equal to the reference clock signal.

When the division ratio N of the frequency divider 110 is adjusted, the divided signals output from the respective stages in the frequency divider 110 are affected, and thus the frequency of the integration clock signal supplied from the second clock selection unit 144 to the integrator 226 in the digital loop filter 132 is also affected. It will be appreciated that adjusting the divide ratio serves to move the phase of the carrier signal forward or backward in large steps, while the change in the integrated clock frequency of integrator 226 affects only the rate of change of the phase of the first clock signal output by first clock selection unit 134, but does not affect the direction of change (e.g., increase or decrease) of the phase of the first clock signal. Moreover, the digital loop filter 132 adjusts the carrier signal phase by a much smaller step than the carrier signal phase adjustment step caused by the change in the frequency division ratio of the frequency divider 110. Therefore, the carrier signal phase adjustment speed change due to the integral clock frequency change of the integrator 226 does not have any substantial negative effect on the overall phase adjustment process when adjusting the division ratio of the divider 110.

The phase adjustment speed control achieved by the scaling factor adjustment and the integration clock frequency adjustment of the digital loop filter 132 and the division ratio adjustment of the frequency divider 110 described above may be used in combination. In an embodiment, when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the dynamic detection adjustment unit 142 may generate the coefficient adjustment signal to increase at least one of the first scaling factor a and the second scaling factor p until the maximum scaling factor is reached; then, the second clock selection signal is generated again to increase the frequency of the second clock signal selected by the second clock selection unit 144 until the highest frequency is reached; the divide ratio adjustment signal is then generated to increase the frequency division gear of the frequency divider 110. When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit 142 may generate the division ratio adjustment signal to lower the division gear of the frequency divider 110 until the base gear is reached; then generating a second clock selection signal to decrease the frequency of the second clock signal selected by the second clock selection unit 144 until reaching the lowest frequency; the coefficient adjustment signal is then regenerated to reduce the at least one of the first scaling factor a and the second scaling factor p until the base/lowest scaling factor is reached. This process will be discussed in detail below with reference to fig. 12, which is only briefly described here.

Briefly, in the phase adjustment method described above, when the phase adjustment speed is increased, the scaling factor is first increased, then the integral clock frequency is increased, and finally the frequency division ratio is increased; when the phase adjustment speed is reduced, the frequency division ratio is reduced, then the integral clock frequency is reduced, and finally the proportionality coefficient is reduced. The inventors have appreciated that the power consumption of the phase tracking loop 100 increases when the integration clock frequency is raised, while the integration clock frequency has a lower effect on the phase adjustment speed than the frequency division ratio variation. Thus, in one embodiment, the integration clock frequency may be minimized when the divider ratio is raised to save power consumption. Specifically, when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the dynamic detection adjustment unit 142 may generate the coefficient adjustment signal to increase at least one of the first scaling factor a and the second scaling factor p until the maximum scaling factor is reached; then, the second clock selection signal is generated again to increase the frequency of the second clock signal selected by the second clock selection unit 144 until the highest frequency is reached; the frequency division ratio adjustment signal is then generated to increase the frequency division gear of the frequency divider 110, and at the first time of increasing the frequency division gear, a minimum second clock setting signal is generated to set the frequency of the second clock signal selected by the second clock selection unit 144 to the lowest frequency. When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and jumps by a predetermined number of times, the dynamic detection adjustment unit 142 may generate the split ratio adjustment signal to lower the divided gear of the frequency divider 110 until the basic gear is reached, and upon reaching the basic gear, generate a maximum second clock setting signal to set the frequency of the second clock signal selected by the second clock selection unit 144 to the highest frequency; then generating a second clock selection signal to decrease the frequency of the second clock signal selected by the second clock selection unit 144 until reaching the lowest frequency; the coefficient adjustment signal is then regenerated to reduce the at least one of the first scaling factor a and the second scaling factor p until the base/lowest scaling factor is reached. This process will be discussed in further detail below with reference to fig. 13, which is only briefly described herein. In this way, power consumption of the phase tracking loop 100 may be saved.

Fig. 7 shows a flow chart of a phase tracking method 300 according to an embodiment of the invention. The method 300 may be implemented using the phase tracking loop 100 described above with reference to fig. 1-6. Referring to fig. 7, the phase tracking method 300 may include: step 310, performing frequency division processing on the first clock signal by using the frequency divider 110 to obtain a carrier signal; step 320, comparing the phase of the carrier signal and the reference clock signal by the phase detector 120 to generate a phase indication signal; step 330, adjusting, by the phase tuning module 130, the phase of the first clock signal based on the phase indication signal such that the phase of the carrier signal tracks or is closer to the phase of the reference clock signal; and step 340 of controlling, by the control module 140, the operating clock of the phase tuning module 130, or more specifically, the frequency of the operating clock of the phase tuning module 130 and the division ratio of the frequency divider 110, based on the phase indication signal.

Fig. 8 shows a flowchart of a phase adjustment process of a first clock signal according to an embodiment of the invention, which can be applied in step 330 of the method 300 shown in fig. 7. Referring to fig. 8, in step 332, a first clock selection signal may be generated based on the phase indication signal using the digital loop filter 132. In step 334, one clock signal from among the multiphase clock signals may be selected as the first clock signal provided to the frequency divider 110 based on the first clock selection signal using the first clock selection unit 134.

Fig. 9 shows a flowchart of a process of running clock adjustment and divide ratio adjustment according to an embodiment of the invention, which is applicable in step 340 of the method 300 shown in fig. 7. Referring to fig. 9, in step 342, the phase indication signal generated by the phase detector 120 is detected by the dynamic detection adjustment unit 142, and/or the second clock selection signal and the division ratio adjustment signal are generated. Note that the second clock selection signal and the frequency division ratio adjustment signal may be generated at different times or under different circumstances based on the phase indication signal. In step 344, one of the plurality of second clock signals may be selected as an operation clock of the digital loop filter 132 in the phase tuning module 130 based on the second clock selection signal using the second clock selection unit 144. The plurality of second clock signals may include one or more divided signals provided by the frequency divider 110, or may further include a first clock signal provided by the first clock selection unit 134. In step 346, the frequency division ratio of the frequency divider 110 may be controlled based on the frequency division ratio adjustment signal using the frequency division ratio control unit 146.

Fig. 10 shows a flowchart of a process of generating the second clock selection signal and/or the division ratio adjustment signal according to an embodiment of the present invention, which is applicable to step 342 shown in fig. 9. Referring to fig. 10, in step 401, the dynamic detection adjustment unit 142 determines whether the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and jumps up to a predetermined number of times based on detecting the phase indication signal generated by the phase detector 120. If so, in step 403, the dynamic detection adjustment unit 142 generates a second clock selection signal for reducing the frequency of the second clock signal selected by the second clock selection unit 144 and/or a division ratio control signal for reducing the division level of the frequency divider 110. Steps 401 and 403 may be repeated until the second clock selection unit 144 selects the clock signal of the lowest/fundamental frequency and/or the frequency division gear of the frequency divider 110 reaches the fundamental gear.

If it is determined in step 401 that the above-mentioned transition has not occurred or the transition has not reached the predetermined number of times, the dynamic detection adjustment unit 142 may determine whether the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and for a predetermined period based on detecting the phase indication signal generated by the phase detector 120 in step 405. If so, the dynamic detection adjustment unit 142 may generate a second clock selection signal for increasing the frequency of the clock signal selected by the second clock selection unit 144 and/or a division ratio control signal for increasing the division gear of the frequency divider 110 in step 407. Steps 405 and 407 may be repeated until the second clock selection unit 144 selects the clock signal of the highest frequency and/or the frequency division gear of the frequency divider 110 reaches the highest gear.

Fig. 11 shows a flowchart of a process of generating a first clock selection signal according to an embodiment of the present invention, which is applicable to step 332 shown in fig. 8. Referring to fig. 11, at step 512, a first proportional signal may be generated using proportional path 210 that is a first proportion to the phase indication signal provided by phase detector 120; at step 514, a second proportional signal may be generated that is a second proportion of the phase indication signal using the integration path 220.

Optionally, in step 516, the first scale or the first scale signal may be adjusted by the first scale adjustment unit 214; in step 518, the second ratio or the second ratio signal may be adjusted by the second ratio adjustment unit 224. In one embodiment, the first and second ratios may be scaled equally using the same scaling factor in steps 516 and 518. As described above, the adjustment coefficient for adjusting the first scale and/or the second scale may be controlled by the coefficient control unit 136 based on the coefficient adjustment signal generated by the dynamic detection adjustment unit 142. For example, when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the coefficient adjustment signal generated by the dynamic detection adjustment unit 142 may instruct the coefficient control unit 136 to increase the adjustment coefficient to increase the first proportion and/or the second proportion, and this step may be repeatedly performed until the maximum proportion is reached when such a continuation period is detected a plurality of times. When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the coefficient adjustment signal generated by the dynamic detection adjustment unit 142 may instruct the coefficient control unit 136 to decrease the adjustment coefficient to decrease the first scale and/or the second scale, and this step may be repeated until the minimum/base scale is reached as well.

With continued reference to fig. 11, at step 520, the second proportional signal may be integrated using integrator 226 in integration path 220 to obtain an integrated signal. As described above, the second clock signal selected by the second clock selection unit 144 may be used as the operation clock of the integrator 226 to control the speed of the integration process. The first proportional signal and the integral signal may then be summed using adder 232 to obtain a sum of the two at step 522. At step 524, the sum may be summed with respect to a predetermined value using the summing unit 234 to generate a first clock select signal. The predetermined value may be equal to the number of clock signals having different phases to be selected by the first clock selection unit 134.

Fig. 12 shows a flowchart of coefficient adjustment and running clock frequency adjustment for the digital loop filter 132 and frequency division ratio adjustment for the divider 110 according to an embodiment of the present invention, in which the execution sequence of the coefficient adjustment, the running clock frequency adjustment, and the frequency division ratio adjustment is shown. Referring to fig. 12, in step 601, it may be determined whether the phase of the carrier signal hops between being more advanced and more retarded than the phase of the reference clock signal and up to a predetermined number of times based on the phase indication signal. If no transitions occur or the transitions do not reach a predetermined number of times, then a determination is made at step 603 as to whether the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period. If it is not detected that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal by a predetermined period, the scaling factor and the running clock of the digital loop filter 132 and the division ratio/division gear of the frequency divider 110 may be maintained unchanged at step 629, and then return to step 601.

If it is determined in step 603 that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, it may be determined in step 605 whether the scaling factor (first scaling factor a and/or second scaling factor p) of the digital loop filter 132 to be adjusted reaches a maximum value. If the maximum value has not been reached, the scaling factor of the digital loop filter 132 to be adjusted may be increased in step 607 and then returned to step 601.

If it is determined in step 605 that the scaling factor of the digital loop filter 132 to be adjusted has reached a maximum value, it may be determined in step 609 whether the operating clock frequency of the digital loop filter 132, or more precisely, the operating clock frequency of the integrator in the integrating path of the digital loop filter 132, i.e. the frequency of the second clock signal selected by the second clock selection unit 144, has reached a maximum value. If the maximum frequency has not been reached, the operating clock frequency of the digital loop filter, i.e. the frequency of the second clock signal selected by the second clock selection unit 144, may be increased in step 611 and then returned to step 601.

If it is determined in step 609 that the frequency of the second clock signal has reached a maximum value, it may be determined in step 613 whether the frequency division gear of the frequency divider 110 has reached the highest gear. If the highest gear has not been reached, the frequency division gear of frequency divider 110 may be increased in step 615 and then step 601 is returned. If the highest gear has been reached, the scaling factor and running clock of digital loop filter 132 and the division ratio/division gear of divider 110 may be kept unchanged in step 629, and then return to step 601.

On the other hand, if it is determined in step 601 that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and jumps up to a predetermined number of times, it may be determined in step 617 whether the frequency division gear of the frequency divider 110 is the lowest/base gear. If not the lowest gear, the frequency division gear of frequency divider 110 may be reduced in step 619 and then return to step 601.

If it is determined in step 617 that the divided gear of the frequency divider 110 is at the lowest gear, it may be determined in step 621 whether the operating clock frequency of the digital loop filter 132, i.e., the frequency of the second clock signal selected by the second clock selection unit 144, is at the lowest frequency. If not the lowest frequency, the operating clock frequency of digital loop filter 132 may be reduced in step 623 and then returned to step 601.

If it is determined in step 621 that the operating clock frequency of the digital loop filter 132 is the lowest frequency, it may be determined in step 625 whether the scaling factor (first scaling factor a and/or second scaling factor p) of the digital loop filter 132 to be adjusted is a minimum. If not, the scaling factor of the digital loop filter 132 to be adjusted may be reduced at step 627 and then returned to step 601. If the scaling factor of digital loop filter 132 to be adjusted is already at a minimum, then the scaling factor and operating clock of digital loop filter 132 and the divide ratio of divider 110 may be maintained at step 629 and then returned to step 601.

Fig. 13 shows a flowchart of coefficient adjustment and running clock frequency adjustment for the digital loop filter 132 and frequency division ratio adjustment for the divider 110 according to another embodiment of the present invention, in which the execution sequence of the coefficient adjustment, the running clock frequency adjustment, and the frequency division ratio adjustment is shown. The flow described in fig. 13 includes many of the same steps as the flow shown in fig. 12, which are denoted by the same step numbers, and only the steps different from each other will be described below.

Referring to fig. 13, when it is determined in step 605 that the scaling factor of the digital loop filter 132 has reached the maximum value, it is determined in step 608 whether the frequency division gear of the frequency divider 110 is at the lowest/base gear and the operation clock of the integrator 226 in the digital loop filter 132, that is, the second clock signal selected by the second clock selection unit 144, is at a non-highest frequency. If so, the operating clock frequency of integrator 226 in digital loop filter 132 is increased in step 611 and then returned to step 601. If not, flow proceeds to step 613.

When it is determined in step 613 that the frequency division gear of the frequency divider 110 does not reach the highest gear, the frequency division gear of the frequency divider 110 may be increased in step 614, and the operation clock of the integrator 226 in the digital loop filter 132, that is, the second clock signal selected by the second clock selection unit 144, is also placed at the lowest frequency when the frequency division gear of the frequency divider 110 is increased for the first time, that is, when the frequency division gear is increased from the base gear to the gear 1, to save the power consumption of the digital loop filter 132 during the frequency division ratio adjustment.

On the other hand, when it is determined that the transition reaches the predetermined number of times in step 601 and it is determined that the frequency division gear of the frequency divider 110 is not the base/lowest gear in step 617, the frequency division gear of the frequency divider 110 is lowered in step 618, and when the frequency division gear of the frequency divider 110 is lowered to the base/lowest gear, the operation clock of the integrator 226 in the digital loop filter 132, that is, the second clock signal selected by the second clock selection unit 144, is also placed at the highest frequency. The following steps are the same as the flow shown in fig. 12, and the description is not repeated here.

As can be understood from a comparison of the flows shown in fig. 12 and 13, the difference is mainly that in the flow shown in fig. 13, the operating clock frequency of the integrator 226 in the digital loop filter 132 is set to the lowest frequency when the frequency division ratio adjustment is applied. Thus, the flow shown in fig. 13 can save power consumption as compared with the flow shown in fig. 12.

The embodiments of the phase tracking loop and the phase tracking method of the present invention have been described above with reference to the accompanying drawings, and it can be seen that the phase tracking loop and the phase tracking method of the present invention can achieve fast and high-precision phase locking within a large phase difference range, and have improved phase noise performance, and also have saved power consumption. For example, taking the case where the frequency division ratio n=64 and the multiphase clock signal have a 30 ° phase difference (m=12), the conventional phase adjustment step is 0.46875 °, and if there is a 180 ° phase difference between the carrier signal and the reference clock signal, the phase lock time is typically around 100 μs. If there is a certain frequency deviation between the carrier signal and the reference clock signal, the phase lock time is above 100 mus. By using the dynamic detection and adjustment technology of the invention, the locking time can be greatly accelerated by improving the proportional coefficient and the integral frequency in the digital loop filter in the initial phase of phase tracking. While near lock, the scaling factor and integration frequency in the digital loop filter can be reduced to the minimum factor and minimum frequency, making lock more stable. The overall locking and settling time can be up to within 10 mus.

Fig. 14 shows a schematic diagram of an electronic device 700 according to an embodiment of the application. The electronic device 700 may include a phase tracking loop 720 in accordance with an embodiment of the present application. For example, the electronic device 700 may have an NFC module 710 that may operate in a card emulation mode. NFC module 710 may include a phase tracking loop 720 to track the phase of the signal of the NFC reader. Examples of such an electronic device 700 include, but are not limited to, a cell phone, tablet, portable personal digital assistant, wearable electronic device, and the like.

The basic principles of the present application have been described above in connection with specific embodiments, however, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are merely examples and not intended to be limiting, and these advantages, benefits, effects, etc. are not to be considered as essential to the various embodiments of the present application. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, as the application is not necessarily limited to practice with the above described specific details.

The block diagrams of the devices, apparatuses, devices, systems referred to in the present application are only illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be made in the manner shown in the block diagrams. As will be appreciated by one of skill in the art, the devices, apparatuses, devices, systems may be connected, arranged, configured in any manner. Words such as "including," "comprising," "having," and the like are words of openness and mean "including but not limited to," and are used interchangeably therewith. The terms "or" and "as used herein refer to and are used interchangeably with the term" and/or "unless the context clearly indicates otherwise. The term "such as" as used herein refers to, and is used interchangeably with, the phrase "such as, but not limited to.

It is also noted that in the apparatus, devices and methods of the present application, the components or steps may be disassembled and/or assembled. Such decomposition and/or recombination should be considered as equivalent aspects of the present application.

The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the application. Thus, the present application is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit embodiments of the application to the form disclosed herein. Although a number of example aspects and embodiments have been discussed above, a person of ordinary skill in the art will recognize certain variations, modifications, alterations, additions, and subcombinations thereof.

Claims

1. A phase tracking loop, comprising:

the frequency divider is used for carrying out frequency division processing on the first clock signal to obtain a carrier signal;

A phase detector for comparing the phases of the carrier signal and a reference clock signal to generate a phase indication signal;

a phase tuning module for adjusting the phase of the first clock signal based on the phase indication signal such that the phase of the carrier signal is closer to the phase of the reference clock signal; and

and the control module is used for controlling the running clock of the phase tuning module and the frequency division ratio of the frequency divider based on the phase indication signal.

2. The phase tracking loop of claim 1, wherein the phase detector is a binary phase detector, the phase indication signal output by the binary phase detector indicating that the phase of the carrier signal is either advanced or retarded relative to the phase of the reference clock signal.

3. The phase tracking loop of claim 1, wherein the phase tuning module comprises:

a digital loop filter for generating a first clock selection signal based on the phase indication signal; and

and the first clock selection unit is used for selecting one clock signal from multiphase clock signals based on the first clock selection signal as the first clock signal.

4. A phase tracking loop as claimed in claim 3, wherein the control module comprises:

A dynamic detection adjustment unit for detecting the phase indication signal generated by the phase detector and generating a second clock selection signal and a frequency division ratio adjustment signal;

a second clock selection unit configured to select one of a plurality of second clock signals as an operation clock of the digital loop filter based on the second clock selection signal; and

and the frequency dividing ratio control unit is used for controlling the frequency dividing ratio of the frequency divider based on the frequency dividing ratio adjustment signal.

5. The phase tracking loop of claim 4 wherein the plurality of second clock signals includes one or more divided signals provided by the divider.

6. The phase tracking loop of claim 5, wherein the plurality of second clock signals further includes the first clock signal provided by the first clock selection unit.

7. The phase tracking loop of claim 4, wherein when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the second clock selection signal generated by the dynamic detection adjustment unit indicates that the second clock selection unit selects one clock signal of higher frequency than the currently selected clock signal from the plurality of second clock signals, the frequency division ratio adjustment signal generated by the dynamic detection adjustment unit indicates that the frequency division ratio control unit increases the frequency division gear of the frequency divider,

When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the second clock selection signal generated by the dynamic detection adjustment unit instructs the second clock selection unit to select a frequency division signal of a lower frequency than the currently selected clock signal from the plurality of second clock signals, the frequency division ratio adjustment signal generated by the dynamic detection adjustment unit instructs the frequency division ratio control unit to lower the frequency division gear of the frequency divider,

the frequency divider has a basic gear having a basic frequency division ratio N, and at least one higher gear having a higher frequency division ratio n+x or a lower frequency division ratio N-x, N being a preset positive integer, x being a smaller positive integer than N and the higher the gear, the larger the value of x, the higher gear having the higher frequency division ratio n+x when the phase indication signal indicates that the phase of the carrier signal is more advanced than the phase of the reference clock signal, and the lower frequency division ratio N-x when the phase indication signal indicates that the phase of the carrier signal is more retarded than the phase of the reference clock signal.

8. The phase tracking loop of claim 7 wherein the carrier signal is a divided signal having a lowest frequency of a plurality of divided signals provided by the divider, the base division ratio N being such that the frequency of the carrier signal is equal to the frequency of the reference clock signal.

9. The phase tracking loop of claim 7 wherein said multiphase clock signal comprises M clock signals of different phases, M being an integer greater than one,

the first clock selection signal generated by the digital loop filter represents one of M index values to instruct the first clock selection unit to select a corresponding clock signal from among the M clock signals of different phases as the first clock signal.

10. The phase tracking loop of claim 7, wherein the first clock selection signal generated by the digital loop filter instructs the first clock selection unit to select a clock signal from the multiphase clock signals that is more phase retarded than a currently selected clock signal when the phase indication signal generated by the phase detector indicates that the phase of the carrier signal is advanced than the phase of the reference clock signal for a predetermined period,

When the phase indication signal generated by the phase detector indicates that the phase of the carrier signal lags behind the phase of the reference clock signal and lasts for a predetermined period, the first clock selection signal generated by the digital loop filter indicates that the first clock selection unit selects one clock signal from the multiphase clock signals, which is more advanced than the currently selected clock signal.

11. The phase tracking loop of claim 7, wherein the digital loop filter comprises:

a proportional path for generating a first proportional signal that is a first proportion to the phase indication signal;

an integrating path for generating a second proportional signal at a second ratio to the phase indication signal, and integrating the second proportional signal using an integrator to generate an integrated signal;

an adder for adding the first proportional signal and the integral signal to output a sum of the two; and

and a remainder unit for performing a remainder operation on the sum value received from the adder with respect to a predetermined value to generate the first clock selection signal representing a remainder.

12. The phase tracking loop according to claim 11, wherein the second clock signal selected by the second clock selection unit is used as an operation clock of an integrator in the integration path, the predetermined value being equal to the number of clock signals having different phases included in the multiphase clock signal.

13. The phase tracking loop of claim 11, wherein the digital loop filter further comprises at least one of:

a first proportion adjusting unit provided in the proportion path for adjusting the first proportion; and

and a second proportion adjusting unit arranged in the integrating path and used for adjusting the second proportion.

14. The phase tracking loop of claim 13, wherein the first and second scaling units use the same scaling factor to perform an equal scaling of the first and second scales.

15. The phase tracking loop of claim 13, further comprising:

a coefficient control unit configured to control an adjustment coefficient that adjusts at least one of the first ratio and the second ratio based on a coefficient adjustment signal generated by the dynamic detection adjustment unit,

wherein when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the coefficient adjustment signal generated by the dynamic detection adjustment unit instructs the coefficient control unit to increase the adjustment coefficient to increase the at least one of the first ratio and the second ratio,

When the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the coefficient adjustment signal generated by the dynamic detection adjustment unit instructs the coefficient control unit to decrease the adjustment coefficient to decrease the at least one of the first ratio and the second ratio.

16. The phase tracking loop according to claim 15, wherein when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the dynamic detection adjustment unit generates the coefficient adjustment signal to increase the at least one of the first ratio and the second ratio until a maximum ratio is reached, then generates the second clock selection signal to increase the frequency of the second clock signal selected by the second clock selection unit until a maximum frequency is reached, then generates the division ratio adjustment signal to increase the division gear of the frequency divider,

when the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit first generates the frequency division ratio adjustment signal to decrease the frequency division shift of the frequency divider until a basic shift is reached, then generates the second clock selection signal to decrease the frequency of the second clock signal selected by the second clock selection unit until a minimum frequency is reached, and then generates the coefficient adjustment signal to decrease the at least one of the first ratio and the second ratio.

17. The phase tracking loop according to claim 15, wherein when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the dynamic detection adjustment unit generates the coefficient adjustment signal to increase the at least one of the first ratio and the second ratio until a maximum ratio is reached, then generates the second clock selection signal to increase the frequency of the second clock signal selected by the second clock selection unit until a maximum frequency is reached, then generates a minimum second clock setting signal to set the frequency of the second clock signal selected by the second clock selection unit to a minimum frequency, and generates the division ratio adjustment signal to increase the division gear of the frequency divider,

when the phase indication signal indicates that the phase of the carrier signal jumps between more advanced and more retarded than the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit generates the frequency division ratio adjustment signal to decrease the frequency division shift range of the frequency divider until a base shift range is reached, and generates a maximum second clock setting signal to set the frequency of the second clock signal selected by the second clock selection unit to the highest frequency when the frequency division shift range reaches the base shift range, and then generates the second clock selection signal to decrease the frequency of the second clock signal selected by the second clock selection unit until the lowest frequency is reached, and then generates the coefficient adjustment signal to decrease the at least one of the first proportion and the second proportion.

18. A phase tracking method, comprising:

the frequency divider performs frequency division processing on the first clock signal to obtain a carrier signal;

a phase detector compares the phases of the carrier signal and a reference clock signal to generate a phase indication signal;

a phase tuning module adjusts a phase of the first clock signal based on the phase indication signal such that the phase of the carrier signal is closer to a phase of the reference clock signal; and

a control module controls an operating clock of the phase tuning module and a division ratio of the frequency divider based on the phase indication signal.

19. The method of claim 18, wherein the phase tuning module adjusting the phase of the first clock signal based on the phase indication signal comprises:

generating a first clock selection signal based on the phase indication signal with a digital loop filter; and

a first clock selection unit is used for selecting one clock signal from multiphase clock signals based on the first clock selection signal as the first clock signal.

20. The method of claim 19, wherein controlling the operating clock of the phase tuning module and the division ratio of the divider based on the phase indication signal comprises:

Detecting the phase indication signal generated by the phase detector by using a dynamic detection adjustment unit, and generating a second clock selection signal and a frequency division ratio adjustment signal;

selecting one of a plurality of second clock signals as an operation clock of the digital loop filter based on the second clock selection signal by a second clock selection unit; and

the frequency dividing ratio of the frequency divider is controlled based on the frequency dividing ratio adjustment signal by a frequency dividing ratio control unit.

21. The method of claim 20, wherein the plurality of second clock signals comprises one or more divided signals provided by the divider.

22. The method of claim 21, wherein the plurality of second clock signals further comprises the first clock signal provided by the first clock selection unit.

23. The method of claim 20, wherein when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the second clock selection signal generated by the dynamic detection adjustment unit indicates that the second clock selection unit selects one clock signal of a higher frequency than the currently selected clock signal from the plurality of second clock signals, the frequency division ratio adjustment signal generated by the dynamic detection adjustment unit indicates that the frequency division ratio control unit increases the frequency division gear of the frequency divider,

24. The method of claim 23, wherein the first clock selection signal generated by the digital loop filter instructs the first clock selection unit to select a clock signal having a phase more retarded than a currently selected clock signal from the multiphase clock signals when the phase instruction signal instructs the carrier signal to be in advance of the phase of the reference clock signal for a predetermined period,

when the phase indication signal indicates that the phase of the carrier signal lags behind the phase of the reference clock signal and lasts for a predetermined period, the first clock selection signal generated by the digital loop filter instructs the first clock selection unit to select one clock signal from the multiphase clock signals, which is more advanced than the currently selected clock signal.

25. The method of claim 23, wherein generating a first clock selection signal based on the phase indication signal with a digital loop filter comprises:

generating a first proportional signal in a first proportion to the phase indication signal using a proportional path;

generating a second proportional signal at a second proportion to the phase indication signal with an integrating path, and performing an integrating process on the second proportional signal using an integrator provided in the integrating path to generate an integrated signal;

Adding the first proportional signal and the integral signal by an adder to output a sum of the first proportional signal and the integral signal; and

and performing a remainder operation on the sum value with respect to a predetermined value by using a remainder unit to generate the first clock selection signal representing a remainder.

26. The method of claim 25, wherein the second clock signal selected by the second clock selection unit is used as an operation clock of an integrator in the integration path to control a speed of integrating the second proportional signal, the predetermined value being equal to the number of clock signals having different phases included in the multi-phase clock signal.

27. The method of claim 25, wherein generating a first clock selection signal based on the phase indication signal with a digital loop filter further comprises at least one of:

adjusting the first ratio with a first ratio adjusting unit provided in the ratio path; and

the second ratio is adjusted using a second ratio adjustment unit disposed in the integration path.

28. The method of claim 27, wherein the first and second scaling units use the same scaling factor to perform an equal scaling of the first and second scales.

29. The method of claim 27, further comprising:

controlling an adjustment coefficient for adjusting at least one of the first ratio and the second ratio based on the coefficient adjustment signal generated by the dynamic detection adjustment unit with a coefficient control unit,

30. The method of claim 29, wherein when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the dynamic detection adjustment unit generates the coefficient adjustment signal to increase the at least one of the first ratio and the second ratio until a maximum ratio is reached, then generates the second clock selection signal to increase the frequency of the second clock signal selected by the second clock selection unit until a maximum frequency is reached, then generates the division ratio adjustment signal to increase a division gear of the frequency divider,

31. The method of claim 29, wherein when the phase indication signal indicates that the phase of the carrier signal is more advanced or more retarded than the phase of the reference clock signal and continues for a predetermined period, the dynamic detection adjustment unit generates the coefficient adjustment signal to increase the at least one of the first ratio and the second ratio until reaching a maximum ratio, then generates the second clock selection signal to increase the frequency of the second clock signal selected by the second clock selection unit until reaching a maximum frequency, then generates a minimum second clock setting signal to set the frequency of the second clock signal selected by the second clock selection unit to a minimum frequency, and generates the division ratio adjustment signal to increase the division gear of the frequency divider,

32. An electronic device comprising the phase tracking loop of any one of claims 1-17.