CN106209093A - A kind of digital fractional frequency-division phase-locked loop structure - Google Patents

Abstract

The present invention provides a kind of digital fractional frequency-division phase-locked loop structure, including: time to digital converter device TDC, digital filter DLF, digital controlled oscillator DCO, numerical control phase interpolator DPI, ∑ Delta modulator SDM, integer frequency divider DIV and forward feedback correction module.By using numerical control phase interpolator DPI to complete the digital controlled signal conversion to phase information, and use the elimination of forward feedback correction means by DPI introduce non-linear.The problems such as this structure not only reduces the complexity of circuit design, solves power consumption in existing structure high simultaneously, design complexity, noise difference.It is applicable to high-performance, low-consumption wireless communication field.

Description

An all-digital fractional frequency-division phase-locked loop structure

technical field

The invention relates to an all-digital fractional frequency-division phase-locked loop structure, which belongs to the field of radio frequency integrated circuits.

Background technique

In recent years, wireless communication technology has developed rapidly, and with the development of integrated circuits, wireless communication has spread to every corner of life. In a wireless communication system, a frequency synthesizer is the core module in a radio frequency system, which generates a stable local oscillator signal (LO) for use by receivers and transmitters. The frequency synthesizer based on the phase-locked loop (PLL) structure has received continuous attention due to its simple structure, stable performance, low implementation cost, and easy integration with large-scale analog and digital circuits, and has been widely used in modern communications. Applications.

Generally, phase locked loops can be classified into integer phase locked loops (integer-N PLL) and fractional phase locked loops (fractional-N PLL) according to frequency division ratio types. Because the frequency division ratio of the latter can be set flexibly, its application is more extensive. A typical structural block diagram of a fractional frequency division phase-locked loop is shown in Figure 1. Basically including phase detector (PFD), charge pump (CP), loop filter (LPF), voltage controlled oscillator (VCO), frequency divider (DIV) and ΣΔ modulator (SDM). The ΣΔ modulator is the core module to realize the fractional frequency division. Its function is to modulate the fractional frequency division value into a variable integer frequency division value, so that the average frequency division ratio is a decimal, thereby indirectly realizing the "fractional" frequency division. Compared with the integer phase-locked loop, the fractional frequency division phase-locked loop breaks the constraint relationship between the frequency resolution and the phase-locked loop bandwidth, and it has great flexibility, and can achieve any frequency by changing the frequency division ratio, Therefore, the fractional frequency phase-locked loop occupies a dominant position in modern wireless communication applications.

With the development of integrated circuit technology, the feature size of semiconductor devices is continuously reduced. When the CMOS process enters the deep sub-micron range, in many cases, the transistor with the shortest channel cannot be used in the analog circuit, so that the analog circuit cannot be scaled down with the process. However, advanced technology has brought increasing advantages to digital circuit design. Compared with traditional analog circuits, digital circuits have the advantages of low power consumption, low cost, high speed, and easy large-scale integration. Therefore, industry and academia gradually turn their attention to digital circuits. Because most of the circuits are implemented with digital circuits, and the external control interfaces are all digital signals. Compared with traditional analog structures, all-digital phase-locked loops (ADPLLs) have lower power consumption, lower cost, and are easier to integrate.

After the concepts of the Internet of Things, cloud computing, and big data were proposed, the performance requirements for wireless communication are getting higher and higher, and the requirements for low cost and high compatibility are also becoming stronger. Therefore, with the continuous improvement of performance requirements, the contradictions among the phase noise, power consumption and area of the phase-locked loop are increasingly intensified. Therefore, some new structures have emerged to compromise various contradictions.

One of the most intuitive structures is an all-digital fractional frequency-division phase-locked loop based on a Time-to-Digital Converter (TDC) structure, and the structural block diagram is shown in Figure 2. Compared with the traditional analog loop, the digital loop uses a time-to-digital converter (TDC) to replace the phase detector/charge pump, a digital filter (DLF) to replace the analog filter (LPF), and a digitally controlled oscillator (DCO) to replace A voltage controlled oscillator (VCO). Usually, in order to improve the noise performance of the digital phase-locked loop, both TDC and DCO need to achieve higher resolution. However, the improvement of the resolution of the traditional TDC based on the delay chain structure is limited by the influence of inverter delay and process mismatch, and it is difficult to achieve high precision. Therefore, many documents have proposed improved TDC structures. However, in this loop structure, the high-precision TDC must meet the total coverage of more than one DCO cycle at the same time, so it inevitably consumes a lot of chip area and power consumption.

In order to reduce the area and power consumption of the TDC, a loop architecture based on the switch phase detector BB-PD (Bang-Bang Phase Detector) structure is proposed, as shown in Figure 3. Since BB-PD exhibits linear characteristics in a small range under the action of Gaussian noise, it can be used for linear locking, otherwise the loop will be in an unstable state and the noise performance will drop sharply. Therefore, in this loop structure, it is necessary to insert a phase delay unit array before the BB-PD. Due to the limited linear range of the BB-PD, the phase delay unit array is required to have a relatively small phase resolution, which leads to an increase in the array scale and consumes a large amount of chip area. Secondly, the delay time fluctuates greatly with the process, and the total length of the delay unit needs to be strictly consistent with the DCO period, so an additional complex correction loop is usually required to calibrate the delay time of the delay chain. This greatly increases the complexity of the loop design, and non-ideal factors such as process, layout mismatch, and device mismatch inside the delay unit will introduce serious nonlinearity, which will deteriorate the loop performance when the loop bandwidth is large. phase noise performance, while also adding additional area and power consumption.

The above structure, whether it is based on TDC or BB-PD loop structure, when meeting the requirements of low phase noise, causes the chip to consume a large amount of area and power consumption, which cannot meet the requirements of modern wireless communication systems. On the one hand, it is very difficult to realize a time-to-digital converter with high precision, high linearity and wide coverage, and the circuit structure is complex. On the other hand, adding a complex feedback correction loop to the phase-locked loop, this multi-loop structure will seriously affect the stability of the system.

Contents of the invention

In view of the problems referred to above, the purpose of the present invention is to provide a kind of all-digital fractional frequency-division phase-locked loop structure, by using digital control phase interpolator DPI to complete the conversion of digital control signal to phase information, and adopting feed-forward correction means to eliminate the distortion introduced by DPI. non-linear. This structure not only reduces the complexity of circuit design, but also solves the problems of high power consumption, complex design, poor noise and the like in the existing structure. It is applicable to the field of high-performance, low-power wireless communication.

In order to achieve the above object, the concrete technical scheme that the present invention takes is:

An all-digital fractional frequency-division phase-locked loop structure, including:

Time-to-digital converter TDC, digital filter DLF, numerically controlled oscillator DCO, numerically controlled phase interpolator DPI, ΣΔ modulator SDM, integer frequency divider DIV and feedforward correction module;

The TDC is used to detect the phase difference between the input signals and output it as a digital signal, and its input terminals input a reference clock and a feedback clock respectively;

The DLF is used to filter the digital signal output by the TDC;

The filtered digital signal is input to the DCO and controls the switched capacitor array in the DCO to adjust the oscillation frequency, and output a group of multi-phase clock signals with the same period;

The DPI is used to take the multi-phase clock signal output by the DCO as an input signal, and output the required phase signal according to the digital control signal;

The DIV is used in combination with the DPI to realize fractional frequency division;

The SDM is used to dynamically adjust the digital control signal of the DPI with a fractional frequency division ratio as an input;

The DIV is used to divide the frequency of the phase signal output by the DPI, and finally generate a feedback clock signal and input it to the TDC;

The feed-forward correction module is used to evaluate the non-linearity of DPI under different control codes, and subtract the non-linear error introduced by DPI from the output of the TDC to output to the loop filter, thereby eliminating the non-linear influence of DPI .

Further, the TDC samples the reference clock according to the rising edge of the feedback clock, and performs phase comparison on the sampled data, and then obtains the phase difference between the feedback clock signal and the reference clock signal, and converts it into a multi-bit Digital signal output.

Further, the DLF filters out high-frequency components of the digital signal output by the TDC and outputs a set of digital control signals to control the frequency and phase of the DCO.

Further, the DPI weights two clock signals with different phases, and then outputs a clock signal with a required phase.

Further, the high bit of the digital control signal of the DPI is used to realize quadrant selection, and the low bit is used to realize weight ratio.

First, two adjacent phases are selected from the input multi-phase clock signal, and weighted summation is performed according to the low-order control code of the control signal to generate a new clock signal between the two phases.

If the frequency division ratio is set to 4+1/2 ⁿ , the phase interpolator will insert a 1/2 ⁿ phase in the four input cycles, so that the output of the phase interpolator passes through a divide-by-4 circuit, The desired fractional frequency division ratio can be obtained. In the next four cycles, two 1/2 ⁿ phases are inserted, and so on, thus realizing fractional frequency division.

Further, the SDM dynamically adjusts the digital control signal of the DPI by generating a series of random number signals.

Further, the input of the DPI is an quadrature differential eight-phase clock, which are respectively 0°, 45°, 90°, 135°, 180°, 225°, 270° and 315° phases; 8-bit Digital control signal, the upper 3 bits are used to control the switching tube to select two phases to determine the quadrant of the output phase, and the lower 5 bits are used to determine the weight of the tail current.

Further, the TDC adopts a structure based on a Vernier delay line.

By adopting the above-mentioned technical scheme, the novel fractional frequency-division phase-locked loop structure based on a time-to-digital converter (TDC) and a digitally controlled phase interpolator (DPI) proposed by the present invention inputs the feedback clock signal to the time-to-digital converter as a sampling signal, Sample the reference clock signal according to its rising edge, output the corresponding digital signal, and subtract it from the output of the feedforward correction module, then transmit it to the digital filter to filter out its high-frequency component, and then input it to the input of the numerically controlled oscillator end. The frequency of the local oscillator signal of the oscillator changes with the change of the digital control signal. The multi-phase clock signal output by the oscillator is used as the input of the phase interpolator, and the required phase value is interpolated according to the digital control signal. After integer frequency division, it is fed back to the time-to-digital converter for phase comparison, and finally reaches the locked state.

Compared with the existing loop structure, the present invention has the following advantages:

1) The present invention adopts the structure combining TDC and DPI. Due to the DPI phase interpolation, the coverage of TDC can be greatly reduced, and only need to cover the phase accuracy of several DPIs, which is far less than one DCO cycle. The required effective length can be greatly reduced, thereby effectively reducing the area and power consumption of the TDC. At the same time, the TDC structure is adopted in the present invention, so the requirement on DPI accuracy is relaxed, and the circuit design is simplified to a great extent. In fact, as long as the sum of the bit widths of DPI and TDC satisfies the total bit width requirement. Therefore, a simple circuit structure can be used to realize a high-precision TDC, which greatly reduces the complexity of circuit design.

2) The DPI structure is adopted in the present invention, because the DPI has an accurate 360° phase due to its phase periodicity, so there is no need to use additional complicated correction techniques to calibrate the total phase length. The design difficulty of the circuit is greatly reduced. And by introducing an error evaluation unit before the loop filter on the forward path, the influence of DPI nonlinearity is eliminated, thereby improving the phase noise performance of the loop.

3) In the present invention, it is proposed to use the technique of combining DPI and ΔΣ modulator to realize the fractional part of the frequency division ratio. A random dynamic frequency division ratio is generated in the loop through the noise shaping function of the ΔΣ modulator, thereby eliminating fractional frequency division spurs in the system.

Description of drawings

FIG. 1 is a schematic diagram of the architecture of a traditional analog fractional frequency division phase-locked loop.

FIG. 2 is a schematic diagram of the architecture of the all-digital fractional frequency-division phase-locked loop based on the time-to-digital converter.

Fig. 3 is a schematic diagram of the structure of the all-digital fractional frequency division phase-locked loop based on the switch phase detector.

Fig. 4 is a schematic diagram of the principle of fractional frequency division described in an embodiment of the present invention.

FIG. 5 is a schematic structural diagram of an all-digital fractional frequency-division phase-locked loop described in an embodiment of the present invention.

FIG. 6 is a schematic structural diagram of a high-precision digitally controlled oscillator described in an embodiment of the present invention.

FIG. 7 is a schematic structural diagram of a digitally controlled phase interpolator described in an embodiment of the present invention.

FIG. 8 is a schematic structural diagram of a time-to-digital converter based on a Vernier delay line described in an embodiment of the present invention.

detailed description

Below by specific embodiment, and cooperate with accompanying drawing, the present invention will be further described:

As shown in FIG. 5 , an all-digital fractional frequency-division phase-locked loop structure provided for an embodiment of the present invention. It includes:

Time-to-digital converter TDC, digital filter DLF, numerically controlled oscillator DCO, numerically controlled phase interpolator DPI, ΣΔ modulator SDM, integer frequency divider DIV and feedforward correction module;

The TDC is used to convert the phase and output it as a digital signal, and its input terminals input the reference clock and the feedback clock respectively; sample the reference clock according to the rising edge of the feedback clock, and compare the phases of the sampled data to obtain the feedback clock The phase difference between the signal and the reference clock signal, and convert it into a multi-bit digital signal output.

The DLF is used to filter the digital signal output by the TDC; filter out the high frequency components of the digital signal output by the TDC and output a set of digital control signals to control the frequency and phase of the DCO.

The filtered digital signal is input to the DCO and controls the switched capacitor array in the DCO to adjust the oscillation frequency, and output a group of multi-phase clock signals with the same period;

The DPI is used to take the multi-phase clock signal output by the DCO as an input signal, weight two clock signals of different phases, and then output a clock signal of a required phase. The high bit of the control multiphase clock signal is used to realize the quadrant selection, and the low bit is used to realize the weight ratio. First, two adjacent phases are selected from the input multi-phase clock signal, and summed according to a certain weight ratio to generate a new clock signal between the two phases.

The DIV is used to combine with the DPI to realize the fractional frequency division; in combination with that shown in Figure 4, the principle of the fractional frequency division is explained as follows: Taking the frequency division ratio as 4+1/2 ^{n as an example} , the phase interpolator A phase of 1/2 ⁿ will be inserted in the four input cycles, so that the output of the phase interpolator passes through a divide-by-4 circuit to obtain the required fractional frequency division ratio. In the next four cycles, two 1/2 ⁿ phases are inserted, and so on, thus realizing fractional frequency division.

The SDM is used to generate a series of random number signals to dynamically adjust the digital control signal of the DPI with a fractional frequency division ratio as input;

The DIV is used to divide the frequency of the phase signal output by the DPI, and finally generate a feedback clock signal and input it to the TDC;

The feed-forward correction module is used to evaluate the non-linearity of DPI under different control codes, and subtract this part of the error from the output end of the TDC to output to the loop filter, so as to eliminate the non-linear influence of DPI.

In addition, in this embodiment, in order to improve the precision of the digitally controlled oscillator, an inductor-tapped digitally controlled oscillator DCO is used, the structure of which is shown in FIG. 6 . By tapping the inductor and adding a fine-tuning capacitor array at the tap, the frequency accuracy brought about by the same capacitance value change can be improved by several orders of magnitude, thereby achieving low phase noise performance.

In this embodiment, the digitally controlled phase interpolator adopts a typical structure based on current mode, and the circuit frame diagram is shown in Figure 7, and its input is an orthogonal differential eight-phase clock, respectively 0°, 45°, 90°, 135°, 180°, 225°, 270° and 315° phase.

In this example, an 8-bit digital control signal is used. The upper 3 bits are used to control the switching tube to select two phases to determine the quadrant of the output phase, and the lower 5 bits are used to determine the weight of the tail current, so 360° can be realized /256 = 1.40625° phase resolution. For example, when outputting a 130° phase, first select two branches of 90° and 135°. Then, by controlling the weight of the tail current, the ratio of 90° and 135° is adjusted to achieve a 130° phase output. Therefore, the entire phase interpolator can realize the output of the entire 360° phase.

In this embodiment, the ΣΔ modulator (SDM) adopts the MASH1-1-1 structure, which connects three first-order DSMs in series, has no complex inter-stage feedback loop, has a simple structure, and has excellent stability.

In order to improve the TDC resolution, the present invention adopts a structure based on a Vernier delay line, and its circuit structure diagram is shown in FIG. 8 . The structure is composed of two delay chains, and the delay time of each chain is different, respectively td1 and td2, so its resolution is: Δt _res =td1-td ₂ . Due to the presence of the phase interpolator, the TDC needs to cover only 8 DPI phase resolutions. For example, the DCO outputs a differential clock signal with a frequency of 2G, and first passes through a divide-by-four circuit to generate an 8-phase signal of quadrature differential as the input of the DPI. At this time, the precision that the DPI can achieve is 7.8125ps. After the fractional part of the frequency division ratio is quantized by the ΣΔ modulator (SDM), the maximum variation range is 8. Therefore, in the structure of the present invention, the coverage of the TDC only needs to satisfy: 8*7.8125=62.5ps, which is far Less than one DCO cycle, 500ps. If the resolution of the TDC is 2 ps, the present invention only needs to use a 5-bit delay chain to meet the requirements.

The feedforward correction module described in this embodiment can segmentally evaluate the residual mismatch under the high-order control code of the phase interpolator and the mismatch under the low-order control code through a digital algorithm, which can greatly reduce the number of required registers , to reduce the chip area.

The structure of the digital filter in this embodiment is simple, and a second-order finite-length unit impulse response filter (FIR) can be used. The digital filter includes two branches, one path realizes first-order integration, and the other parallel path realizes low-pass filtering. Among them, the parameters of the filter directly affect the loop bandwidth, so the bandwidth of the loop can be adjusted by changing its parameters.

In combination with the structures described in the above embodiments, the present invention proposes a fractional frequency-division phase-locked loop structure based on the combination of a time-to-digital converter (TDC) and a digitally controlled phase interpolator (DPI). The complex phase calibration circuit in the traditional structure is not needed, and the area and power consumption of the chip are greatly reduced. And the digital control part of the whole circuit is also very simple, and each module can be realized based on digital code, which greatly simplifies the circuit structure.

The above embodiments are only used to illustrate the technical solution of the present invention and not to limit it. Those of ordinary skill in the art can modify or equivalently replace the technical solution of the present invention without departing from the spirit and scope of the present invention. The protection of Fangfang Win is subject to the claims.

Claims (8)

1. A kind of all-digital fractional frequency division phase-locked loop structure, it is characterized in that, comprises: Time-to-digital converter TDC, digital filter DLF, numerically controlled oscillator DCO, numerically controlled phase interpolator DPI, ΣΔ modulator SDM, integer frequency divider DIV and feedforward correction module; The TDC is used to detect the phase difference between the input signals and output it as a digital signal, and its input terminals input a reference clock and a feedback clock respectively; The DLF is used to filter the digital signal output by the TDC; The filtered digital signal is input to the DCO and controls the switched capacitor array in the DCO to adjust the oscillation frequency, and output a group of multi-phase clock signals with the same period; The DPI is used to take the multi-phase clock signal output by the DCO as an input signal, and output the required phase signal according to the digital control signal; The DIV is used in combination with the DPI to realize fractional frequency division; The SDM is used to dynamically adjust the digital control signal of the DPI with a fractional frequency division ratio as an input; The DIV is used to divide the frequency of the phase signal output by the DPI, and finally generate a feedback clock signal and input it to the TDC; The feedforward correction module is used to evaluate the non-linearity of DPI under different control codes, and subtract the non-linear error introduced by DPI from the output end of the TDC to output to the loop filter. 2. The all-digital fractional frequency division phase-locked loop structure as claimed in claim 1, wherein said TDC samples the reference clock according to the rising edge of the feedback clock, and compares the phases of the sampled data to obtain feedback The phase difference between the clock signal and the reference clock signal is converted into a multi-bit digital signal output. 3. The all-digital fractional frequency-division PLL structure as claimed in claim 1, wherein the DLF filters out the high-frequency components of the digital signal output by the TDC and outputs a group of digital control signals to control the DCO frequency and phase. 4. The all-digital fractional frequency-division PLL structure according to claim 1, wherein the DPI weights two clock signals of different phases, and then outputs a clock signal of a required phase. 5. The all-digital fractional frequency-division phase-locked loop structure as claimed in claim 4, wherein the high bit of the digital control signal of the DPI is used to realize quadrant selection, and the low bit is used to realize weight ratio. 6. The all-digital fractional frequency-division phase-locked loop structure as claimed in claim 1, wherein the SDM dynamically adjusts the digital control signal of the DPI by generating a series of random number signals. 7. The all-digital fractional frequency-division phase-locked loop structure as claimed in claim 1, wherein the input of the DPI is an orthogonal differential eight-phase clock, which is respectively 0°, 45°, 90°, 135° , 180°, 225°, 270° and 315° phases; 8-bit digital control signals are used, the upper 3 bits are used to control the switching tube to select a certain two phases to determine the quadrant of the output phase, and the lower 5 bits are used To determine the tail current weight. 8. The all-digital fractional frequency division PLL structure as claimed in claim 1, wherein said TDC adopts a structure based on a Vernier delay line.