KR101885033B1 - Digital clock data recovery apparatus using delayed line phase frequency detection - Google Patents

Abstract

The present invention relates to a digital clock data recovery device. According to the present invention, the digital clock data recovery device includes: a delayed line phase frequency detector detecting a positive edge and a negative edge of an input signal in each delay cell using a digitally controlled oscillator (DCO) clock signal while the input signal passes through the multiple delay cells in order and generating a count signal of counting the position of the positive edge and the negative edge, wherein the delayed line phase frequency detector outputs sampling data in which the input signal is sampled in accordance with the DCO clock signal; a digital loop filter generating the DCO control signal for controlling frequencies of the DCO clock signal using the count signal and a parameter which is set in advance; a DCO generating the DCO clock signal by controlling output frequencies in accordance with the DCO control signal; a programmable frequency demultiplier converting the frequencies of the DCO clock signal in accordance with a reference factor which is set in advance; a demultiply factor generator generating a demultiply rate by storing the multiple sampling data using the DCO clock signal and comparing the multiple sampling data with a preamble stored in advance; and a clock frequency demultiplier outputting a restoration clock signal by demultiplying the DCO clock signal in accordance with the demultiply rate. According to the present invention, the digital clock data recovery device forms whole composition of the clock data recovery device as a digital circuit. So, an operation condition is flexible, and portability to the other process techniques is excellent.

Description

TECHNICAL FIELD [0001] The present invention relates to a digital clock data restoration apparatus using delay line phase frequency detection,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital clock data recovery apparatus using delay line phase frequency detection, and more particularly, to a clock data recovery apparatus implemented with a pure digital circuit through a delay line phase frequency detection method.

Clock Data Recovery (CDR) circuitry is one of the most important circuits in digital data communication. The CDR circuit is a circuit that determines the data input / output performance. It is important to design the CDR circuit so that it can withstand large input jitter in design.

Most of the existing CDR circuits are implemented by analog circuit design method. Recently, various digital CDR implementations such as a CDR circuit using an all-digital PLL (AD-PLL) and a burst mode CDR (BM-CDR) have been actively studied. However, it is difficult to judge a pure digital design method in terms of full custom layout using certain cell libraries or some analog circuits to be external. The pure digital method is designed based on HDL and can be synthesized using EDA tool, so that it can be designed without depending on specific process technology.

Conventional CDR circuits have been implemented in various ways, and many circuits have been designed based on the Alexander PFD (Phase Frequency Detector). This structure has a problem in that it is difficult to restore clock data in the process of searching for the phase when the jitter of the input terminal is large due to the low operating frequency. In the case of PFD, which simply generates UP and DOWN signals, it is difficult to know which data should be sampled at what timing when random data is input, and input jitter may not operate correctly for large random data input.

The technology of the background of the present invention is disclosed in Korean Patent Laid-Open No. 10-2015-0012137 (published on Feb. 20, 2013).

An object of the present invention is to provide a clock data recovery device implemented as a pure digital circuit through a delay line phase frequency detection method.

According to an aspect of the present invention, there is provided a digital clock data recovery apparatus including: a digital-to-analog converter for converting a rising edge of the input signal in each delay cell and a rising edge of the input signal in each delay cell using a DCO clock signal while an input signal sequentially passes through a plurality of delay cells; A delay line phase frequency detector for detecting a falling edge and generating a count signal which counts the positions of the rising edge and the falling edge, the input signal outputting sampling data sampled in accordance with the DCO clock signal, A digital loop filter for generating a DCO control signal for controlling a frequency of the DCO clock signal using a predetermined parameter, a digital controlled oscillator for adjusting the output frequency according to the DCO control signal to generate the DCO clock signal, A processor for converting the frequency of the DCO clock signal according to a reference factor A division factor generator for storing a plurality of sampling data using the DCO clock signal and generating a division ratio by comparing the plurality of sampling data with a pre-stored preamble, And a clock divider that divides the signal and outputs a restored clock signal.

Wherein the delay line phase frequency detector comprises: a delay line connected in series with a plurality of delay cells through which the input signal passes; an output terminal connected to the output terminals of the plurality of delay cells and using the output signal of the delay cell connected thereto and the DCO clock signal A plurality of D flip-flops for generating a DFF (D-Flip Flop) signal, and for detecting a rising edge and a falling edge of the input signal using the DFF signal, counting positions of the rising edge and the falling edge, And a counter section for generating a count signal.

The counter determines the rising edge if the neighboring DFF signal is '10' and the rising edge if the neighboring DFF signal is '01' The position can be detected.

The delay line phase frequency detector outputs the DFF signal of the D flip-flop connected to the output terminal of the delay cell located at the center among the plurality of delay cells to the division factor generator in a locking process for synchronization, .

Wherein the division factor generator comprises: a plurality of shift registers that operate in response to DCO clock signals having different division values, the plurality of shift registers storing a plurality of sampling data, and determining whether or not the pre-stored preamble matches a plurality of sampling data, And a controller for generating the frequency division ratio with a frequency division value corresponding to the sampling signal if the number of times of coincidence with the preamble stored in the preamble is equal to or greater than a preset value.

A frequency difference between the frequency of the PVT clock signal reflecting the operation error of the digital controlled oscillator according to the PVT variation and the automatic P & R and the frequency of the reference clock signal, and generating a frequency correction signal according to the determined frequency difference And may further include a single phase frequency detector 3SPFD.

Wherein the frequency correction signal includes a first correction signal for lowering the frequency division ratio of the programmable frequency divider, an UP signal for lowering the frequency of the DCO clock signal, a second correction signal for increasing the frequency division ratio of the programmable frequency divider, DOWN < / RTI >

As described above, according to the present invention, since the entire configuration of the clock data restoration apparatus is implemented by a digital circuit, portability to other process technology is excellent and operating conditions are flexible. In addition, since the entire circuit is implemented as a digital circuit, it is possible to perform fast frequency tracking on signals and operate in a wide frequency band, so that it can be easily applied to high-speed communication equipment.

1 is a block diagram of a digital clock data recovery apparatus according to an embodiment of the present invention.
2 is a block diagram of a delay line phase frequency detector according to an embodiment of the present invention.
3 is a block diagram of a digitally controlled oscillator according to an embodiment of the present invention.
4 is a block diagram of a division factor generator according to an embodiment of the present invention.
5 is a view showing a finite state machine of a three-stage phase frequency detector according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention.

In the following description of the present invention, it is assumed that an input signal is a S / PDIF (Sony Philips Digital Interface Format) signal.

First, a digital clock data restoration apparatus according to an embodiment of the present invention will be described with reference to FIG. 1 is a block diagram of a digital clock data recovery apparatus according to an embodiment of the present invention.

1, the apparatus 100 for recovering digital clock data according to an embodiment of the present invention includes a delay line phase frequency detector 110, a digital loop filter 120, a digital controlled oscillator 130, a programmable frequency divider 140, a divider factor generator 150, and a clock divider 160, and may further include a three-stage phase frequency detector 170.

A delayed phase phase detector (DLPFD) 110 detects an input signal (S / PDIF) in each delay cell using a DCO clock signal while the input signal S / PDIF sequentially passes through a plurality of delay cells. The rising edge and the falling edge are detected.

The delay line phase frequency detector 110 generates a count signal indicating the phase difference between the rising edge and the falling edge of the input signal, that is, the DCO clock. Where the count signal includes a leading edge count signal clkLeadsCnt and a delay edge count signal clkLagsCnt. The leading edge count signal clkLeadsCnt indicates how far the edge or phase of the input signal precedes the edge or phase of the DCO clock and the delayed edge count signal clkLagsCnt indicates that the edge or phase of the input signal is at the edge or phase of the DCO clock And how much it lags behind. The larger the phase difference between the input signal and the DCO clock is, the larger the value of the count signal becomes.

The delay line phase frequency detector 110 then transmits the count signal to the digital loop filter 120.

The delay line phase frequency detector 110 outputs sampling data CDR_SPDIF to the host. The sampling data means a signal obtained by sampling an input signal according to a restored clock signal.

Next, the digital loop filter (DLF) 120 is used to control the digital controlled oscillator 130. The digital loop filter 120 converts the input count signal according to a predetermined rule using digital logic to generate a DCO control signal . The DCO control signal is a signal for controlling the phase and frequency of the DCO clock signal.

Here, the count signal of the delay line phase frequency detector is a value indicating the degree of phase difference between the DCO clock signal and the input signal, and the count value 1 is different from 1 of the DCO control signal. Therefore, the input count value should be converted into an appropriate DCO control signal using a predetermined rule. At this time, the DCO control signal is calculated according to the predetermined formula using the count value and predetermined parameters. The calculation process may be changed according to the semiconductor manufacturing process, the frequency range of the DCO clock signal, and the DCO structure.

Specifically, the digital loop filter 120 outputs a DCO control signal according to any one of the leading edge count signal and the delayed edge count signal when any one of the leading edge count signal and the delayed edge count signal is not '0' .

For example, it is assumed that the leading edge count signal is not '0'. The digital loop filter 120 then generates a DCO control signal in accordance with the leading edge count signal. On the other hand, if the delay edge count signal is not '0', the digital loop filter 120 generates a DCO control signal in accordance with the delay edge count signal.

Next, a digital controlled oscillator (DCO) 130 adjusts the output frequency according to the DCO control signal to generate a DCO clock signal. The digital controlled oscillator 130 may be implemented in a structure capable of dynamic timing analysis, and a specific configuration will be described below.

Next, the programmable divider (PD) 140 converts the frequency of the DCO clock signal according to a preset reference factor. In this case, the reference factor may be a design value that is used by a person skilled in the art using a previously stored reference value or a value stored in the host or three-phase frequency detector 170.

Generally, in the case of the digitally controlled oscillator 130, the oscillation frequency is inversely proportional to the number of gates through which the clock signal passes. Therefore, when the frequency of the signal is relatively low, such as the S / PDIF signal, the digitally controlled oscillator 130 requires too many gates and is difficult to implement. In order to solve this problem, in the embodiment of the present invention, the digital controlled oscillator 130 generates a high frequency DCO clock and at the same time converts the frequency of the DCO clock signal into a preset reference frequency using the programmable frequency divider 140 .

At this time, the conversion rate can be changed through parameters in the host. In addition, the digital controlled oscillator can be designed in HDL (Hardware Description Language) using a digital process cell library and can be implemented in an automatic P & R (Place and Route) method. At this time, a design frequency error may occur. If this value is large, correction can be performed through the three-stage phase frequency detector 170, so that it can be implemented in a pure digital manner.

Next, the DIVision factor generator (DIVGEN) 150 stores a predetermined number of the plurality of sampled data using the DC0 clock signal, and compares the plurality of sampled data with the pre-stored preamble to generate the frequency division ratio.

At this time, the number of the stored sampling data varies according to the transmission standard, and the data is sampled according to different sampling frequencies supported by the transmission standard, and the frame or block synchronization is performed while searching for a sampling frequency coinciding with the preamble stored.

Next, the clock divider 160 divides the DCO clock signal according to the division ratio and outputs the restored clock signal CDR_CLK to the host. The host performs data sampling using the restored clock signal and the sampling data or directly uses the sampling data.

Next, the 3-stage phase frequency detector (3SPFD, 170) minimizes the operation error of the digitally controlled oscillator 130 caused by PVT (Process, Voltage, Temperature) variation.

Specifically, the three-phase frequency detector 170 compares the PVT clock signal PVT_CLK reflecting the operation error of the digitally controlled oscillator 130 according to the PVT transition and the reference clock signal REF_CLK to determine the frequency difference relationship. The three-stage phase frequency detector 170 generates a frequency correction signal according to the determined frequency difference relation.

Here, the frequency correction signal is generated as a correction value for correcting the reference factor of the programmable frequency divider when the frequency difference between the PVT clock signal and the reference clock is larger than a preset threshold value. And the frequency correction signal is generated as an UP signal indicating a state in which the PVT clock signal is higher in phase than the reference clock signal and a DOWN signal indicating a state in which the PVT clock signal is in phase with respect to the reference clock signal.

If the frequency difference between the PVT clock signal and the reference clock is greater than a predetermined threshold value, the three-phase phase frequency detector 170 stores the frequency correction signal in the setting register of the programmable frequency divider. Change the division factor of the DCO clock signal frequency by changing the factor.

When the three-phase frequency detector 170 is smaller than a predetermined threshold value, the digital filter 130 transmits a frequency correction signal to the digital loop filter 120. The digital loop filter 120 filters the digital control oscillator 130 according to the frequency correction signal. And generates a control signal. The digitally controlled oscillator 130 adjusts the output frequency of the DCO clock signal in accordance with the control signal.

Therefore, if the frequency difference between the PVT clock signal and the reference clock is greater than a predetermined threshold value, the frequency division ratio of the programmable frequency divider 140 is changed. If the frequency division ratio is smaller than the preset threshold value, the DCO output frequency .

Meanwhile, the three-phase frequency detector 170 operates simultaneously when the digital controlled oscillator 130 is operated for the first time. When the frequency difference of the PVT clock signal becomes smaller than a predetermined threshold value as a result of the frequency relation determination, the operation ends. Therefore, the triple phase frequency detector 170 does not operate during normal data transmission. According to the embodiment of the present invention, it is possible to minimize the operation error of the PV control oscillator 130 by the PVT variation and the automatic P & R.

2 is a block diagram of a delay line phase frequency detector according to an embodiment of the present invention.

2, the delay line phase frequency detector 110 according to the embodiment of the present invention includes a delay line 111, a plurality of D-flip flops 112, and a counter unit 113.

First, the delay line 111 has a structure in which a plurality of delay cells through which the input signal S / PDIF passes are serially connected. At this time, the phase of the input signal changes every time it passes through each delay cell.

When there are the same number of delay cells, a larger range of phase difference can be detected if the delay time of each delay cell is large. However, the phase error of the DCO clock and the input signal increases after the lock, thereby increasing the output jitter. On the other hand, if the delay time of the delay cell is small, the detection range of the phase difference is small, but the output jitter is also small. To increase the detection range and reduce the output jitter, the number of delay cells is increased and the delay time of the delay cells is reduced, but the circuit size is increased.

A plurality of D flip-flops 112 are connected to the output terminals of the plurality of delay cells, and generate a DFF (D-Flip Flop) signal using the output signal of the delay cell and the DCO clock signal do. In this case, the DFF signal of the D flip-flop 112 connected to the output terminal of the delay cell located at the middle among the serially connected delay cells is used as the sampling data in the division factor generator 150 in the process of locking for synchronization, .

The counter unit 113 detects the positions of the rising edge and the falling edge of the input signal using the DFF signal. Specifically, the counter unit 113 determines that the neighboring DFF signal is '10', and determines that the neighboring DFF signal is a rising edge if the neighboring DFF signal is '01'. For example, if the output of the second D flip-flop is '0' and the output of the third D flip-flop is '1', the neighboring DFF signal becomes '01' do.

Then, the counter unit 113 generates a count signal indicating the magnitude of the leading and delaying, that is, the position where the rising edge and the falling edge are detected. Herein, the term "leading" means that the phase of the input signal is faster than the phase of the DCO clock signal, and the term "lagging" means that the phase of the input signal is slower than the phase of the DCO clock signal. For example, in the case where the rising edge of the input signal is detected as a delay cell after 10 cells with respect to the center cell, the number of delay cells in the preceding cell becomes 10, and the counter unit 113 counts the leading edge count signal clkLeadsCnt 10. Since the count signal is detected and output at a time, the phase difference can be rapidly reduced and the lock time can be reduced.

3 is a block diagram of a digitally controlled oscillator according to an embodiment of the present invention.

As shown in FIG. 3, the digitally controlled oscillator 130 includes an inverter chain 131 and a clock path selector 132 in which a plurality of inverters are serially connected.

The clock path selector 132 includes a tri-state cell chain and a decoder. The path and frequency are determined according to the DCO control signal tune of the digital loop filter 120.

The number and frequency of the inverters and the tri-state cells constituting the inverter chain 131 are determined according to the delay times of the inverters and the tri-state cells required by the digital clock data recovery apparatus 100. For example, if the operating frequency is low, a large delay time and a large number of cells are required. Conversely, if the operating frequency is high, a small delay time and a small number of cells are required.

4 is a block diagram of a division factor generator according to an embodiment of the present invention.

As shown in FIG. 4, the division factor generator 150 includes a plurality of shift registers 151 and a controller 152.

First, a plurality of shift registers 151 operate in response to DCO clock signals having different division values, and sample the input signal that has passed through a plurality of delay cells to generate a sampling signal.

The control unit 152 determines whether or not the preamble stored in the preamble matches the preamble and generates a frequency division ratio corresponding to the preamble corresponding to the preamble.

For example, as shown in FIG. 4, it is assumed that a plurality of shift registers 151 are five 8-bit shift registers 151. Here, the five shift registers 151 have different sampling frequencies corresponding to the respective shift registers 151, respectively, and operate according to the DCO clock signal having five different division values. Since the plurality of shift registers 151 are composed of 8 bits, when the input signal passes through the shift register 151, an 8-bit sampling signal is generated. Thus, a total of five 8-bit sampling signals are generated.

Then, the control unit 152 receives five 8-bit sampling signals and compares them with the 8-bit preamble stored in advance. Since the five 8-bit sampling signals are sampled using DCO clock signals having different dividing values, only one of the five sampling signals has a value that matches the pre-stored preamble.

However, the data may accidentally have the same value as the preamble or be changed to another sampling frequency after sampling. Therefore, the control unit 152 determines the frequency division ratio of the shift register 151 that outputs the same sampling signal as the preamble stored three or more times. If the third shift register 151 outputs the same sampling signal as the previously stored preamble three times, the division value of the third shift register 151 is determined as the division ratio.

Meanwhile, when the values of the leading edge count and the delayed edge count are both '0', the digital clock data recovery apparatus 100 according to the embodiment of the present invention performs frequency locking and the output of the division factor generator becomes effective Respectively. If the number of times of coincidence with the pre-stored preamble of the sampling signal is equal to or larger than the set value, the divide factor divFactor is generated with the division value corresponding to the corresponding sampling signal. The clock divider 160 receiving the division ratio generates the lock signal CDR_LOCK after division completion.

5 is a view showing a finite state machine of a three-stage phase frequency detector according to an embodiment of the present invention.

5, the three-stage phase frequency detector 170 is a finite state machine (Finite) having three states of a zero state (state 0), a first state (state 1) and a second state (state 2) State Machine, FSM).

Here, the 0-th state indicates a state in which generation of the frequency correction signal is terminated. The zero state indicates an initial state and a stabilized state. The first state is a state for generating a frequency correction signal or UP signal that lowers the frequency division ratio of the programmable frequency divider. The second state is a state for generating a frequency correction signal or a DOWN signal for increasing the frequency division ratio of the programmable frequency divider.

More specifically, the three-phase frequency detector 170 operates in the 0 state in the initial operation, and in the 0th state, in the 0th state or the 2nd state, depending on the frequency difference between the PVT clock signal (PVT_CLK) and the reference clock signal (REF_CLK) And generates a frequency correction signal corresponding to whether the frequency difference is larger or smaller than a predetermined threshold value. The three-stage phase frequency detector 170 terminates the generation of the frequency correction signal when transitioning from the first state or the second state to the zero state.

According to the first embodiment, first, the three-stage phase frequency detector 170 starts its operation in the 0-th state. When the frequency of the PVT clock signal and the frequency of the reference clock signal F_REF are compared with each other, if the value obtained by subtracting the frequency of the reference clock signal from the frequency of the PVT clock signal is greater than a preset first threshold value (F_PVT - F_REF > first threshold value), transition is made from the 0th state to the first state. If the value obtained by subtracting the frequency of the reference clock signal from the frequency of the PVT clock signal is greater than a predetermined second threshold value (F_PVT - F_REF> second threshold value), the three stage phase frequency detector 170 A correction value for reducing the frequency division ratio of the programmable frequency divider is generated and stored in the setting register. On the other hand, if the value obtained by subtracting the frequency of the PVT clock signal from the frequency of the reference clock signal is smaller than or equal to a predetermined second threshold value (F_PVT - F_REF? Q second threshold value), the 3-stage phase frequency detector 170 outputs the UP signal And lowers the frequency of the DCO clock through the digital loop filter 120.

On the other hand, if the state in which the value obtained by subtracting the frequency of the reference clock signal from the frequency of the PVT clock signal in the first state continues to be greater than a predetermined first threshold value (F_PVT - F_REF> first threshold value) ≪ / RTI > again transitions to the first state to generate the UP signal. On the other hand, if the value obtained by subtracting the frequency of the reference clock signal from the frequency of the PVT clock signal in the first state is less than or equal to a predetermined first threshold value (F_PVT - F_REF? Q first threshold value) 0 " state to terminate the generation of the frequency correction signal.

According to the second embodiment, first, the three-stage phase frequency detector 170 starts its operation in the 0-th state. Thereafter, if the frequency (F_PVT) of the PVT clock signal is compared with the frequency (F_REF) of the reference clock signal and the value obtained by subtracting the frequency of the PVT clock signal from the frequency of the reference clock signal is greater than a predetermined first threshold value (F_REF - F_PVT > First threshold value), transition is made from the 0th state to the second state. If the value obtained by subtracting the frequency of the reference clock signal from the frequency of the PVT clock signal is greater than a predetermined second threshold value (F_REF - F_PVT> second threshold value), the three stage phase frequency detector 170 determines the magnitude of the difference, That is, a correction value for increasing the frequency division ratio of the programmable frequency divider is generated according to the difference value and stored in the setting register. On the other hand, if the value of the frequency of the reference clock signal minus the frequency of the PVT clock signal is less than or equal to the second threshold value (F_REF - F_PVT? Q second threshold value), the triple phase frequency detector 170 generates the DOWN signal And raises the DCO clock frequency through the digital loop filter 120.

On the other hand, if the state (F_REF - F_PVT> first threshold value) in which the value obtained by subtracting the frequency of the PVT clock signal from the frequency of the reference clock signal in the second state continues to be greater than the preset first threshold value, 170 transition back to the second state to generate the DOWN signal. On the other hand, if the value obtained by subtracting the frequency of the PVT clock signal from the frequency of the reference clock signal in the second state is less than or equal to the preset first threshold value (F_REF - F_PVT? Q first threshold value) Shifts to the 0th state and ends the generation of the frequency correction signal.

The operation according to the three states in the three-stage phase frequency detector 170 according to the embodiment of the present invention is to stabilize the output of the frequency correction signal in a high-speed operation environment. If the phase error signal is output using only the first and second states without the zero state, the UP signal and the DOWN signal are repeatedly output even in a fine phase error, resulting in an unstable state. However, the three-stage phase frequency detector 170 according to the embodiment of the present invention can increase the output stability of the frequency correction signal by preventing the repeated output of the UP signal and the DOWN signal by adding the 0 state.

According to the embodiment of the present invention, since the entire configuration of the clock data restoration device is implemented by a digital circuit, it is advantageous in portability to other process technology and flexibility in operating conditions. In addition, since the entire circuit is implemented as a digital circuit, it is possible to perform fast frequency tracking on signals and operate in a wide frequency band, so that it can be easily applied to high-speed communication equipment.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

100: Digital clock data restoration device
110: delay line phase frequency detector 111: delay line
112: a plurality of D flip-flops 113:
120: digital loop filter 130: digitally controlled oscillator
131: inverter chain 132: clock path selector
140: Programmable divider 150: Divider factor generator
151: Shift register 152:
160: clock divider 170: three-phase frequency detector

Claims (7)

Detecting a rising edge and a falling edge of the input signal in each delay cell using a DCO (Digital Controlled Oscillator) clock signal while the input signal sequentially passes through a plurality of delay cells, and detecting a rising edge and a falling edge of the input signal A delay line phase frequency detector for generating a count signal in which the input signal is sampled according to the DCO clock signal,
A digital loop filter for generating a DCO control signal for controlling the frequency of the DCO clock signal using the count signal and predetermined parameters,
A digital controlled oscillator for adjusting the output frequency according to the DCO control signal to generate the DCO clock signal,
A programmable divider for converting the frequency of the DCO clock signal according to a predetermined reference factor,
A division factor generator that stores a plurality of sampling data using the DCO clock signal output from the programmable frequency divider and generates a division ratio by comparing the plurality of sampling data with a pre-stored preamble,
And a clock divider that divides the DCO clock signal according to the division ratio to output a restored clock signal,
Wherein the delay line phase frequency detector comprises:
And detects the rising edge and the falling edge using the DCO clock signal output in the programmable frequency divider. The method according to claim 1,
Wherein the delay line phase frequency detector comprises:
A delay line in which a plurality of delay cells through which the input signal passes are serially connected,
A plurality of D flip-flops connected to the output terminals of the plurality of delay cells, each of the D flip-flops generating a DFF (D-Flip Flop) signal using an output signal of the delay cell connected to the delay cell and the DCO clock signal;
And a counter unit for detecting a rising edge and a falling edge of the input signal using the DFF signal and counting the positions of the rising edge and the falling edge to generate the count signal. 3. The method of claim 2,
Wherein,
If the neighboring DFF signal is '10', it is determined to be the falling edge. If the neighboring DFF signal is '01', it is determined that the rising edge is detected and the position of the rising edge and the falling edge of the input signal is detected Digital clock data recovery device. 3. The method of claim 2,
Wherein the delay line phase frequency detector comprises:
A digital clock data recovery unit for outputting the DFF signal of the D flip-flop connected to the output terminal of the delay cell located at the center among the plurality of delay cells to the division factor generator in the locking process for synchronization, . The method according to claim 1,
Wherein the division factor generator comprises:
A plurality of shift registers which operate in response to DCO clock signals having different division values, the shift registers storing the plurality of sampling data,
A control unit for determining whether or not the preamble stored beforehand matches the plurality of sampling data and generating the division ratio with a division value corresponding to the sampling data if the number of times of matching the preamble with the preamble is equal to or larger than a preset value A digital clock data recovery device. The method according to claim 1,
Wherein a frequency difference between the frequency of the PVT clock signal reflecting the operation error of the digital controlled oscillator according to the PVT variation and the frequency of the reference clock signal is determined, Detector (3SPFD). ≪ / RTI > The method according to claim 6,
The frequency-
A first correction signal for lowering the frequency division ratio of the programmable frequency divider,
An UP signal for lowering the frequency of the DCO clock signal,
A second correction signal for increasing the frequency division ratio of the programmable frequency divider, and
And a DOWN signal for increasing the frequency of the DCO clock signal.

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