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CN114823592B - 一种晶上系统结构及其制备方法 - Google Patents

一种晶上系统结构及其制备方法 Download PDF

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CN114823592B
CN114823592B CN202210758528.XA CN202210758528A CN114823592B CN 114823592 B CN114823592 B CN 114823592B CN 202210758528 A CN202210758528 A CN 202210758528A CN 114823592 B CN114823592 B CN 114823592B
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wafer
wafer substrate
bonding
integrated
core particles
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CN114823592A (zh
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王伟豪
李顺斌
刘冠东
张汝云
刘勤让
万智泉
沈剑良
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Zhejiang Lab
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Abstract

本发明公开一种晶上系统结构及其制备方法，该结构包括晶圆基板、集成芯粒、系统配置板和系统散热模组。所述晶圆基板和集成芯粒通过晶圆基板上表面的晶圆微凸点阵列和集成芯粒下表面的芯粒微凸点阵列键合相连；所述晶圆基板和系统配置板通过晶圆基板上的铜柱阵列和系统配置板下表面的焊盘键合相连；晶圆基板和系统配置板之间设有塑封层，塑封晶圆基板、集成芯粒和铜柱阵列；所述集成芯粒之间通过晶圆基板的顶部设置的重布线层电连接；所述系统配置板通过所述重布线层以及铜柱阵列与集成芯粒电连接；所述系统散热模组贴合在晶圆基板的下表面。本发明解决了SoW制备良率的忧虑和高密度TSV带来的晶圆可靠性的问题。

Description

一种晶上系统结构及其制备方法
技术领域
本发明涉及集成电路技术领域，尤其涉及一种晶上系统结构及其制备方法。
背景技术
集成电路产业进入到后摩尔定律时代后，先进集成封装技术逐步成为潮流的浪尖。More than Moore中利用先进封装在系统架构层面对系统进行优化。利用die-to-die内部互联技术将多个模块芯片与底层基础芯片封装在一起，构成SiP芯片模式，诸如EMIB及CoWoS等技术。而在2021年台积电将系统集成进一步扩展到了晶圆上，发布了InFO_SoW（Integrated Fan Out_System on Wafer）晶上系统技术，美国Cerebras以及特斯拉分别利用SoW技术发布了其WSE（Wafer scale engine）以及Tesla Tojo产品用于高性能人工智能计算系统。
目前晶上系统SoW主要依赖于晶圆上的但工艺节点在一张晶圆上直接利用半导体工艺制备多个芯片并实现互连，再通过TSV（硅通孔）等垂直互连技术将系统信号引出，构成如Cerebras WSE的超大芯片。这种方法对半导体晶圆厂的良率有着极大的考验，一旦晶圆上芯片存在工艺缺陷，就有可能导致整个系统失效，同时高密度的TSV对晶圆的可靠性也会造成极大困扰。
发明内容
为了解决现有技术中存在的上述技术问题，本发明提出了一种晶上系统结构及其制备方法，可以有效提高晶上系统的良率以及可靠性，其具体技术方案如下：
一种晶上系统结构，包括晶圆基板、集成芯粒、系统配置板和系统散热模组；
所述的晶圆基板的顶部设有重布线层，上表面设有晶圆微凸点阵列形成的键合区域，在该键合区域周围设有由铜柱垫和铜柱连接组成的铜柱阵列；
所述的集成芯粒下表面设有芯粒微凸点阵列，与晶圆基板上表面键合区域的晶圆微凸点阵列对应；
所述的系统配置板上集成有配置芯片和接插件，系统配置板下表面设有焊盘；
所述的晶圆基板和集成芯粒通过所述晶圆微凸点阵列和芯粒微凸点阵列在键合区域键合相连；所述的晶圆基板和系统配置板通过所述铜柱阵列和焊盘键合相连；晶圆基板和系统配置板之间设有塑封层，用于塑封晶圆基板、与晶圆基板键合相连的集成芯粒和铜柱阵列；所述的集成芯粒之间通过所述重布线层电连接；所述系统配置板通过所述重布线层以及铜柱阵列与集成芯粒电连接；所述的系统散热模组贴合在晶圆基板的下表面。
优选的，所述的晶圆基板为半导体晶圆，包括Si、SiC、GaN的半导体材料晶圆，尺寸≥8寸，厚度在300 um~1000um之间。
优选的，所述的铜柱高度≥100um，径高比为1：1~1：2之间。
优选的，所述键合区域面积小于一次图形化区域的最大面积，所述一次图形化区域的最大面积由键合区域及其周围的铜柱阵列所占区域的面积组成，各个键合区域间距≥100um。
优选的，所述集成芯粒为异质异构芯粒，集成芯粒的面积大小≤一次图形化区域的最大面积，集成芯粒的厚度≤150um。
优选的，所述系统配置板为PCB板，所述配置芯片用于对集成芯粒进行供电、测试、系统配置。
优选的，所述的系统散热模组包括风冷散热模组、水冷散热模组、微流道散热模组。
一种晶上系统结构的制备方法，包括以下步骤：
步骤S1，对晶圆基板进行多次图形化操作后在晶圆基板表面形成多个一次图形化区域，所述图形化操作具体为：利用半导体前道/后道金属工艺形成晶圆基板顶部的重布线层、晶圆微凸点阵列以及铜柱垫；其中的晶圆微凸点阵列形成晶圆基板表面的键合区域；
步骤S2，利用C2W键合工艺将集成芯粒与晶圆基板键合，形成集成晶圆；
步骤S3，利用厚膜光刻胶在集成晶圆表面形成≥100um的光阻层，刻蚀出铜柱的位置，即铜柱孔；
步骤S4，利用电镀工艺在步骤S3刻蚀出的即铜柱孔处形成铜柱；
步骤S5，去除光刻胶后对集成晶圆进行塑封形成塑封层，再减薄塑封层，使露出铜柱表面；
步骤S6，将铜柱与系统配置板下表面的焊盘对准键合，再在集成晶圆底部贴合系统散热模组，完成晶上系统的结构。
有益效果：
通过本发明的晶上系统结构可以实现晶上系统晶圆基板、集成芯粒、系统配置板、系统散热模组的高密度集成，利用C2W键合解决SoW制备良率的忧虑，并且可以通过改变集成芯粒的类型实现不同领域专用的晶上系统，并且通过晶圆基板铜柱实现集成芯粒与系统配置板的连接，解决了高密度TSV带来的晶圆可靠性的问题，对晶上系统的发展具有重要意义。
附图说明
图1为本发明的晶上系统结构示意图；
图2为本发明的晶上系统结构横截面示意图；
图3为本发明的晶上系统晶圆基板上表面示意图；
图4为本发明的晶上系统晶圆系统集成芯粒和铜柱示意图；
图5为本发明实施例的晶上系统结构的制备过程示意图；
图中，1晶圆基板，2集成芯粒，3铜柱，4系统散热模组，5系统配置板，6配置芯片，7接插件，8焊盘，9塑封层，10铜柱垫，11重布线层，12芯粒微凸点阵列，13晶圆微凸点阵列，14键合区域，15一次图形化区域，16光阻层，铜柱孔17。
具体实施方式
为了使本发明的目的、技术方案和技术效果更加清楚明白，以下结合说明书附图和实施例，对本发明作进一步详细说明。
如图1所示，一种晶上系统结构，包括晶圆基板1、集成芯粒2、系统配置板5和系统散热模组4；
如图2所示，所述的晶圆基板1的顶部具有重布线层11（RDL），上表面具有晶圆微凸点阵列13形成的键合区域14，在该键合区域14周围设有由铜柱垫10和铜柱3连接组成的铜柱阵列，如图3和图4所示；
所述的集成芯粒2下表面具有芯粒微凸点阵列12，与晶圆基板1上表面键合区域14的晶圆微凸点阵列13对应；
所述的系统配置板5集成了对晶上系统的配置芯片6和对外部通信的接插件7，系统配置板5下表面具有焊盘8。
所述的晶圆基板1和集成芯粒2通过晶圆基板1上表面的晶圆微凸点阵列13和集成芯粒2下表面的芯粒微凸点阵列12在键合区域14键合相连；所述的晶圆基板1和系统配置板5通过晶圆基板1上的铜柱阵列和系统配置板5下表面的焊盘8键合相连；晶圆基板1和系统配置板5之间设有塑封层9，用于塑封晶圆基板1、与晶圆基板1键合相连的集成芯粒2和铜柱阵列；所述的集成芯粒2之间可以通过晶圆基板1的重布线层11实现电学连接；所述的集成芯粒2和系统配置板5通过晶圆基板1的重布线层11以及铜柱阵列实现电学连接；所述的系统散热模组4贴合在晶圆基板1的下表面。
所述的晶圆基板1为半导体晶圆，包括但不限于Si、SiC、GaN等半导体材料晶圆，尺寸≥8寸，厚度在300 um~1000um之间。本实施例中选用750um厚的12寸硅晶圆。
所述的晶圆基板1铜柱高度≥100um，径高比为1：1~1：2之间。本实施例中为150um高的径高比1：1铜柱。
所述的晶圆基板1的重布线层11可以实现芯粒键合后集成芯粒2之间的电学连通。
所述的晶圆基板1的由晶圆微凸点阵列13形成的键合区域14面积小于一次图形化区域15的最大面积，所述一次图形化区域15的最大面积由键合区域14及其周围的铜柱阵列所占区域的面积组成，各个键合区域间距≥100um。本实施例中键合区域间距400um。
所述的集成芯粒2可以是异质异构芯粒，根据集成芯粒2的不同可以构建不同领域专用的晶上系统类型，集成芯粒2的面积大小≤一次图形化区域15的最大面积，集成芯粒2的厚度≤150um。本实施例中为同质的交换芯片，交换芯片面积与键合区域面积相同，交换芯片厚度为100um。
所述的系统配置板5为PCB板，所述的配置芯片6具有对集成芯粒2进行供电、测试、系统配置等功能。
所述的系统散热模组4根据晶上系统的功率需求选取风冷、水冷、微流道等多种散热模组。本实施例中选用水冷微流道散热件作为散热模组。
如图5所示，一种晶上系统结构的制备方法，包括以下步骤：
步骤S1，对晶圆基板1进行多次图形化操作后在晶圆基板1表面形成多个一次图形化区域15，所述图形化操作具体为：利用半导体前道/后道金属工艺形成晶圆基板1顶部的重布线层11、晶圆微凸点阵列13以及铜柱垫10；其中的晶圆微凸点阵列13形成晶圆基板1表面的键合区域14；
步骤S2，利用C2W（Chip to Wafer）键合工艺将集成芯粒2与晶圆基板1键合，形成集成晶圆；
步骤S3，利用厚膜光刻胶在集成晶圆表面形成≥100um的光阻层16，刻蚀出铜柱3的位置，即铜柱孔17；
步骤S4，利用电镀工艺在步骤S3刻蚀出铜柱孔17处形成铜柱3，所述铜柱3高度150um，径高比为1：1；
步骤S5，去除光刻胶后对集成晶圆进行塑封后形成塑封层9，再减薄塑封层9，使露出铜柱表面，本实施例中塑封层9减薄至120um；
步骤S6，将步骤S5得到的集成晶圆铜柱3与系统配置板5下表面焊盘8对准键合，再在集成晶圆底部贴合系统散热模组4，完成了晶上系统的结构；所述系统散热模4组根据晶上功率系选取。
以上所述，仅为本发明的优选实施案例，并非对本发明做任何形式上的限制。虽然前文对本发明的实施过程进行了详细说明，对于熟悉本领域的人员来说，其依然可以对前述各实例记载的技术方案进行修改，或者对其中部分技术特征进行同等替换。凡在本发明精神和原则之内所做修改、同等替换等，均应包含在本发明的保护范围之内。

Claims (6)

1.一种晶上系统结构的制备方法，所述晶上系统结构包括：晶圆基板（1）、集成芯粒（2）、系统配置板（5）和系统散热模组（4）；所述的晶圆基板（1）的顶部设有重布线层（11），上表面设有晶圆微凸点阵列（13）形成的键合区域（14），在该键合区域（14）周围设有由铜柱垫（10）和铜柱（3）连接组成的铜柱阵列；所述的集成芯粒（2）下表面设有芯粒微凸点阵列（12），与晶圆基板（1）上表面键合区域（14）的晶圆微凸点阵列（13）对应；所述的系统配置板（5）上集成有配置芯片（6）和接插件（7），系统配置板（5）下表面设有焊盘（8）；所述系统配置板（5）为PCB板，所述配置芯片（6）用于对集成芯粒（2）进行供电、测试、系统配置；所述的晶圆基板（1）和集成芯粒（2）通过所述晶圆微凸点阵列（13）和芯粒微凸点阵列（12）在键合区域（14）键合相连；所述的晶圆基板（1）和系统配置板（5）通过所述铜柱阵列和焊盘（8）键合相连；晶圆基板（1）和系统配置板（5）之间设有塑封层（9），用于塑封晶圆基板（1）、与晶圆基板（1）键合相连的集成芯粒（2）和铜柱阵列；所述的集成芯粒（2）之间通过所述重布线层（11）电连接；所述系统配置板（5）通过所述重布线层（11）以及铜柱阵列与集成芯粒（2）电连接；所述的系统散热模组（4）贴合在晶圆基板（1）的下表面；
其特征在于，该制备方法包括以下步骤：
步骤S1，对晶圆基板（1）进行多次图形化操作后在晶圆基板（1）表面形成多个一次图形化区域（15），所述图形化操作具体为：利用半导体前道/后道金属工艺形成晶圆基板（1）顶部的重布线层（11）、晶圆微凸点阵列（13）以及铜柱垫（10）；其中的晶圆微凸点阵列（13）形成晶圆基板（1）表面的键合区域（14）；
步骤S2，利用C2W键合工艺将集成芯粒（2）与晶圆基板（1）键合，形成集成晶圆；
步骤S3，利用厚膜光刻胶在集成晶圆表面形成≥100um的光阻层，刻蚀出铜柱（3）的位置，即铜柱孔（17）；
步骤S4，利用电镀工艺在步骤S3刻蚀出的即铜柱孔（17）处形成铜柱（3）；
步骤S5，去除光刻胶后对集成晶圆进行塑封形成塑封层（9），再减薄塑封层（9），使露出铜柱表面；
步骤S6，将铜柱（3）与系统配置板（5）下表面的焊盘（8）对准键合，再在集成晶圆底部贴合系统散热模组（4），完成晶上系统的结构。
2.如权利要求1所述的制备方法，其特征在于，所述的晶圆基板（1）为半导体晶圆，包括Si、SiC、GaN的半导体材料晶圆，尺寸≥8寸，厚度在300 um~1000um之间。
3.如权利要求1所述的制备方法，其特征在于，所述的铜柱（3）高度≥100um，径高比为1：1~1：2之间。
4.如权利要求1所述的制备方法，其特征在于，所述键合区域（14）面积小于一次图形化区域（15）的最大面积，所述一次图形化区域（15）的最大面积由键合区域（14）及其周围的铜柱阵列所占区域的面积组成，各个键合区域间距≥100um。
5.如权利要求4所述的制备方法，其特征在于，所述集成芯粒（2）为异质异构芯粒，集成芯粒（2）的面积大小≤一次图形化区域（15）的最大面积，集成芯粒（2）的厚度≤150um。
6.如权利要求1所述的制备方法，其特征在于，所述的系统散热模组（4）包括风冷散热模组、水冷散热模组、微流道散热模组。
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