CN114756814B - Variable resistor array forming method and analog matrix computing circuit based on variable resistor array forming method - Google Patents
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Abstract
The invention provides a variable resistor array forming method and an analog matrix computing circuit based on the variable resistor array forming method, and belongs to the field of semiconductors, analog computing and integrated circuits. Each row vector of the matrix of the present invention is mapped to the difference in conductance between two rows of devices in a variable resistor array, the corresponding two rows of devices being connected to the positive and negative inputs of an Operational Amplifier (OA). The positive and negative input terminals of each OA in the circuit are respectively connected with a compensation resistor, so that the sum of the conductance values of the resistor devices connected with the two input terminals is equal. The invention realizes the efficient analog computation of matrix inversion, eigenvector and matrix pseudo-inversion, reduces the time delay and hardware cost of matrix operation containing negative elements, can effectively overcome the influence of array line resistance and device difference, and has wide application prospect in the fields of signal processing, wireless communication, machine learning and the like.
Description
Technical Field
The invention provides an analog matrix calculating circuit based on a variable resistor array, which is used for calculating matrix inversion, eigenvectors and pseudo-inversion (including left inversion and right inversion) problems, in particular relates to an analog calculating circuit design based on variable resistor devices (such as a resistance variable memory, a phase change memory, a magnetic memory, a ferroelectric memory and the like), and comprises a working principle and a parameter design method thereof, and belongs to the fields of semiconductors, analog computing (analog computing) and integrated circuits (INTEGRATED CIRCUIT).
Background
Matrix operations exist in almost all scientific and engineering fields, such as scientific computing, machine learning, wireless communication, etc. In conventional digital computation, matrix operations generally have relatively high computational complexity, and in particular, matrix equation solutions are more complex, such as matrix inversion, eigenvectors, and pseudo-inverse computation, and their time complexity is generally O (n 3) (n is the matrix size). In the big data age, the scale of matrix operation in the computing task is rapidly increased, and a strong computing power demand is put on a computing system. Analog computing techniques based on variable resistor arrays are expected to provide an efficient solution for some basic matrix operations. On one hand, due to the space parallel architecture of the variable resistor array, the simulation calculation is carried out by utilizing the physical law in the array circuit, so that the calculation parallelism is high; on the other hand, thanks to the non-volatility of the variable resistance memory device, the in-situ calculation in the memory, namely the in-memory calculation, is realized based on the analog calculation of the variable resistance array, the limitation of memory and calculation separation in the traditional calculation architecture is overcome, and the calculation force and the energy efficiency of matrix calculation are further improved.
Disclosure of Invention
In order to realize efficient inversion, eigenvector and pseudo-inversion (left inversion and right inversion) operation facing the matrix containing the negative elements, the invention provides a novel variable resistor array-based analog matrix computing circuit which can execute efficient matrix inversion, eigenvector and pseudo-inversion operation and is particularly suitable for operation of the matrix containing the negative elements.
The specific technical scheme of the invention is as follows:
A method for forming a variable resistor array used for analog matrix calculation is characterized in that each row vector or column vector of the matrix is mapped into the difference of the conductivities of two rows or two columns of variable resistor devices in the variable resistor array, the corresponding two rows or two columns of variable resistor devices are connected to the positive input end and the negative input end of an operational amplifier OA, and the positive input end and the negative input end of each OA are respectively connected with a compensation resistor so that the sum of the conductivities of the variable resistor devices connected with the two input ends is equal.
The variable resistance device is a resistance change memory, a phase change memory, a magnetic memory, a ferroelectric memory and the like.
The analog computation matrix inversion circuit utilizes a group of OAs to construct global feedback and reads out inversion computation results. Each row vector of the matrix is mapped to the difference of conductance values of two rows of devices in the array, the two row lines are respectively connected with the positive input end and the negative input end of one OA, and the output end of each OA is correspondingly fed back to the column line of the variable resistor array one by one. When the circuit works, a group of voltages are applied to the row lines of the variable resistor array to represent an input vector, and the output voltage of the OA represents the calculated result of matrix inversion, namely the result of multiplication of an inverse matrix and the input vector. The conductance values of the variable resistive devices connecting all the OA positive and negative inputs form two non-negative matrices. In addition to the variable resistance devices mapping the matrix elements, there is a column of variable resistance devices as compensation resistances that sum up the conductance values of the resistance devices connecting each of the OA positive and negative inputs. One end of the compensation resistor is connected with the positive or negative input end of the OA, and the other end of the compensation resistor is grounded. Their conductance values are calculated from the row sum and the input conductance of two non-negative matrices.
The analog computation feature vector circuit is implemented based on an array of variable resistance devices. And constructing global feedback by using a group of OAs and reading out a feature vector calculation result. Each row vector of the matrix is mapped to the difference of conductance values of two rows of devices in the array, the two row lines are respectively connected with the positive input end and the negative input end of one OA, meanwhile, the output end of each OA is fed back to the column line of the variable resistor array, and the negative input end is connected with a feedback resistor for mapping the characteristic value (or the absolute value of the characteristic value) to the output end. In addition to the variable resistance devices mapping matrix elements and mapping eigenvalues, there is a column of variable resistance devices as compensation resistors that sum up the conductance values of the resistance devices (including feedback resistance devices) connecting each of the OA positive and negative inputs. One end of the compensation resistor is connected with the positive or negative input end of the OA, and the other end of the compensation resistor is grounded. Their conductance values are calculated based on the row sum and eigenvalue feedback conductances of the two non-negative matrices.
In the analog calculation eigenvector circuit, the feedback conductance of the mapping eigenvalue lambda is slightly smaller than the nominal value thereof, namely, the conductance value can be determined according to |lambda| (1-delta), delta is a positive number which is far smaller than 1, so that an output voltage reaches the maximum value allowed, and all the output voltages form the calculation result of the eigenvector.
The left inverse circuit of the analog calculation matrix is realized based on a variable resistance device array, and two groups of OAs form a feedback loop to complete calculation. Each row vector of the matrix is mapped into the difference of conductance values of two rows (or two columns) of devices in two arrays, two row lines of the first array are respectively connected with positive and negative input ends of one OA, meanwhile, the negative input end is connected with a feedback resistor to an output end, and the output end is connected to a corresponding row line of the second array; two column lines of the second array are respectively connected with positive and negative input ends of one OA, and the output end is connected with the corresponding column line of the first array in a feedback way. The input vector for the left inverse operation is mapped to a set of voltages applied to the row lines in the first array. In addition to the variable resistance devices mapping the matrix elements, there is a column (or row) of variable resistance devices as compensation resistances that sum up the conductance values of the variable resistance devices connecting each of the OA positive and negative inputs. One end of the compensation resistor is connected with the positive or negative input end of the OA, and the other end of the compensation resistor is grounded. Their conductance values are calculated from the row sum (or column sum) of the two non-negative matrices, the input conductance and the feedback conductance.
The analog calculation matrix right inverse circuit is realized based on a variable resistance device array, and two groups of OAs form a feedback loop to complete calculation. The right inverse circuit needs to map the transpose matrix into the array. Each row vector of the transposed matrix is mapped into the difference of conductance values of two rows (or two columns) of devices in two arrays, two row lines of the first array are respectively connected with positive and negative input ends of one OA, meanwhile, the negative input end is connected with a feedback resistor to an output end, and the output end is connected to a corresponding row line of the second array; two column lines of the second array are respectively connected with positive and negative input ends of one OA, and the output end is connected with the corresponding column line of the first array in a feedback way. The input vector for the right inversion operation is mapped to a set of voltages applied to the column lines in the second array. In addition to the variable resistance devices mapping transposed matrix elements, there is a column (or row) of devices as compensation resistors that sum up the conductance values of the resistive devices connecting each of the OA positive and negative inputs. One end of the compensation resistor is connected with the positive or negative input end of the OA, and the other end of the compensation resistor is grounded. Their conductance values are calculated from the row sum (or column sum) of the two non-negative matrices, the input conductance and the feedback conductance.
The right inverse circuit main body and the left inverse circuit are different in that: first, a right inverse circuit maps the transpose of the matrix to two variable resistor arrays; second, the voltage representing the input vector is applied to the input resistor on the column line of the second array; third, the output voltages of the first set of OA represent the result vector of the right inverse computation, i.e., the result of multiplying the input vector by the right inverse matrix.
The matrix inversion, eigenvector and pseudo-inverse calculation circuit is particularly suitable for the operation of a matrix containing negative elements, and can be used for the operation of a non-negative matrix. Because the line resistance effects on the row line or the column line connected with the positive input end and the negative input end of the OA cancel each other out, the series of circuits can effectively overcome the influence of the array line resistance on the calculation result.
The beneficial effects of the invention are as follows:
the invention provides a variable resistor array-based analog calculation circuit facing basic matrix operation, which can execute efficient matrix inversion, eigenvector and pseudo-inversion operation, and is particularly suitable for operation of a matrix containing negative elements. Compared with other analog computing circuits facing negative element matrix correlation operation, the circuit has higher circuit area efficiency, lower computing delay and lower energy consumption. In addition, the parallel input line resistance effects cancel each other, so that the matrix multiplication circuit can effectively relieve the influence of line resistance and non-ideal factors of devices on a calculation result.
Drawings
Fig. 1 is a block diagram of the kth line of the analog computation matrix inversion circuit of the present invention.
Fig. 2 is a block diagram of an analog computation matrix inversion circuit of the present invention.
Fig. 3 is an example of the negative element-containing matrix factorization method and compensation conductance calculation method of the present invention.
FIG. 4 is a block diagram of a simulated computing matrix eigenvector circuit of the present invention.
Fig. 5 is a circuit configuration diagram of the pseudo-inverse (left inverse) of the analog computation matrix of the present invention.
Fig. 6 is a circuit configuration diagram of the pseudo-inverse (right inverse) of the analog computation matrix of the present invention.
Detailed Description
In order to more clearly clarify the objects, technical solutions and advantages of the present invention, a further detailed description will be given below with reference to the accompanying drawings. The description herein is only for the purpose of illustrating the invention and is not to be construed as limiting the invention.
The invention provides a variable resistor array-based analog calculation matrix inversion, eigenvector and pseudo-inversion (left inversion and right inversion) circuit, which is particularly suitable for the correlation operation of a matrix containing negative elements, and is realized based on the principles of feedback loops and OA positive and negative input end conductance compensation.
Fig. 1 is a circuit configuration diagram of a kth row of an analog computation matrix inversion circuit based on a variable resistor array, where a kth row vector a k of the matrix is mapped to a difference between conductivities of two rows of variable resistor devices, a relationship between a row vector a k and a vector B k、Ck represented by conductivities of two rows of devices is a k＝Bk-Ck, the two rows of devices are respectively connected to negative and positive input terminals of an OA, an output terminal of the OA is feedback connected to the kth column, and the kth element is used as an output vector. To ensure that the sign of the calculation result is correct, the input vector is inverted in advance in the present invention, i.e., input-y, represented by the voltage (-y k) applied to the negative input of each row OA. The input vector is converted into a current value through an input resistor to participate in operation. The output voltages of the n OA's constitute a column vector x. In the present invention, the agreed input conductance is the unit conductance, i.e. g 0 =1, and the conductance value of the other resistor device is the ratio divided by the input conductance.
In FIG. 1, according to kirchhoff's current law, the potentials at the OA positive and negative inputs are respectivelyAnd Where Δs bk、Δsck is the compensation conductance of conductance row vector B k、Ck, respectively. Due to the "virtual short" nature of OA, the potentials at the positive and negative inputs are equal, i.e./>By choosing the appropriate Δs bk、Δsck so that they satisfy Σ jBkj+Δsbk+1＝∑jCkj+Δsck, then there is-y k+Bkx＝Ck x, resulting in equation (1) in fig. 1, i.e. the circuit must satisfy
yk＝(Bk-Ck)x＝Akx. (1)
In a practical circuit, the compensated conductance sum is difficult to be exactly equal, and the equation (1) is approximately established considering the approximate equality, i.e., Σ jBkj+Δsbk+1≈∑jCkj+Δsck.
For an n×n real matrix a, it can be decomposed with two non-negative matrices B and C, i.e. a=b-C. After conducting conductance compensation of the row summation of the variable resistance devices mapped by the B and the C, the corresponding variable resistance array circuit can calculate any matrix inversion operation. In FIG. 2, the potential at either one of the OA positive and negative inputs satisfies Synthesizing n equations to obtain the matrix form/>Where U B、UC is a diagonal matrix, UB＝diag(∑jB1j+Δsb1+1,∑jB2j+Δsb2+1,…,∑jBnj+Δsbn+1)、UC＝diag(∑jC1j+Δsc1,∑jC2j+Δsc2,…,∑jCnj+Δscn). is provided by selecting appropriate compensation conductances Δs bk and Δs ck for U B＝UC, then there is-y+bx=cx, i.e., y= (B-C) x=ax, and to satisfy this equation, the output vector x must satisfy equation (2) in fig. 2, i.e.
x＝(B-C)-1y＝A-1y. (2)
Where A -1 is the inverse of matrix A. Thus, the circuit of FIG. 2 may implement a matrix inversion calculation function. If the compensated conductance sums are approximately equal, i.e., Σ jBkj+Δsbk+1≈∑jCkj+Δsck, then equation (2) is approximately true.
Fig. 3 shows an example of decomposing a real matrix a into two non-negative matrices B and C, assuming that a contains negative elements. The decomposition method is characterized in that non-negative elements of A are correspondingly reserved in B one by one, and elements at other positions of B are 0; the negative elements of A are reserved in C in one-to-one correspondence after being inverted, and the elements at other positions of C are 0. The mathematical expression of this method isWhere |a| represents taking absolute value for the elements of matrix a. After the non-negative matrices B and C are obtained, the row sums s B and s C of the two are calculated, as well as the differences between them. Since the negative OA input terminal is connected with the input resistor, its conductance value is 1, and the sum difference of the conducions is Δs=s C-1-sB. Finally, the compensation conductance is calculated according to the result of delta s, and one value mode is/>
Fig. 4 is a block diagram of a simulation calculation matrix eigenvector circuit based on a variable resistor array. The size of the matrix A is n multiplied by n, each row vector of the matrix A is mapped into the difference of the conductance of two rows of variable resistance devices, the two rows of devices are respectively connected to the positive input end and the negative input end of one OA, the output ends of the OA are in feedback connection to the column lines of the variable resistance array in a one-to-one correspondence mode, namely the OA on the kth row of the matrix A is connected to the kth column. The conductance values of the variable resistance devices connected with the positive and negative input ends of all the OA respectively form non-negative matrixes B and C, so as to meet a=b-C. In addition, a feedback resistor (the conductance of which is g λ) for mapping the characteristic value is connected from the negative input end to the output end of each OA, and a compensation resistor is connected to the positive and negative input ends of each OA. According to kirchhoff current law and the 'virtual short' property of OA, the potential of any one of the positive and negative OA input ends meets the following conditionsWhere x is the column vector of the output voltages of n OA, Δs bk、Δsck is the compensation conductance of conductance row vector B k、Ck, k=1, 2. Synthesizing n equations to obtain the matrix form/>Where U B、UC is a diagonal matrix, UB＝diag(∑jB1j+Δsb1,∑jB2j+Δsb2,…,∑jBnj+Δsbn)、UC＝diag(∑jC1j+Δsc1+gλ,∑jC2j+Δsc2+gλ,…,∑jCnj+Δscn+gλ)., respectively, and U B＝UC is obtained by selecting appropriate compensation conductivities Δs bk and Δs ck, then bx=λx+cx, to obtain equation (3) in fig. 4, i.e
λx＝(B-C)x＝Ax. (3)
In order to satisfy equation (3), the output voltage vector must be a eigenvector of λ. Thus, the circuit of FIG. 4 may implement a matrix eigenvector calculation function. If the compensated conductance sums are approximately equal, i.e., Σ jBkj+Δsbk≈∑jCkj+Δsck+gλ, then equation (3) is approximately true.
Fig. 5 is a circuit diagram of a pseudo-inverse (left inverse) of a matrix calculated based on simulation of variable resistor arrays, where the size of matrix a is n×m (n > m), which is mapped in two variable resistor arrays, and two sets of OA are used to form a feedback loop. In the first variable resistor array (the left variable resistor array in the figure), each row vector of the matrix a is mapped to the difference between the conductivities of two rows of variable resistor devices, the two rows of devices are respectively connected to the positive and negative input terminals of an OA, the negative input terminal of the OA is connected to a feedback resistor (the conductivities are g 0) to the output terminal, and the positive and negative input terminals are respectively connected to a compensation resistor. The conductance values of the variable resistance devices connected with the positive and negative input ends of all the OA respectively form non-negative matrixes B and C, so as to meet a=b-C. The input vector y is represented by the voltage applied to the negative input of each row OA, which is converted to a current value via an input resistor to participate in the operation. The output voltages of the n OA's constitute a column vector r, which is applied as input to the row lines of the second variable resistor array.
In the second variable resistor array (the right variable resistor array in the figure), each column vector of the matrix a is mapped to the difference in conductance between two columns of variable resistor devices, which are connected to the positive and negative input terminals of an OA respectively, and also connected to a compensation resistor respectively. The conductance values of the variable resistor devices connected to the positive and negative inputs of all OA constitute the same non-negative matrices C and B, respectively, as in the first variable resistor array. The output voltages of the m OA's constitute a column vector x, which is applied as input to the column line of the first variable resistor array.
In the first variable resistor array, according to kirchhoff current law and the 'virtual short' property of OA, the potential of any one of the positive and negative OA input ends meets the following conditionsWhere Δs b1k、Δsc1k is the compensation conductance of conductance vector B k、Ck, k=1, 2,..n. Synthesizing n equations to obtain the matrix form/>Where U B1、UC1 is a diagonal matrix, UB1＝diag(∑jB1j+Δsb11,∑jB2j+Δsb12,…,∑jBnj+Δsb1n)、UC1＝diag(∑jC1j+Δsc11+2,∑jC2j+Δsc12+2,…,∑jCnj+Δsc1n+2). is obtained by selecting appropriate compensation conductivities Δs b1k and Δs c1k for U B1＝UC1, then bx=r+y+cx, to obtain equation (4) in fig. 5, i.e
r＝(B-C)x-y＝Ax-y. (4)
In the second variable resistor array, the potential of any one of the positive and negative OA input terminals satisfiesWherein Δs b2l、Δsc2l are respectively the electrical rank vectors/>I=1, 2,..m. Synthesizing m equations to obtain the matrix form/>Where U B2、UC2 is a diagonal matrix, UB2＝diag(∑jBj1+Δsb21,∑jBj2+Δsb22,…,∑jBjm+Δsb2m)、UC2＝diag(∑jCj1+Δsc21,∑jCj2+Δsc22,…,∑jCjm+Δsc2m)., respectively, and U B2＝UC2 is obtained by selecting the appropriate Δs b2l、Δsc2l to obtain B Tr＝CT r, equation (5) in FIG. 5:
(BT-CT)r＝ATr＝0. (5)
A T·Ax＝AT y is obtained by combining the formulas (4) and (5), and in order to satisfy the formula, the output vector x should satisfy the formula (6) in FIG. 5, namely
x＝(AT·A)-1·ATy. (6)
Where (A T·A)-1·AT is the left inverse of matrix A. Thus, the circuit of FIG. 5 may implement the matrix left inverse calculation function. If the compensated conductance sums are approximately equal, i.e., ∑jBkj+Δsb1k≈∑jCkj+Δsc1k+2、∑jBjl+Δsb2l≈∑jCjl+Δsc2l,, then equation (6) is approximately true.
Fig. 6 is a circuit structure diagram of the right inverse of the analog computation matrix based on the variable resistor arrays, and its main body is the same as the left inverse circuit of the matrix of fig. 5, i.e. two variable resistor arrays form a feedback loop through two groups of OA. Unlike the left inverse circuit, the two variable resistor arrays in this circuit are mapped to a transpose of matrix a, a T. The size of the original matrix A is m×n (n > m). In the present invention, the input vector, i.e., input-y, is previously inverted, and is expressed as a voltage applied to the column line of the second variable resistor array, and is converted into a current value through the input resistor to participate in the operation. The output vector r of the second variable resistor array is applied as input to the column line of the first variable resistor array. The output voltage of OA on the row line of the first variable resistor array forms a vector x.
In the first variable resistor array, the potential of any one of the positive and negative OA input terminals satisfiesWherein Δs b1l、Δsc1l are respectively the electrical conductance vector/>I=1, 2,..m. Synthesizing m equations to obtain the matrix form/>Wherein U B1、UC1 is a diagonal matrix, UB1＝diag(∑jBj1+Δsb11,∑jBj2+Δsb12,…,∑jBjm+Δsb1m)、UC1＝diag(∑jCj1+Δsc11+1,∑jCj2+Δsc12+1,…,∑jCjm+Δsc1m+1)., and U B1＝UC1 is obtained by selecting appropriate compensation conductivities Δs b1l and Δs c1l, then B Tr＝y+CT r is present, which yields equation (7) in FIG. 6
x＝(BT-CT)r＝ATr (7)
In the second variable resistor array, the potential of the positive and negative input ends of any one OA satisfies Synthesizing n equations to obtain the matrix form/>Wherein U B2、UC2 is a diagonal matrix, UB2＝diag(∑jB1j+Δsb21+1,∑jB2j+Δsb22+1,…,∑jBnj+Δsb2n+1)、UC2＝diag(∑jC1j+Δsc21,∑jC2j+Δsc22,…,∑jCnj+Δsc2n)., respectively, and U B2＝UC2 is obtained by selecting appropriate compensation conductivities Δs b2k and Δs c2k to obtain formula (8) in FIG. 6, namely
y＝(B-C)x＝Ax (8)
Combining equations (7), (8) yields y=a·a T r, in order to satisfy this equation, r must satisfy r= (a·a T)-1 y, so that output vector x must satisfy equation (9) in fig. 6, i.e.
x＝AT·(A·AT)-1y. (9)
Where A T·(A·AT)-1 is the right inverse of matrix A. Thus, the circuit of FIG. 6 may implement a matrix inverse right calculation function. Equation (9) is approximately true if the compensated conductance sums are approximately equal, ∑jBjl+Δsb1l≈∑jCjl+Δsc1l+1、∑jBkj+Δsb2k+1≈∑jCkj+Δsc2k,.
Finally, it should be noted that the examples are disclosed for the purpose of aiding in the further understanding of the present invention, but those skilled in the art will appreciate that: various alternatives and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the disclosed embodiments, but rather the scope of the invention is defined by the appended claims.
Claims (6)
1. A method for forming a variable resistor array used for analog matrix calculation is characterized in that each row vector or column vector of the matrix is mapped into the difference of the conductivities of two rows or two columns of variable resistor devices in the variable resistor array, the corresponding two rows or two columns of variable resistor devices are connected to the positive input end and the negative input end of an operational amplifier OA, and the positive input end and the negative input end of each OA are respectively connected with a compensation resistor so that the sum of the conductivities of the variable resistor devices connected with the two input ends is equal.
2. The variable resistance array construction method according to claim 1, wherein the variable resistance device is a resistance change memory, a phase change memory, a magnetic memory, or a ferroelectric memory.
3. An analog calculation matrix inversion circuit is characterized in that each row vector of a matrix is expressed as the difference of two non-negative real row vectors, the two row vectors are respectively mapped to the conductance values of two rows of variable resistance devices in the variable resistance array according to claim 1, two row lines in the variable resistance array are respectively connected to the positive input end and the negative input end of an operational amplifier OA, the conductance values of the variable resistance devices connected with the positive input end and the negative input end of all the OAs form two non-negative matrices, and the output end of each OA is in feedback connection with the column line of the variable resistance array in a one-to-one correspondence manner; the compensation resistor is a column of variable resistor devices, one end of the compensation resistor is connected with the positive or negative input end of the OA, the other end of the compensation resistor is grounded, and the conductance value of the compensation resistor is obtained by pre-calculating the row sum of two non-negative matrixes; when the circuit works, a group of voltages are applied to the row lines of the variable resistor array to represent an input vector, and the output voltage of the OA represents the calculated result of matrix inversion, namely the result of multiplication of an inverse matrix and the input vector.
4. An analog calculation eigenvector circuit, wherein each row vector of the matrix is expressed as a difference between two non-negative real row vectors, the two row vectors are respectively mapped into conductance values of two rows of devices in the variable resistor array according to claim 1, the two row lines in the corresponding variable resistor array are respectively connected to positive and negative input ends of one OA, the conductance values of the variable resistor devices connected with the positive and negative input ends of all OAs form two non-negative matrices, and a feedback resistor for mapping eigenvalue lambda is connected from the output end to the negative input end of each OA; the compensation resistor is a column of grounded variable resistor device, and the conductance value of the compensation resistor is obtained by pre-calculating the row sum of two non-negative matrixes; in operation of the circuit, the output voltage of the OA represents the result of the feature vector calculation.
5. A left inverse circuit for analog computation matrix, wherein the matrix is mapped to two variable resistor arrays according to claim 1, two groups of OA are utilized to form a feedback loop, each row vector of the matrix is represented as a difference between two non-negative real row vectors, the two row vectors are mapped to conductance values of two rows of variable resistor devices in the variable resistor array, and the corresponding two row lines are respectively connected to positive and negative input ends of the first group of OA; in the second variable resistor array, each column vector of the matrix is expressed as a difference of two non-negative real column vectors, the two column vectors are mapped into conductance values of two columns of devices in the variable resistor array, the two column lines are respectively connected to positive and negative input ends of one of the second group of OAs, the output end to the negative input end of the first group of OAs are respectively connected with a feedback resistor, the output end of each OA is connected to a corresponding row line of the second variable resistor array, and the output end of the second group of OAs is connected to a corresponding column line of the first variable resistor array in a feedback manner; the compensation resistors are a column or a row of grounded variable resistor devices, and the conductance values of the first group of compensation resistors and the second group of compensation resistors are respectively obtained by pre-calculating row addition or column addition of two non-negative matrixes, and calculating input conductance and feedback conductance; in operation of the circuit, voltages representing input vectors are applied to the input resistors on the row lines of the first variable resistor array, and the output voltages of the second set of OA represent the resulting vectors of the left inverse calculations, i.e. the result of the multiplication of the left inverse matrix with the input vectors.
6. A right inverse circuit of an analog computation matrix, characterized in that a transpose of the matrix is mapped to two variable resistor arrays in the left inverse circuit of an analog computation matrix according to claim 5, the circuit being operative in that a voltage representing an input vector is applied to an input resistor on a column line of the second variable resistor array; the output voltages of the first set of OA represent the result vector of the right inverse calculation, i.e. the result of the multiplication of the right inverse matrix with the input vector.
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