CN114282164B - Analog calculation matrix multiplication circuit and application thereof in DFT/IDFT - Google Patents
Analog calculation matrix multiplication circuit and application thereof in DFT/IDFT Download PDFInfo
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Abstract
The invention provides an analog computation matrix multiplication circuit and application thereof in DFT/IDFT, wherein the circuit represents each row vector of a real matrix as the difference of conductance of two rows of devices in a variable resistance device array, and the corresponding two row lines are respectively connected to the positive input end and the negative input end of an operational amplifier OA, and the negative input end is connected with a feedback resistor to the output end. The positive and negative input ends of each OA are connected with a compensation resistor so that the sum of the conductance values of the resistor devices (including feedback resistors) connected with the positive and negative input ends of each OA is equal to ensure that the OA outputs the correct product result. The present invention applies this circuit to Discrete Fourier Transform (DFT) and inverse transform (IDFT), and designs the compensation conductance values that need to be employed when mapping the DFT/IDFT matrix to the variable resistor array. The invention realizes the efficient analog calculation of arbitrary real matrix multiplication, reduces the time delay and hardware cost of matrix operation containing negative elements, and has wide application prospect in the fields of signal processing, wireless communication, machine learning and the like.
Description
Technical Field
The invention belongs to the field of semiconductors, analog computing (analog computing) and integrated circuits (INTEGRATED CIRCUIT), relates to an analog computing matrix multiplication circuit, in particular to an analog computing circuit design based on variable resistance devices (such as a resistance change memory, a phase change memory, a magnetic memory, a ferroelectric memory and the like), comprising a working principle and a parameter design method thereof, and typical application of the analog computing circuit design in discrete Fourier transform and inverse transform.
Background
Matrix multiplication is a core operation of many important applications and algorithms, such as fourier transform and inverse transform in signal processing, feed-forward reasoning of neural networks, etc. In traditional digital computing, matrix multiplication has relatively high computational complexity, such as the time complexity of multiplication between matrices and vectors is O (n 2) (n is the matrix size), and therefore, the data-intensive computing task in the big data age places a strong computational power demand on the computing system. Analog computing techniques based on arrays of variable resistance devices are expected to provide an efficient solution for matrix multiplication operations. On the one hand, due to the space parallel architecture of the variable resistance device array, the simulation calculation is carried out by utilizing the physical law in the array circuit, so that the calculation parallelism is high, and the matrix multiplication operation of O (1) time complexity can be realized. On the other hand, due to the non-volatility of the variable resistance memory device, the in-situ calculation in the memory, namely the in-memory calculation, is realized based on the analog calculation of the variable resistance device array, the limitation of memory and calculation separation in the traditional calculation architecture is overcome, and the calculation force and the energy efficiency of matrix multiplication operation are further improved.
Currently, one major implementation of analog matrix multiplication is to read out the product result using a transimpedance amplifier (TIA). However, since the device conductance can only be positive, the method is mainly applied to the multiplication operation (M.Hu,J.P.Strachan,Z.Li,R.S.Williams,Crossbar arrays for calculating matrix multiplication,US Patent 10497440B2,2019). of the positive matrix, for the matrix containing the negative elements, it can be decomposed into two positive matrices, then analog matrix multiplication operation is performed respectively, and then the peripheral circuit or program performs differential calculation to obtain the product result (N.Muralimanohar,B.Feinberg,A.Shafiee-Ardestani,Vector-matrix multiplications involving negative values,US Patent 9910827B2,2018).. These methods inevitably increase computation delay and hardware overhead. In order to realize efficient multiplication operation for any real matrix, new design and research are needed for an analog computing circuit.
Disclosure of Invention
The invention aims to provide an analog calculation matrix multiplication circuit for realizing high-efficiency oriented to any real matrix and an application of the analog calculation matrix multiplication circuit in DFT/IDFT.
The technical scheme provided by the invention is as follows:
the analog computation matrix multiplication circuit based on the variable resistor device array is characterized in that for an n×m real number matrix, the analog computation matrix multiplication circuit comprises a 2n×m variable resistor device array and n operational amplifiers OA, each row vector of any real number matrix is represented as a difference of two non-negative real number row vectors, the difference is respectively mapped to the conductance values of two rows of devices in the variable resistor device array, two row lines in the corresponding variable resistor device array are respectively connected to the positive input end and the negative input end of one operational amplifier OA, the negative input end is connected with a feedback resistor to the output end, the conductance values of the variable resistor device array connected with the positive input end and the negative input end of all the operational amplifiers OA respectively form two non-negative matrixes, when the circuit works, a group of voltages are applied to column lines of the variable resistor device array to represent the input vector of matrix multiplication, and the output voltage of the operational amplifier OA represents the computation result of matrix multiplication.
When the number of the matrix lines n=1, the analog calculation matrix multiplication circuit calculates the inner product between two arbitrary real vectors; when the number of rows n=1 and the number of columns m=1, the analog calculation matrix multiplication circuit calculates the product between two arbitrary real numbers.
In the variable resistor device array of the analog calculation matrix multiplication circuit, besides the variable resistor devices of the mapping matrix elements, a column of variable resistor devices are used as compensation resistors, one end of each compensation resistor is connected with the positive or negative input end of an OA, the other end of each compensation resistor is grounded, and the conductance values of the resistor devices (including feedback resistors) connected with the positive and negative input ends of each OA are added and equal.
The conductance value of the compensation resistor is calculated according to the difference of the row sums of the two non-negative matrixes, wherein the row sum of the non-negative matrixes corresponding to the OA negative input end contains the conductance value of the feedback resistor.
The invention further provides a discrete fourier transform DFT and inverse transform IDFT calculation method. The method is characterized in that an analog calculation matrix multiplication circuit is constructed, and the real part and the imaginary part of the DFT/IDFT matrix are mapped in the variable resistor device array together. In the DFT/IDFT implementation, the real part matrix of the n multiplied by n DFT or IDFT matrix is mapped into two variable resistor sub-arrays of 2n rows and n columns by a conductivity difference method, the imaginary part matrix and the inverse matrix thereof are respectively mapped into the two variable resistor sub-arrays of 2n rows and n columns to form an array of 4n rows and 2n columns together, and 2n OAs are needed. The real part and the imaginary part of the input vector of DFT/IDFT are applied to 2n column lines at the same time, and the output voltage of OA represents the real part and the imaginary part of the DFT/IDFT result.
In the DFT/IDFT analog calculation circuit, the compensation conductance of the negative input ends of the 1 st and n+1st OAs is (n-1) times of the feedback conductance, and the compensation conductance of the positive input ends of other OAs is the same as the feedback conductance.
The beneficial effects of the invention are as follows:
the invention is realized based on an array of variable resistance devices (such as a resistive random access memory, a phase change memory, a magnetic memory, a ferroelectric memory, etc.), and the product result is read out by a group of feedback Operational Amplifiers (OA). Each row vector of the matrix is mapped to the difference of conductance values of two rows of variable resistors in the array, the two row lines are respectively connected with positive and negative input ends of one OA, and the negative input end is connected with one feedback resistor to the output end. The conductance values of the variable resistance devices connected to the positive and negative inputs of all OA respectively form two non-negative matrices. The vector inputs of the matrix multiplication are mapped to a set of voltages applied on the column lines in the array. The analog calculation matrix multiplication circuit based on the variable resistance device array can execute multiplication operation of any real matrix, and is particularly suitable for operation of a matrix containing negative elements. The circuit has higher circuit area efficiency, lower computation delay and lower energy consumption than other analog computation circuits or methods facing negative element matrix multiplication operations. In addition, the parallel input line resistance effects cancel each other out, so that the matrix multiplication circuit can effectively relieve the influence of the line resistance on a calculation result.
Meanwhile, the invention provides an efficient DFT/IDFT analog calculation method, which can realize one-step calculation based on the analog calculation matrix multiplication circuit. In addition, because of the variable resistance device array structure, the circuit is relatively simple to realize, and the row summation of two nonnegative matrixes obtained by decomposition does not need to be calculated in advance.
Drawings
FIG. 1 is a circuit block diagram of the present invention for calculating the inner product of two vectors containing negative elements;
FIG. 2 is a circuit block diagram of the present invention for computing a negative element-containing matrix multiplication;
FIG. 3 is an example of a negative element-containing matrix factorization method and compensation conductance calculation method of the present invention;
FIG. 4 is a schematic diagram of another method of negative element-containing matrix decomposition and corresponding compensation conductance calculation;
FIG. 5 is a DFT matrix synthesis method suitable for use in a variable resistance device array matrix multiplication circuit;
FIG. 6 is a mapping of a composite DFT matrix of the present invention to an array of variable resistance devices and the resulting addition of two non-negative matrix rows;
fig. 7 is a block diagram of a DFT computation circuit based on a variable resistance device array according to the present invention.
Detailed Description
In order to more clearly clarify the objects, technical solutions and advantages of the present invention, a further detailed description will be given below with reference to the accompanying drawings. The description herein is only for the purpose of illustrating the invention and is not to be construed as limiting the invention.
The invention provides an analog calculation matrix multiplication circuit based on a variable resistance device array, and provides a DFT/IDFT calculation method based on the matrix multiplication circuit. The circuit is suitable for multiplication operation of any real number matrix, especially a matrix containing negative elements, and is realized based on the idea of conductance compensation of a positive input end and a negative input end of a feedback Operational Amplifier (OA).
Fig. 1 is a graph of the inner product between two real vectors based on simulation of an array of variable resistance devices, where one vector (assumed to be the row vector a k of a matrix) maps to the difference in conductance between two rows of variable resistance devices and the other vector x is represented by the voltage applied on the column line. The relationship between row vector a k and vector B k、Ck, represented by the conductance of two rows of devices, a k＝Bk-Ck, is connected to the positive and negative inputs of one OA, respectively. In addition, the negative input end of the OA is also connected with a feedback resistor, and the positive input end and the negative input end are respectively connected with a compensation resistor. In the invention, the conductance value of the feedback resistor is defined as the unit conductance, namely g 0 =1, and the conductance value of other resistor devices is the ratio of dividing the conductance value by the feedback conductance.
In FIG. 1, according to kirchhoff's voltage law, the potentials at the OA positive and negative inputs are respectivelyYang (Yang)Where Δs bk、Δsck is the compensation conductance of conductance row vector B k、Ck, respectively. Due to the "virtual short" nature of OA, the potentials at the positive and negative inputs are equal, i.eBy choosing the appropriate Δs bk、Δsck so that they satisfy Σ jBkj+Δsbk＝∑jCkj+Δsck +1, then there is B kx＝ckx+yk, resulting in equation (1) in fig. 1, i.e
yk＝(Bk-Ck)x＝Akx. (1)
In an actual circuit, the compensated conductance sum is difficult to be exactly equal, and the equation (1) is approximately established considering the approximate equality, i.e., Σ jBkj+Δsbk≈∑jCkj+Δsck +1.
For a real matrix a with n rows, it can be decomposed with two non-negative matrices B and C, i.e. a=b-C. After conducting the conductance compensation of the row summation of the variable resistance devices mapped by B and C, the corresponding variable resistance device array circuit can calculate the multiplication operation of any real matrix. In FIG. 2, the potential at either one of the OA positive and negative inputs satisfiesSynthesizing n equations to obtain a matrix formWherein U B、UC is a diagonal matrix, UB＝diag(∑jB1j+Δsb1,∑jB2j+Δsb2,…,∑jBnj+Δsbn)、Uc＝diag(∑jc1j+Δsc1+1,∑jc2j+Δsc2+1,…,∑jCnj+Δscn+1),y is an output column vector. By choosing appropriate compensation conductances Δs bk and Δs ck to give U B＝UC, then bx=cx+y, equation (2) in fig. 2 is obtained, i.e
y＝(B-C)x＝Ax. (2)
If the compensated conductance sums are approximately equal, i.e., Σ jBkj+Δsbk≈∑jCkj+Δsck +1, then equation (2) is approximately true.
Fig. 3 shows an example of decomposing a real matrix a into two non-negative matrices B and C, assuming that a contains negative elements. The most direct decomposition method is that non-negative elements of A are correspondingly reserved in B one by one, and elements at other positions of B are 0; the negative elements of A are reserved in C in one-to-one correspondence after being inverted, and the elements at other positions of C are 0. The mathematical expression of this method is Where |a| represents taking absolute value for the elements of matrix a. After the non-negative matrices B and C are obtained, the row sums s B and s C of the two are calculated, as well as the differences between them. Since the negative input terminal of OA is connected with the feedback resistor, its conductance value is 1, and the sum difference of conductance is Δs=s C+1-sB. Finally, the compensation conductance is calculated according to the result of delta s, and one value mode is that
Fig. 4 shows another method of decomposing matrix a into non-negative matrices, and another way of compensating for conductance values. To avoid the matrices B and C taking 0's at certain positions, all elements of both matrices may be added with a positive number, e.g. 1, ensuring that both matrices are positive, better mapping to the conductance value of the variable resistance device. It should be noted that even through this addition operation, the difference between the two matrix row sums does not change, and then is based on The compensation conductance is calculated. Also, to avoid that Δs B and Δs c take 0's at some positions, all elements of both may be added with a positive number, e.g. 1.
For a signal sequence with n points, the Discrete Fourier Transform (DFT) from time domain to frequency domain isDFT can be expressed as a multiplication of an n by n matrix, i.e., y=ax, where A is a complex matrix with elements in the kth row, the jth column beingX and y are complex vectors. The complex matrix multiplication operation can be converted into real number domain, and calculated by using the matrix multiplication circuit of the invention. Synthesizing a 2n x 2n real matrix based on complex matrix AComplex vector x is expressed asThen the multiplication between the two results inThe complex vector y is restored. Taking a 16 x 16 DFT matrix as an example, fig. 5 shows the converted real matrix M, which has a size of 32 x 32.
The matrix M contains negative elements, and the result of mapping two non-negative matrices B and C (both of size 2n×2n) to the variable resistor device array is shown in fig. 6 (a), with reference to the matrix decomposition method in fig. 4, for a total of 4n rows and 2n columns. The row summation results for matrices B and C are shown in fig. 6 (B). It can be seen that the row sums for rows B and C1 (corresponding to rows i, 2 in fig. 6 (B)) are n and 0, respectively, as are the n+1th row (corresponding to rows 2n+1, 2n+2 in fig. 6 (B), all other row sums being equal. This feature saves prior row sum and compensation conductance estimates for DFT calculations based on the inventive circuit, and maximizes the matrix multiplication efficiency of the inventive circuit.
Inverse Discrete Fourier Transform (IDFT) of a sequence of n-point signals, which is similar in form to DFT, i.eThe elements of the kth row and the jth column of the IDFT matrix areBased on the same method as DFT, it can be mapped into a variable resistance device array of 4n rows and 2n columns to realize matrix multiplication operation. Similarly, due to the special structure of the IDFT matrix, the IDFT calculation based on the circuit of the invention does not require pre-calculation of row summation and compensation conductance.
Fig. 7 is a circuit configuration diagram of a calculation DFT/IDFT by using the analog calculation matrix multiplication circuit of the present invention. Taking DFT calculations as an example, the graph shows the compensation conductance employed. It can be seen that the other compensation resistors are connected to the OA positive input except for two compensation resistors with conductance value (n-1) g 0, and the conductance value g 0. In fig. 7, the real and imaginary parts of the vector x are denoted by a and b, respectively, and the real and imaginary parts of the vector y are denoted by c and d, respectively.
The above-described embodiments are not intended to limit the invention, and various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention is therefore defined in the claims.
Claims (8)
1. An analog computation matrix multiplication circuit is characterized in that for an n×m real number matrix, the analog computation matrix multiplication circuit comprises a 2n×m variable resistor device array and n operational amplifiers OA, each row vector of any real number matrix is expressed as a difference of two non-negative real number row vectors, the difference is respectively mapped to the conductance values of two rows of devices in the variable resistor device array, two row lines in the corresponding variable resistor device array are respectively connected to the positive input end and the negative input end of one operational amplifier OA, meanwhile, the output end to the negative input end of each operational amplifier OA are connected with a feedback resistor, the conductance values of the variable resistor device array connected with the positive input end and the negative input end of all the operational amplifiers OA respectively form two non-negative matrixes, when the circuit works, a group of voltages are applied to column lines of the variable resistor device array to represent the input vector of matrix multiplication, and the output voltage of the operational amplifier OA represents the calculation result of matrix multiplication.
2. An analog computing matrix multiplication circuit according to claim 1, wherein the variable resistance device is a resistive memory, a phase change memory, a magnetic memory, or a ferroelectric memory.
3. A matrix multiplication circuit according to claim 1 wherein an additional column of variable resistance devices is added as compensation resistors, one end of which is connected to the positive or negative input of the operational amplifier OA and the other end is grounded.
4. A analog computation matrix multiplication circuit as claimed in claim 3, wherein the conductance values of said compensation resistors are calculated from the difference between the row sums of the two non-negative matrices such that the sum of the conductance values of the resistor devices connected to the positive and negative inputs of each operational amplifier OA is equal.
5. The analog computation matrix multiplication circuit of claim 1, wherein when the number of matrix rows n = 1, an inner product between two arbitrary real vectors is computed; when the number of rows n=1 and the number of columns m=1 of the matrix, the product between two arbitrary real numbers is calculated.
6. A discrete fourier transform DFT and inverse transform IDFT calculation method, characterized by constructing the analog computation matrix multiplication circuit according to claim 1, wherein the discrete fourier transform DFT and inverse transform IDFT are expressed as a multiplication of an n×n matrix, the real part and the imaginary part of which are mapped together in the variable resistance device array.
7. The method of discrete fourier transform DFT and inverse transform IDFT computation of claim 6, wherein in DFT/IDFT computation, a real part matrix of an n×n DFT or IDFT matrix is mapped to two variable resistor element sub-arrays of 2n rows and n columns by a conductance difference method, an imaginary part matrix and an inverse matrix thereof are mapped to two variable resistor element sub-arrays of 2n rows and n columns, respectively, to form an array of 4n rows and 2n columns together, 2n OA's are required, real parts and imaginary parts of input vectors of DFT/IDFT are applied to 2n column lines at the same time, and output voltages of operational amplifier OA represent real parts and imaginary parts of DFT/IDFT results.
8. A discrete fourier transform DFT and inverse transform IDFT computation method as recited in claim 7, wherein in DFT/IDFT computation, the compensation conductance of the negative input terminal connecting 1 st and n+1st OA is n-1 times the feedback conductance, and the compensation conductance of the positive input terminal of the other operational amplifier OA is the same as the feedback conductance.
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