CN103941068A - On-chip sensor for measuring threshold voltage drifting - Google Patents
On-chip sensor for measuring threshold voltage drifting Download PDFInfo
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- CN103941068A CN103941068A CN201310024231.1A CN201310024231A CN103941068A CN 103941068 A CN103941068 A CN 103941068A CN 201310024231 A CN201310024231 A CN 201310024231A CN 103941068 A CN103941068 A CN 103941068A
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Abstract
The invention relates to an on-chip sensor for measuring threshold voltage drifting. The sensor comprises a test circuit, a reference circuit and a subtracter circuit. The reference circuit and the test circuit are connected in parallel between power supply voltages and a grounding position; the output ends of the test circuit and the reference circuit are respectively in electrical connection with the input end of the subtracter circuit; the test circuit comprises a transistor to be tested and an antenna structure; the antenna structure is connected with the grid electrode of the transistor to be tested; and the subtracter circuit is used for measuring drifting threshold voltages, which are caused by plasma induced damage generated from the antenna structure, of the transistor to be tested, and threshold voltage differences among reference transistors corresponding to the transistor to be tested in the reference circuit. The on-chip sensor provided by the invention is provided with the antenna structure and the reference circuit and influences possibly generated by other transistors are eliminated so that the testing and monitoring of the threshold voltages of the transistor to be tested can be more accurate and simpler.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of for measuring the chip upper sensor of threshold voltage shift.
Background technology
For VLSI (very large scale integrated circuit) manufacturing industry, along with constantly reducing of MOSFET (mos field effect transistor) plant bulk, semiconductor fabrication process has entered the deep-submicron epoch, and develop to sub-micro, now, semiconductor device reliability more and more directly affects the performance and used life of the IC chip of making.
In the manufacturing process of semiconductor devices, many processing steps such as dry etching, Implantation and chemical vapor deposition all can be used plasma, and in theory, described plasma is externally electric neutrality, that is to say, the quantity of positive ion and negative ion equates.But in fact enter into positive ion in the regional area of wafer and negative ion and be not equivalent, this just causes producing a large amount of free electric charges, make to be exposed to the conductors such as plain conductor in plasma environment or polysilicon just as antenna, collect these free electric charges.The length of these antenna is longer, and area is larger, and the electric charge of collecting is more.When the electric charge of collecting when these antenna acquires a certain degree, will produce electric discharge phenomena, above-mentioned electric discharge phenomena are exactly usually said plasma damage (Plasma Induced Damage, PID) effect, also referred to as antenna effect.
Plasma damage (Plasma Induced Damage, PID) effect becomes affects the stable principal element of cmos device, same plasma damage (Plasma Induced Damage, PID) effect has important impact equally for polysilicon/SiON, hafnium/metal gates, in addition, plasma damage (Plasma Induced Damage, PID) effect can cause threshold voltage (threshold voltage, Vt) drift, the phenomenons such as junction leakage increase, have a strong impact on chip performance.
Plasma damage (Plasma Induced Damage in prior art, PID) detection architecture of effect as depicted in figs. 1 and 2, wherein Fig. 1 is the reference configuration (Reference Structure) in detection architecture, in described reference configuration, do not comprise antenna (Antenna), and in the antenna structure shown in Fig. 2 (Antenna Structure), comprise antenna (Antenna), described antenna (Antenna) is connected with device grids structure, the threshold voltage of wherein said reference configuration and described antenna structure is measured respectively, then contrast, wherein measure, the circuit of read threshold voltages as shown in Figure 3, because described threshold voltage is measured respectively, make the complexity for the monitor procedure change of chip, be unfavorable for the monitoring of threshold voltage.
Therefore, need a kind of detection architecture examination and controlling device applying plasma damage (Plasma Induced Damage online badly, PID) size, and plasma damage (Plasma Induced Damage, PID) impact that device is caused.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection domain of attempting to determine technical scheme required for protection.
The invention provides that a kind of described sensor comprises test circuit, reference circuit and subtraction circuit for measuring the chip upper sensor of threshold voltage shift,
Wherein, described reference circuit and described test circuit are connected in parallel between supply voltage and ground connection;
The output terminal of described test circuit and described reference circuit is electrically connected to respectively the input end of described subtraction circuit, it is characterized in that, described test circuit comprises a test transistor and an antenna structure, wherein, described antenna structure is connected with the grid of described test transistor, described subtraction circuit for the threshold voltage of the drift of measuring plasma damage that described test transistor produces from antenna structure and causing with described reference circuit with reference transistor corresponding to described test transistor between threshold voltage difference.
As preferably, described test circuit comprises that first mirror is as current circuit and the first subtraction circuit.
As preferably, described the first circuit mirror current and described the first subtraction circuit are connected in parallel between described supply voltage and ground connection.
As preferably, described first mirror consists of 6 transistors as current circuit, and wherein said test transistor and transistor seconds (P2), the 5th transistor (P5) and the 6th transistor (P6) join end to end and form a closed path backfeed loop.
As preferably, between described test transistor and described the 5th transistor, be also connected with the 3rd transistor (P3), between described transistor seconds and described the 6th transistor, be also connected with the 4th transistor (P4).
As preferably, described antenna structure is not connected with described transistor seconds, to avoid described plasma damage to affect described transistor seconds.
As preferably, described reference circuit comprises the second mirror image current circuit and the second subtraction circuit.
As preferably, described the second circuit mirror current and described the second subtraction circuit are connected in parallel between described supply voltage and ground connection.
As preferably, described the second mirror image current circuit consists of 6 transistors, and wherein said reference transistor and transistor seconds (P2r), the 5th transistor (P5r) and the 6th transistor (P6r) join end to end and form a closed path backfeed loop.
As preferably, between described reference transistor and described the 5th transistor, be also connected with the 3rd transistor (P3r), between described transistor seconds and described the 6th transistor, be also connected with the 4th transistor (P4r).
As preferably, described antenna structure is also connected with the first metal throuth hole chain, and one end of described the first metal throuth hole chain connects the grid of described test transistor, and the other end of described metal throuth hole chain is connected in the first metal layer at top.
As preferably, described sensor also comprises the second metal throuth hole chain, and one end of wherein said the second metal throuth hole chain connects the source electrode of described test transistor, and the other end of described metal throuth hole chain is connected in the second metal layer at top.
As preferably, described sensor also comprises the 3rd metal throuth hole chain, and one end of wherein said the 3rd metal throuth hole chain connects the grid of described transistor seconds, and the other end of described metal throuth hole chain is connected in the 3rd metal layer at top.
As preferably, the through hole that described metal throuth hole chain comprises multiple layer metal layer and connects described metal level.
As preferably, between described the first metal layer at top and described the second metal layer at top, described the 3rd metal layer at top, by metal bridge, be connected respectively.
Chip upper sensor of the present invention (on-chip sensor) is used for measuring in test transistor due to plasma damage (Plasma Induced Damage, the drift of the threshold voltage PID) causing, described sensor comprises test circuit, reference circuit and subtraction circuit, in test circuit, antenna structure is connected with described test transistor, and the drift voltage of the threshold voltage that the plasma damage that measurement test transistor produces from antenna structure causes is poor.In the present invention, change the shortcoming of measuring at twice threshold voltage in described reference structure and antenna structure in prior art, by antenna structure and reference circuit are set in sensor, and eliminate the issuable impact of other transistors, the test, monitoring that makes test transistor threshold voltage more accurately, simple.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1-2 is reference configuration and antenna structure view in prior art;
Fig. 3 is threshold voltage test circuit figure in prior art;
Fig. 4 is the circuit diagram that the present invention measures the sensor of transistor threshold voltage drift.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
Should give attention, the term that used is here only in order to describe specific embodiment, but not intention restriction is according to exemplary embodiment of the present invention.As used herein, unless context explicitly points out in addition, otherwise singulative is also intended to comprise plural form.In addition, it is to be further understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination.
Now, describe in more detail according to exemplary embodiment of the present invention with reference to the accompanying drawings.Yet these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.To should be understood that, to provide these embodiment of the present inventionly to disclose thoroughly and complete in order making, and the design of these exemplary embodiments is fully conveyed to those of ordinary skills.In the accompanying drawings, for the sake of clarity, use identical Reference numeral to represent identical element, thereby will omit description of them.
Of the present inventionly for measuring the sensor of transistor threshold voltage drift, comprise test circuit, reference circuit and subtraction circuit,
Wherein, described reference circuit and described test circuit are connected in parallel between supply voltage and ground connection;
The output terminal of described test circuit and described reference circuit is electrically connected to respectively the input end of described subtraction circuit, described test circuit comprises a test transistor and an antenna structure, wherein, described antenna structure is connected with the grid of described test transistor, described subtraction circuit for the threshold voltage of the drift of measuring plasma damage that described test transistor produces from antenna structure and causing with described reference circuit with reference transistor corresponding to described test transistor between threshold voltage difference.
As preferably, described test circuit comprises that first mirror is as current circuit and the first subtraction circuit, and described the first circuit mirror current and described the first subtraction circuit are connected in parallel between described supply voltage and ground connection.
Particularly, for test circuit of the present invention is better described, a kind of embodiment is provided in the present invention, but it should be noted that this embodiment is only used to help to explain, the present invention is not limited only to this embodiment, described test circuit as shown in Figure 4, in described test circuit, there are in this embodiment 8 transistors (P1-P8) to form, described test transistor P1, transistor seconds P2, end to end composition the first circuit mirror current of the 5th transistor P5 and the 6th transistor P6, as preferably, at described test transistor P1, between the 5th transistor P5, also there is the 3rd transistor P3, at described transistor seconds P2, between the 6th transistor P6, also there is the 4th transistor P4, the end to end formation one closed path backfeed loop of source-drain electrode of described transistor P1-P6.As preferably, described the first subtraction circuit comprises the 7th transistor P7, the 8th transistor P8, in parallel with described mirror image current circuit after described the 7th transistor P7, the 8th transistor P8 series connection, is connected between power supply and ground connection.
Wherein, all NMOS and PMOS transistor homogeneous end ground connection in described test circuit, the other end connects operating voltage.
In order to overcome problems of the prior art, improve the accuracy of test transistor P1 threshold voltage shift amount, sensor of the present invention also further comprises reference circuit and a subtraction circuit, to measure more accurately, to monitor the drift of described test transistor threshold voltage.
Wherein, described reference circuit and described test circuit are arranged in parallel, and one end of described reference circuit connects supply voltage, other end ground connection, described reference circuit is the same with described test circuit, and described reference circuit comprises the second mirror image current circuit and the second subtraction circuit.Described the second circuit mirror current and described the second subtraction circuit are connected in parallel between described supply voltage and ground connection.
Particularly, as shown in Figure 4, described the second mirror image current circuit with described first mirror as current circuit, by 6 transistors, formed, wherein said reference transistor and transistor seconds P2r, the 5th transistor P5r and the 6th transistor P6r join end to end and form a closed path backfeed loop, and wherein said reference transistor, transistor seconds P2r, the 5th transistor P5r and the 6th transistor P6r are corresponding as the test transistor in current circuit, transistor seconds P2, the 5th transistor P5 and the 6th transistor P6 with first mirror.
As preferably, between described reference transistor and described the 5th transistor, be also connected with the 3rd transistor P3r, between described transistor seconds and described the 6th transistor, be also connected with the 4th transistor P4r.Corresponding with described the first subtraction circuit, described the second subtraction circuit comprises the 7th transistor P7r, the 8th transistor P8r, is connected between power supply and ground connection after in parallel with described the second mirror image current circuit.
The output terminal of described test circuit and described reference circuit is electrically connected to respectively the input end of described subtraction circuit, measure the threshold voltage of the drift that plasma damage that described test transistor produces from antenna structure causes with in described reference circuit with reference transistor corresponding to described test transistor between threshold voltage difference.
In a specific embodiment of the present invention, described subtraction circuit comprises the 11 transistor P11 and the 11 transistor P11r, wherein, described the 11 transistor P11 is connected with described test circuit, described the 11 transistor P11r is connected with described reference circuit, and described subtraction circuit is by the grounded drain of described transistor P11r.As further preferred, the source electrode of described test transistor P1 is connected with the drain electrode of described the 11 transistor P11, the grid of described the 11 transistor P11 is connected with the drain electrode of described the 7th transistor P7, be used for reading the threshold voltage of test transistor, the source electrode of the first transistor P1r corresponding with described test transistor P1 is connected with the drain electrode of described the 11 transistor P11r, for reading the threshold voltage of described test transistor P1.
Described subtraction circuit is connected with described reference circuit with described test circuit respectively by the way, wherein, the threshold voltage of described test transistor is input in described subtraction circuit by the grid of transistor P11, the threshold voltage of transistor P1r described in described reference circuit is input in described subtraction circuit by the grid of described transistor P11r, again because described test transistor is connected with described antenna structure, therefore by described subtraction circuit, just can show that described test transistor is due to plasma damage (Plasma Induced Damage, PID) threshold voltage causing drift voltage poor.
In described test circuit, described antenna structure is also connected with the first metal throuth hole chain, one end of described the first metal throuth hole chain connects the grid of described test transistor, the other end of described metal throuth hole chain is connected in the first metal layer at top, as preferably, described sensor also comprises the second metal throuth hole chain, one end of wherein said the second metal throuth hole chain connects the source electrode of described test transistor, the other end of described metal throuth hole chain is connected in the second metal layer at top, described sensor also comprises the 3rd metal throuth hole chain, one end of wherein said the 3rd metal throuth hole chain connects the grid of described transistor seconds, the other end of described metal throuth hole chain is connected in the 3rd metal layer at top.
As preferably, the through hole that described metal throuth hole chain comprises multiple layer metal layer and connects described metal level.
As preferably, between described the first metal layer at top and described the second metal layer at top, described the 3rd metal layer at top, by metal bridge, be connected respectively.Wherein, described antenna (Antenna) structure is connected with test transistor P1 in test circuit, be not connected with the transistor seconds P2 in described test circuit, measure plasma damage (the Plasma Induced Damage being produced by antenna structure in test transistor P1, PID), avoid P2 applying plasma damage (Plasma Induced Damage, PID) to impact transistor P1 simultaneously, cause the inaccurate of outcome measurement.
In one embodiment of this invention, described metal throuth hole chain comprises some interlayer metal layers and the through hole that is communicated with described metal level, particularly, as shown in Figure 4, described via chain comprises metal level M1, M2 and via chain between the two, the number of plies of described metal throuth hole chain is not limited to a certain numerical value, can adjust as required, between the top layer metallic layer of wherein said metal throuth hole chain (Top metal), by metal bridge (metal jump), be connected, avoided P2 applying plasma damage (Plasma Induced Damage, PID) transistor P1 is impacted.
Chip upper sensor of the present invention (on-chip sensor) is used for measuring in test transistor due to plasma damage (Plasma Induced Damage, the drift of the threshold voltage PID) causing, described sensor comprises test circuit, reference circuit and subtraction circuit, in test circuit, antenna structure is connected with described test transistor, and then it is poor to measure the drift voltage of the threshold voltage that plasma damage that test transistor produces from antenna structure causes.。In the present invention, change the shortcoming of measuring at twice threshold voltage in described reference structure and antenna structure in prior art, by antenna structure and reference circuit are set in sensor, and eliminate the issuable impact of other transistors, the test, monitoring that makes test transistor threshold voltage more accurately, simple.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (15)
1. for measuring a chip upper sensor for threshold voltage shift, described sensor comprises test circuit, reference circuit and subtraction circuit,
Wherein, described reference circuit and described test circuit are connected in parallel between supply voltage and ground connection;
The output terminal of described test circuit and described reference circuit is electrically connected to respectively the input end of described subtraction circuit, it is characterized in that, described test circuit comprises a test transistor and an antenna structure, wherein, described antenna structure is connected with the grid of described test transistor, described subtraction circuit for the threshold voltage of the drift of measuring plasma damage that described test transistor produces from antenna structure and causing with described reference circuit with reference transistor corresponding to described test transistor between threshold voltage difference.
2. sensor according to claim 1, is characterized in that, described test circuit comprises that first mirror is as current circuit and the first subtraction circuit.
3. sensor according to claim 2, is characterized in that, described the first circuit mirror current and described the first subtraction circuit are connected in parallel between described supply voltage and ground connection.
4. sensor according to claim 2, it is characterized in that, described first mirror consists of 6 transistors as current circuit, and wherein said test transistor and transistor seconds (P2), the 5th transistor (P5) and the 6th transistor (P6) join end to end and form a closed path backfeed loop.
5. sensor according to claim 4, is characterized in that, between described test transistor and described the 5th transistor, is also connected with the 3rd transistor (P3), between described transistor seconds and described the 6th transistor, is also connected with the 4th transistor (P4).
6. sensor according to claim 4, is characterized in that, described antenna structure is not connected with described transistor seconds, to avoid described plasma damage to affect described transistor seconds.
7. sensor according to claim 1, is characterized in that, described reference circuit comprises the second mirror image current circuit and the second subtraction circuit.
8. sensor according to claim 7, is characterized in that, described the second circuit mirror current and described the second subtraction circuit are connected in parallel between described supply voltage and ground connection.
9. sensor according to claim 7, it is characterized in that, described the second mirror image current circuit consists of 6 transistors, and wherein said reference transistor and transistor seconds (P2r), the 5th transistor (P5r) and the 6th transistor (P6r) join end to end and form a closed path backfeed loop.
10. sensor according to claim 9, it is characterized in that, between described reference transistor and described the 5th transistor, be also connected with the 3rd transistor (P3r), between described transistor seconds and described the 6th transistor, be also connected with the 4th transistor (P4r).
11. sensors according to claim 6, it is characterized in that, described antenna structure is also connected with the first metal throuth hole chain, and one end of described the first metal throuth hole chain connects the grid of described test transistor, and the other end of described metal throuth hole chain is connected in the first metal layer at top.
12. sensors according to claim 11, it is characterized in that, described sensor also comprises the second metal throuth hole chain, and one end of wherein said the second metal throuth hole chain connects the source electrode of described test transistor, and the other end of described metal throuth hole chain is connected in the second metal layer at top.
13. sensors according to claim 12, it is characterized in that, described sensor also comprises the 3rd metal throuth hole chain, and one end of wherein said the 3rd metal throuth hole chain connects the grid of described transistor seconds, and the other end of described metal throuth hole chain is connected in the 3rd metal layer at top.
14. sensors according to claim 13, is characterized in that, the through hole that described metal throuth hole chain comprises multiple layer metal layer and connects described metal level.
15. sensors according to claim 13, is characterized in that, between described the first metal layer at top and described the second metal layer at top, described the 3rd metal layer at top, are connected respectively by metal bridge.
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106354117A (en) * | 2015-07-16 | 2017-01-25 | 通用汽车环球科技运作有限责任公司 | Determining the source of a ground offset in a controller area network |
CN107452715A (en) * | 2016-04-28 | 2017-12-08 | 英飞凌科技股份有限公司 | Semiconductor devices and method for the gate insulator of test transistor structure |
CN116224003A (en) * | 2022-12-26 | 2023-06-06 | 重庆大学 | Threshold voltage stability test circuit of MOS type semiconductor device |
CN116359695A (en) * | 2023-02-09 | 2023-06-30 | 重庆大学 | MOS type semiconductor device threshold voltage stabilization test method and system |
WO2024000626A1 (en) * | 2022-06-30 | 2024-01-04 | 长鑫存储技术有限公司 | Semiconductor test key and method for forming same |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10160764A (en) * | 1996-11-27 | 1998-06-19 | Yokogawa Electric Corp | Input circuit for insulating-voltage measuring apparatus |
CN1350368A (en) * | 2000-10-25 | 2002-05-22 | 明碁电通股份有限公司 | Element error correcting system for IC manufacture |
CN1523653A (en) * | 2003-02-20 | 2004-08-25 | ���µ�����ҵ��ʽ���� | Semiconductor device for charge-up damage evaluation and charge-up damage evaluation method |
CN1992267A (en) * | 2005-12-30 | 2007-07-04 | 海力士半导体有限公司 | Semiconductor device |
CN102034816A (en) * | 2009-09-29 | 2011-04-27 | 中芯国际集成电路制造(上海)有限公司 | Plasma induced damage test device and method for producing test device |
CN102044458A (en) * | 2009-10-09 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Detection method of degree of damage of plasma |
-
2013
- 2013-01-22 CN CN201310024231.1A patent/CN103941068B/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10160764A (en) * | 1996-11-27 | 1998-06-19 | Yokogawa Electric Corp | Input circuit for insulating-voltage measuring apparatus |
CN1350368A (en) * | 2000-10-25 | 2002-05-22 | 明碁电通股份有限公司 | Element error correcting system for IC manufacture |
CN1523653A (en) * | 2003-02-20 | 2004-08-25 | ���µ�����ҵ��ʽ���� | Semiconductor device for charge-up damage evaluation and charge-up damage evaluation method |
CN1992267A (en) * | 2005-12-30 | 2007-07-04 | 海力士半导体有限公司 | Semiconductor device |
CN102034816A (en) * | 2009-09-29 | 2011-04-27 | 中芯国际集成电路制造(上海)有限公司 | Plasma induced damage test device and method for producing test device |
CN102044458A (en) * | 2009-10-09 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Detection method of degree of damage of plasma |
Non-Patent Citations (2)
Title |
---|
杨建军 等: "反应离子刻蚀铝中nMOS器件的等离子充电损伤", 《电子工业专用设备》 * |
赵毅 等: "MOS器件中的等离子损伤", 《半导体技术》 * |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106354117A (en) * | 2015-07-16 | 2017-01-25 | 通用汽车环球科技运作有限责任公司 | Determining the source of a ground offset in a controller area network |
CN106354117B (en) * | 2015-07-16 | 2019-03-15 | 通用汽车环球科技运作有限责任公司 | Determine the ground offset source in controller LAN |
CN107452715A (en) * | 2016-04-28 | 2017-12-08 | 英飞凌科技股份有限公司 | Semiconductor devices and method for the gate insulator of test transistor structure |
WO2024000626A1 (en) * | 2022-06-30 | 2024-01-04 | 长鑫存储技术有限公司 | Semiconductor test key and method for forming same |
CN116224003A (en) * | 2022-12-26 | 2023-06-06 | 重庆大学 | Threshold voltage stability test circuit of MOS type semiconductor device |
CN116224003B (en) * | 2022-12-26 | 2023-11-14 | 重庆大学 | Threshold voltage stability test circuit of MOS type semiconductor device |
CN116359695A (en) * | 2023-02-09 | 2023-06-30 | 重庆大学 | MOS type semiconductor device threshold voltage stabilization test method and system |
CN116359695B (en) * | 2023-02-09 | 2024-01-09 | 重庆大学 | MOS type semiconductor device threshold voltage stabilization test method and system |
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