CN102034816A - Plasma induced damage test device and method for producing test device - Google Patents
Plasma induced damage test device and method for producing test device Download PDFInfo
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Abstract
The invention provides a plasma induced damage PID test device, which comprises a first metal interconnection layer, a probe card interconnection layer and a second metal interconnection layer, wherein the first metal interconnection layer is produced on a first semiconductor apparatus on a wafer, the probe card interconnection layer is produced on both a second semiconductor apparatus on the wafer and the first metal interconnection layer; in the first metal interconnection layer, all metal layers are respectively provided with an antennas used for collecting a plasma charge and connected to form a first passage via through holes disposed in interstratified dielectric layers; and the top metal layer of the second metal interconnection layer is conducted with the top metal layer of the first metal interconnection layer, the bottom metal layer of the second metal interconnection layer is conducted with the bottom probe card of the probe card interconnection layer, and all metal layers are connected to form a third passage via through holes disposed in interstratified dielectric layers. The invention also provides a method for producing the test device. In the invention, the device and the method are adopted to prevent the semiconductor apparatus from being damaged by the plasma charge collected by the probe card.
Description
Technical field
The present invention relates to semiconductor fabrication techniques, the method that particularly a kind of plasma is introduced the damage testing apparatus and made testing apparatus.
Background technology
In the semiconductor chip fabrication process, and plasma introducing damage (Plasma Induced Damage, PID) most important to semiconductor chip quality and reliability.PID may appear at front end production (FrontEnd Of Line, FEOL) or the rear end produce (Back End Of Line, BEOL) in many manufacture crafts, such as: ion injection, dry etching and plasma enhanced chemical vapor deposition (Plasma-Enhanced Chemical Vapor Deposition, PECVD) etc. in the manufacture craft, the capital using plasma injects, etching or deposition, and then can introduce a large amount of plasma electric charges in the chip; The plasma electric charge of introducing may be assembled more and morely at chip internal, forms plasma current.The plasma current that PID forms can puncture some semiconductor device on the chip, the reliability of semiconductor device is reduced, such as: the plasma current that PID forms can puncture the gate oxide of metal-oxide-semiconductor, has reduced the reliability of metal-oxide-semiconductor, even metal-oxide-semiconductor can't be worked.
In order to monitor the PID in the semiconductor chip fabrication process, when making semiconductor chip, make in order to detect the testing apparatus of PID usually.Fig. 1 is the structural representation of existing P ID testing apparatus.As shown in Figure 1, existing testing apparatus is described, specific as follows: existing testing apparatus comprise first semiconductor device, second semiconductor device, first metal interconnecting layer of producing on first semiconductor device 104, when making first metal interconnecting layer 104 in the probe card interconnection layer of producing on second semiconductor device 105, when making first metal interconnecting layer 104, on every layer of metal level, make in order to collect the antenna of plasma electric charge; First semiconductor device among Fig. 1 is that metal-oxide-semiconductor 102, the second semiconductor device are diode 103.Each layer of probe card interconnection layer 105 is probe card, its lining plank for inserting for the probe in order to test.
On wafer, form shallow channel isolation area 101, be used to isolate metal-oxide-semiconductor 102 and diode 103; To form P type metal-oxide-semiconductor field effect transistor is example, by N type ion implantation technology, on Semiconductor substrate, form the N trap, adopt deposition, etching technics to form gate oxide 1023 and grid 1024 successively at crystal column surface then, be that mask carries out the injection of P type ion then, form source electrode 1022 and drain electrode 1021 with grid 1024; Form diode 103 when forming P type metal-oxide-semiconductor field effect transistor, described diode 103 comprises the N utmost point and the P utmost point, and the N trap is the N utmost point, carries out the P type and inject in the zonule of N trap, and formed p type island region territory is the P utmost point.
In the testing apparatus shown in Figure 1, first metal interconnecting layer 104 comprises n layer intermediate metal layer, 2 layers of top layer metallic layer and 1 layer of passivation layer, and in first metal interconnecting layer 104, every layer of metal level also is manufactured with simultaneously in order to collecting the antenna of plasma electric charge, and the through hole that every layer of metal level offered by the dielectric layer of interlayer connects into first path; In probe card interconnection layer 105, the through hole that every layer of probe card offered by the dielectric layer of interlayer connects into alternate path.
The method of making probe card interconnection layer 105 and antenna when making first metal interconnecting layer 104 is: at first, utilize chemical vapour deposition (CVD) and photoetching on grid 1024 surfaces of metal-oxide-semiconductor 102, to make connected through hole, utilize identical method on the positive pole of diode 103, to make connected through hole; Secondly, the through hole that is connected with grid 1024 with through hole that diode 103 is connected on lay the ground floor metal level, utilize photoetching to remove the part metals layer of this layer, with the bottom probe card 1051 of the bottom metal layer that forms first metal interconnecting layer 104, the antenna 1041 that is connected with bottom metal layer and probe card interconnection layer 105; Once more, utilize chemical vapour deposition (CVD) and photoetching, when making every layer of metal level of first metal interconnecting layer 104, make probe card and antenna at this layer, such as: make second antenna 1042 and second probe card 1052 on the second layer intermediate metal layer of first metal interconnecting layer 104; And on x layer intermediate metal layer, make x antenna 1043 and x probe card 1053 successively, on n-1 layer intermediate metal layer, make n-1 antenna 1044 and n-1 probe card 1054, on n layer intermediate metal layer, make n antenna 1045 and n-1 probe card 1055, on first top layer metallic layer, make antenna 1046 and probe card 1056, making antenna 1047 and probe card 1057 on the top layer metallic layer, on passivation layer, making probe card 1058; At last, utilize photoetching and chemical vapour deposition (CVD), form metal connecting line 106 at the top layer metallic layer of first metal interconnecting layer 104 and 1057 of the top layer probe cards of probe card interconnection layer 105, put on the grid 1024 of metal-oxide-semiconductor 102 in order to the voltage of the probe card 1058 that will be added to passivation layer when the test MOS pipe 102 by first path of first metal interconnecting layer 104, whether breakdown with the gate oxide 1023 of judging metal-oxide-semiconductor 102.
In the testing apparatus that is made into according to the method described above, the diode 103 that is communicated with probe card interconnection layer 105 can be derived wafer with the part plasma electric charge that produces in the manufacturing process, and another part plasma electric charge is collected in every layer the probe card and antenna; Because the restriction of manufacture craft, the area of the probe card of every layer of making be much larger than the area of the antenna of this layer making, the quantity of the plasma electric charge that this quantity that has just caused the plasma electric charge that every layer of probe card collect is collected much larger than this layer antenna.Though the antenna of making on every layer of metal level can effectively be collected in the plasma electric charge that produces in the technology manufacturing process, reduce of the damage of the plasma current of PID generation to the gate oxide 1023 of metal-oxide-semiconductor 102, but when metal connecting line 106 is communicated with the top layer probe card 1057 of the top layer metallic layer of first metal interconnecting layer 104 and probe card interconnection layer 105, the plasma electric charge of collecting in the probe card 1057 imports metal-oxide-semiconductor 102 by first path in first metal interconnecting layer, destroys gate oxide 1023.
In sum, the plasma electric charge of collecting on the probe card of every layer of making has weakened the ability of the antenna collection plasma electric charge of this layer making; And before utilizing existing testing apparatus that metal-oxide-semiconductor is tested, the plasma electric charge that the plasma electric charge of collecting on the probe card produces can import metal-oxide-semiconductor through first path of first metal interconnecting layer, puncture the gate oxide of metal-oxide-semiconductor, reduced the reliability of metal-oxide-semiconductor, semiconductor device to be measured has been caused plasma damage.
Summary of the invention
In view of this, the invention provides a kind of plasma and introduce damage PID testing apparatus, this testing apparatus can stop the plasma electric charge of storing on the probe card when test wafer that the semiconductor device to be measured on the wafer is caused plasma damage.
The present invention also provides a kind of method of making testing apparatus, and the plasma electric charge that this method can be avoided storing on the probe card when test wafer causes plasma damage to the semiconductor device to be measured on the wafer.
For achieving the above object, technical scheme of the present invention specifically is achieved in that
A kind of plasma imports infringement PID testing apparatus, comprising:
First metal interconnecting layer of on first semiconductor device of wafer, producing;
In wafer in order to second semiconductor device of deriving the plasma electric charge on, the probe card interconnection layer produced simultaneously with described first metal interconnecting layer;
In described first metal interconnecting layer, every layer of metal level also is manufactured with simultaneously in order to collecting the antenna of plasma electric charge, and the through hole that every layer of metal level offered by the dielectric layer of interlayer connects into first path;
In described probe card interconnection layer, the through hole that every layer of probe card offered by the dielectric layer of interlayer connects into alternate path;
This device also comprises second metal interconnecting layer of producing simultaneously with described first metal interconnecting layer;
The through hole that the bottom probe card conducting of the top layer metallic layer conducting of the top layer metallic layer of described second metal interconnecting layer and described first metal interconnecting layer, bottom metal layer and described probe card interconnection layer and every layer of metal level are offered by the dielectric layer of interlayer connects into the 3rd path, conducts to first path in order to the plasma electric charge that stops the probe card interconnection layer to be collected.
In the said apparatus, has first metal connecting line of described bottom metal layer of conducting and described bottom probe card between the bottom probe card of the bottom metal layer of described second metal interconnecting layer and described probe card interconnection layer;
The top-level metallic interlayer of the top layer metallic layer of described second metal interconnecting layer and described first metal interconnecting layer has the second metal connecting line of the top layer metallic layer of the top layer metallic layer of conducting second metal interconnecting layer and first metal interconnecting layer.
In the said apparatus, described first semiconductor device is a metal-oxide-semiconductor; Described second semiconductor device is a diode.
A kind of method of making the PID testing apparatus, this method comprises:
Making first semiconductor device on wafer reaches in order to derive second semiconductor device of plasma electric charge;
On first semiconductor device of wafer, make first metal interconnecting layer, and when making first metal interconnecting layer, on second semiconductor device, make the probe card interconnection layer;
When making first metal interconnecting layer, in each layer metal level of first metal interconnecting layer, be manufactured with antenna in order to collect the plasma electric charge and to be connected with this layer metal level;
It is characterized in that this method also comprises:
When making first metal interconnecting layer and probe card interconnection layer, make second metal interconnecting layer that top layer is communicated with the top layer metallic layer of first metal interconnecting layer, bottom is communicated with the bottom probe card of probe card interconnection layer.
In the said method, described making second metal interconnecting layer comprises:
When the bottom probe card of the bottom metal layer of making first metal interconnecting layer and probe card interconnection layer, utilize chemical vapour deposition (CVD) and photoetching making not to be communicated with the bottom metal layer of second metal interconnecting layer of first metal interconnecting layer and connection bottom probe card;
When other each layer probe cards of other each layer metal levels of making first metal interconnecting layer and probe card interconnection layer, utilize chemical vapour deposition (CVD) and photoetching not to be communicated with the metal level of second metal interconnecting layer of the metal level of first metal interconnecting layer of this layer and probe card every layer of making;
Utilize photoetching and chemical vapour deposition (CVD) to be communicated with the top layer metallic layer of first metal interconnecting layer and the top layer metallic layer of second metal interconnecting layer.
In the said method, described first semiconductor device is a metal-oxide-semiconductor; Described second semiconductor device is a diode.
As seen from the above technical solutions, the invention provides a kind of plasma and import infringement PID testing apparatus, the through hole that the bottom probe card conducting of the top layer metallic layer of second metal interconnecting layer in this device and the top layer metallic layer conducting of first metal interconnecting layer, bottom metal layer and probe card interconnection layer and every layer of metal level are offered by the dielectric layer of interlayer connects into the 3rd path; Adopt testing apparatus provided by the invention that semiconductor device is tested, the 3rd path not only can will put on alternate path when testing test voltage puts on first semiconductor device that is communicated with first path, and can before test, stop the plasma electric charge of collecting on each layer probe card to import first path, first semiconductor device is caused the PID infringement, improved the reliability of semiconductor device.
The present invention also provides a kind of method of making testing apparatus, this method comprises: when making first metal interconnecting layer and probe card interconnection layer, make second metal interconnecting layer that top layer is communicated with the top layer metallic layer of first metal interconnecting layer, bottom is communicated with the bottom probe card of probe card interconnection layer; The test voltage that adopts the 3rd path of the testing apparatus that method provided by the invention produces not only can will put on alternate path when testing puts on first semiconductor device that is communicated with first path, and can before test, stop the plasma electric charge of collecting on each layer probe card to import first path, first semiconductor device is caused the PID infringement, improved the reliability of semiconductor device
Description of drawings
Fig. 1 is the structural representation that existing plasma is introduced damage PID testing apparatus.
Fig. 2 introduces the structural representation of damage PID testing apparatus for plasma of the present invention.
Fig. 3 makes the method flow diagram of testing apparatus for the present invention.
Embodiment
For make purpose of the present invention, technical scheme, and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
The invention provides a kind of plasma and import infringement PID testing apparatus, comprising: first metal interconnecting layer of on first semiconductor device of wafer, producing; In wafer in order to second semiconductor device of deriving the plasma electric charge on, the probe card interconnection layer produced simultaneously with first metal interconnecting layer; In first metal interconnecting layer, every layer of metal level also is manufactured with simultaneously in order to collecting the antenna of plasma electric charge, and the through hole that every layer of metal level offered by the dielectric layer of interlayer connects into first path; In the probe card interconnection layer, the through hole that every layer of probe card offered by the dielectric layer of interlayer connects into alternate path; This device also comprises second metal interconnecting layer of producing simultaneously with first metal interconnecting layer; The through hole that the bottom probe card conducting of the top layer metallic layer conducting of the top layer metallic layer of second metal interconnecting layer and first metal interconnecting layer, bottom metal layer and probe card interconnection layer and every layer of metal level are offered by the dielectric layer of interlayer connects into the 3rd path, conducts to first path in order to the plasma electric charge that stops the probe card interconnection layer to be collected.
The present invention also provides a kind of method of making testing apparatus, comprising: make first semiconductor device and reach in order to derive second semiconductor device of plasma electric charge on wafer; On first semiconductor device of wafer, make first metal interconnecting layer, and when making first metal interconnecting layer, on second semiconductor device, make the probe card interconnection layer; When making first metal interconnecting layer, in each layer metal level of first metal interconnecting layer, be manufactured with antenna in order to collect the plasma electric charge and to be connected with this layer metal level; This method also comprises: when making first metal interconnecting layer and probe card interconnection layer, make second metal interconnecting layer that top layer is communicated with the top layer metallic layer of first metal interconnecting layer, bottom is communicated with the bottom probe card of probe card interconnection layer.
Fig. 2 introduces the structural representation of damage PID testing apparatus for plasma of the present invention.Now in conjunction with Fig. 2, the structure of plasma of the present invention being introduced damage PID testing apparatus describes, and is specific as follows:
Plasma of the present invention is introduced damage PID testing apparatus and is comprised: first semiconductor device, second semiconductor device, first metal interconnecting layer 204, probe card interconnection layer 205 and second metal interconnecting layer 206; Wherein, first metal interconnecting layer 204 comprises the antenna that is connected with this layer metal level of first path and each layer making.
First semiconductor device of the present invention is a semiconductor device to be tested, and this semiconductor device to be tested is a metal-oxide-semiconductor, and this metal-oxide-semiconductor can be P type metal-oxide-semiconductor field effect transistor, also can be N type metal-oxide-semiconductor field effect transistor; Semiconductor device to be tested in the present embodiment is the P type metal-oxide-semiconductor 202 that is made on the wafer; Second semiconductor device is a diode 203 in the present embodiment.On wafer, make in the P type metal-oxide-semiconductor 202, on wafer, make in order to the grade diode 203 of ionic charge of leading-out portion.Because testing apparatus of the present invention both can be tested P type metal-oxide-semiconductor, also can test N type metal-oxide-semiconductor, semiconductor device to be measured is in the present invention no longer distinguished P type metal-oxide-semiconductor and N type metal-oxide-semiconductor, and semiconductor device to be measured of the present invention is a metal-oxide-semiconductor.
First metal interconnecting layer 204 is made on the metal-oxide-semiconductor 202; In first metal interconnecting layer 204, also be manufactured with simultaneously on every layer of metal level in order to collecting the antenna of plasma electric charge, and the through hole that every layer of metal level offered by the dielectric layer of interlayer connects into first path.First metal interconnecting layer 204 comprises n layer intermediate metal layer and 2 layers of top layer metallic layer, is equipped with passivation layer on first metal interconnecting layer, 204 tops; The through hole that the bottom metal layer of first metal interconnecting layer 204 is offered by the dielectric layer on metal-oxide-semiconductor 202 grids 1024 surfaces is communicated with metal-oxide-semiconductor 202.The bottom metal layer of first metal interconnecting layer 204 is the ground floor intermediate metal layer of n layer intermediate metal layer.Antenna in first metal interconnecting layer 204 is to be made when making every layer of metal level, the antenna that just utilizes chemical vapour deposition (CVD) and photoetching to form metal level and be connected with this layer metal level on each layer dielectric layer is such as first antenna 2041 on the ground floor intermediate metal layer, second antenna 2042 on the second layer intermediate metal layer, x antenna 2043 on the x layer intermediate metal layer, n-1 antenna 2044 on the n-1 layer intermediate metal layer, n antenna 2045 on n layer intermediate metal layer, antenna 2046 on first top layer metallic layer and the antenna 2047 on the top layer metallic layer; Wherein, n is the integer more than or equal to 1; X is smaller or equal to n and more than or equal to 1 integer.
Probe card interconnection layer 205 is made on the diode 203 of wafer, and is made when making first metal interconnecting layer 204.In probe card interconnection layer 205, the through hole that every layer of probe card dielectric layer by interlayer begins connects into alternate path; When making the bottom metal layer of first metal interconnecting layer 204, made bottom probe card 2051 at this layer, and the through hole that this bottom probe card 2051 is offered by the dielectric layer of 203 of itself and diodes is communicated with.Probe card interconnection layer 205 comprises n+3 layer probe card, is respectively: first probe card 2051 on the ground floor intermediate metal layer, second probe card 2052 on the second layer intermediate metal layer, the x probe card 2053 on the x layer intermediate metal layer, the n-1 probe card 2054 on the n-1 layer intermediate metal layer, at the n probe card 2055 on the n layer intermediate metal layer, probe card 2056, probe card 2057 on the top layer metallic layer and the probe card 2058 on the passivation layer on first top layer metallic layer; Wherein, n is the integer more than or equal to 1; X is smaller or equal to n and more than or equal to 1 integer.The lining plank of every layer of probe version of probe version interconnection layer 205 of the present invention for inserting for probe in order to test.
Second metal interconnecting layer 206 is to be made when making first metal interconnecting layer 204, and second metal interconnecting layer 206 comprises n layer intermediate metal layer and 2 layers of top layer metallic layer; The top layer metallic layer 2067 of second metal interconnecting layer 206 is communicated with the top layer metallic layer of first metal interconnecting layer 204 and bottom metal layer 2061 is communicated with the bottom probe card 2051 of probe card interconnection layer 205; The through hole that every layer of metal level of second metal interconnecting layer 206 offered by the dielectric layer of interlayer connects into the 3rd path.Second metal interconnecting layer 206 comprises n+2 layer metal level, is respectively: ground floor intermediate metal layer 2061, second layer intermediate metal layer 2062, x layer intermediate metal layer 2063, n-1 layer intermediate metal layer 2064, n layer intermediate metal layer 2065, first top layer metallic layer 2066 and top layer metallic layer 2067; Wherein, n is the integer more than or equal to 1; X is smaller or equal to n and more than or equal to 1 integer.
Make the first metal connecting line 207 at the ground floor metal level 2061 of second metal interconnecting layer 206 and 2051 of the probe cards of probe card interconnection layer 205; Between the top-level metallic interconnection layer of the top-level metallic interconnection layer 2067 of second metal interconnecting layer 206 and first metal interconnecting layer 204, make the second metal connecting line 208.
If adopting the device of present embodiment tests semiconductor device to be measured, before test, the first metal connecting line 207 linking probe plate interconnection layers 205 of one end of the 3rd path of second metal interconnecting layer 206 by making, the other end connect the top layer metallic layer of first metal interconnecting layer 204 by the second metal connecting line of making 208; If the probe card in the probe card interconnection layer 205 is collected a large amount of plasma electric charges is arranged, because the threeway roadlock has ended the plasma electric charge and has conducted to first path, most of plasma electric charge is derived wafer by alternate path and the path that diode 203 forms before test, the plasma electric charge that falls the probe card collection little is to the infringement of metal-oxide-semiconductor 202.
Fig. 3 makes the method flow diagram of testing apparatus for the present invention.Now in conjunction with Fig. 3, the method for the present invention being made testing apparatus describes, and is specific as follows:
Step 301: on wafer, make first semiconductor device and reach in order to derive second semiconductor device of plasma electric charge;
First semiconductor device is a semiconductor device to be measured, and this semiconductor device to be measured is a metal-oxide-semiconductor, and this metal-oxide-semiconductor can be P type metal-oxide-semiconductor field effect transistor, also can be N type metal-oxide-semiconductor field effect transistor; Semiconductor device to be tested in the present embodiment is a P type metal-oxide-semiconductor 202; Second semiconductor device is in order to derive the diode 203 of plasma electric charge.
On wafer, form shallow channel isolation area 201, be used to isolate metal-oxide-semiconductor 202 and diode 203; To form P type metal-oxide-semiconductor is example, by N type ion implantation technology, on Semiconductor substrate, form the N trap, adopt deposition, etching technics to form gate oxide 2023 and grid 2024 successively at crystal column surface then, be that mask carries out the injection of P type ion then, form source electrode 2022 and drain electrode 2021 with grid 2024; Form diode 203 when forming P type metal-oxide-semiconductor field effect transistor, described diode 203 comprises the N utmost point and the P utmost point, and the N trap is the N utmost point, carries out the P type and inject in the zonule of N trap, and formed p type island region territory is the P utmost point.On wafer, make the method for P type metal-oxide-semiconductor and the method for making N type metal-oxide-semiconductor and belong to known technology, do not giving unnecessary details at this.Because testing apparatus of the present invention both can be tested P type metal-oxide-semiconductor, also can test N type metal-oxide-semiconductor, semiconductor device to be measured is in the present invention no longer distinguished P type metal-oxide-semiconductor and N type metal-oxide-semiconductor, and semiconductor device to be measured of the present invention is a metal-oxide-semiconductor.
Step 302: on first semiconductor device of wafer, make first metal interconnecting layer, on second semiconductor device of wafer, make the probe card interconnection layer;
At first, utilize chemical vapour deposition (CVD) and photoetching to make connected through hole at the grid 2024 lip-deep dielectric layers of metal-oxide-semiconductor 202, the dielectric layer that utilizes identical method extremely to go up at the P of diode 203 is made connected through hole;
Secondly, the through hole that is connected with grid 2024 with through hole that diode 203 is connected on lay the ground floor metal level, utilize photoetching to remove the part metals layer of this layer, with the bottom probe card 2051 of the bottom metal layer that forms first metal interconnecting layer 204, the antenna 2041 that is connected with bottom metal layer and probe card interconnection layer 205;
At last, utilize chemical vapour deposition (CVD) and photoetching, when making every layer of metal level of first metal interconnecting layer 204, make probe card at this layer, and every layer of metal level of first metal interconnecting layer 204 connects into first path by the through hole of making at the dielectric layer of interlayer, and every layer of probe card of probe card interconnection layer 205 connects into alternate path by the through hole of making at the dielectric layer of interlayer.
First path, one end connects metal-oxide-semiconductor 202; Alternate path one end connects the P utmost point of diode 203.
Step 303: when making first metal interconnecting layer, in each layer metal level, make antenna;
When making every layer of metal level of first metal interconnecting layer 204,, on every layer of metal level, make the antenna that is connected with this layer metal level by photoetching according to the requirement of the manufacture craft of antenna; Antenna has certain area, in order to collect the plasma electric charge that produces in the manufacturing process; And some antenna has stronger positive charge capacity gauge, and some antenna has stronger negative electrical charge capacity gauge.
Step 304: when making first metal interconnecting layer, make second metal interconnecting layer;
Utilize chemical vapour deposition (CVD) and photoetching, when making belongs to each layer metal level of first metal interconnecting layer 204, make each layer metal of second metal interconnecting layer 206, and the through hole of making on the dielectric layer of each layer metal by interlayer of second metal interconnecting layer 206 connects into the 3rd path;
Make the first metal connecting line 207 at the bottom metal layer 2061 of second metal interconnecting layer 206 and 2051 of the bottom probe cards of probe card interconnection layer 205, be connected the diode P utmost point with first path in order to a end and be communicated with end connection the 3rd path; Make second metal wire 208 at the top layer metallic layer 2067 of second metal interconnecting layer 206 and 2047 of the top layer metallic layers of first metal interconnecting layer 204, connect the end that first path is not communicated with metal-oxide-semiconductor 202 in order to the other end with the 3rd path.
Step 305: finish.
In the above-mentioned preferred embodiment of the present invention, be made in the groove of chip chamber of wafer at the antenna of every layer of making in diode 203, probe card interconnection layer 205, second interconnection layer 206 and first interconnection layer 204.
In the above-mentioned preferred embodiment of the present invention, the 3rd path not only can put on alternate path when testing test voltage puts on the metal-oxide-semiconductor 202 that is communicated with first path, and can stop the plasma electric charge of collecting on each layer probe card to import first path before test; The plasma electric charge of collecting on each layer probe card of probe card interconnection layer 205 is by deriving wafer with the diode 203 anodal alternate paths that are connected, and the plasma electric charge that has reduced to form on the probe card is treated the PID infringement of surveying semiconductor device.
In sum, more than be preferred embodiment of the present invention only, be not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. a plasma imports infringement PID testing apparatus, comprising:
First metal interconnecting layer of on first semiconductor device of wafer, producing;
In wafer in order to second semiconductor device of deriving the plasma electric charge on, the probe card interconnection layer produced simultaneously with described first metal interconnecting layer;
In described first metal interconnecting layer, every layer of metal level also is manufactured with simultaneously in order to collecting the antenna of plasma electric charge, and the through hole that every layer of metal level offered by the dielectric layer of interlayer connects into first path;
In described probe card interconnection layer, the through hole that every layer of probe card offered by the dielectric layer of interlayer connects into alternate path;
It is characterized in that, also comprise second metal interconnecting layer of producing simultaneously with described first metal interconnecting layer;
The through hole that the bottom probe card conducting of the top layer metallic layer conducting of the top layer metallic layer of described second metal interconnecting layer and described first metal interconnecting layer, bottom metal layer and described probe card interconnection layer and every layer of metal level are offered by the dielectric layer of interlayer connects into the 3rd path, conducts to first path in order to the plasma electric charge that stops the probe card interconnection layer to be collected.
2. testing apparatus according to claim 1 is characterized in that,
First metal connecting line that has described bottom metal layer of conducting and described bottom probe card between the bottom probe card of the bottom metal layer of described second metal interconnecting layer and described probe card interconnection layer;
The top-level metallic interlayer of the top layer metallic layer of described second metal interconnecting layer and described first metal interconnecting layer has the second metal connecting line of the top layer metallic layer of the top layer metallic layer of conducting second metal interconnecting layer and first metal interconnecting layer.
3. testing apparatus according to claim 1 is characterized in that,
Described first semiconductor device is a metal-oxide-semiconductor;
Described second semiconductor device is a diode.
4. method of making the PID testing apparatus, this method comprises:
Making first semiconductor device on wafer reaches in order to derive second semiconductor device of plasma electric charge;
On first semiconductor device of wafer, make first metal interconnecting layer, and when making first metal interconnecting layer, on second semiconductor device, make the probe card interconnection layer;
When making first metal interconnecting layer, in each layer metal level of first metal interconnecting layer, be manufactured with antenna in order to collect the plasma electric charge and to be connected with this layer metal level;
It is characterized in that this method also comprises:
When making first metal interconnecting layer and probe card interconnection layer, make second metal interconnecting layer that top layer is communicated with the top layer metallic layer of first metal interconnecting layer, bottom is communicated with the bottom probe card of probe card interconnection layer.
5. method according to claim 4 is characterized in that, described making second metal interconnecting layer comprises:
When the bottom probe card of the bottom metal layer of making first metal interconnecting layer and probe card interconnection layer, utilize chemical vapour deposition (CVD) and photoetching making not to be communicated with the bottom metal layer of second metal interconnecting layer of first metal interconnecting layer and connection bottom probe card;
When other each layer probe cards of other each layer metal levels of making first metal interconnecting layer and probe card interconnection layer, utilize chemical vapour deposition (CVD) and photoetching not to be communicated with the metal level of second metal interconnecting layer of the metal level of first metal interconnecting layer of this layer and probe card every layer of making;
Utilize photoetching and chemical vapour deposition (CVD) to be communicated with the top layer metallic layer of first metal interconnecting layer and the top layer metallic layer of second metal interconnecting layer.
6. method according to claim 4 is characterized in that,
Described first semiconductor device is a metal-oxide-semiconductor;
Described second semiconductor device is a diode.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102142429B (en) * | 2010-01-28 | 2013-02-27 | 中芯国际集成电路制造(上海)有限公司 | Plasma induced damage (PID) detection structure and manufacture method thereof |
| CN103779331A (en) * | 2012-10-25 | 2014-05-07 | 中芯国际集成电路制造(上海)有限公司 | Plasma induced damage detecting structure and manufacture method |
| CN103941068A (en) * | 2013-01-22 | 2014-07-23 | 中芯国际集成电路制造(上海)有限公司 | On-chip sensor for measuring threshold voltage drifting |
| CN105355577A (en) * | 2014-08-21 | 2016-02-24 | 中芯国际集成电路制造(上海)有限公司 | Plasma damage test structure and manufacturing method thereof |
| CN107452715A (en) * | 2016-04-28 | 2017-12-08 | 英飞凌科技股份有限公司 | Semiconductor devices and method for the gate insulator of test transistor structure |
| CN113497002A (en) * | 2020-04-07 | 2021-10-12 | 长鑫存储技术有限公司 | PID test structure and semiconductor test structure |
| CN116093022A (en) * | 2023-04-10 | 2023-05-09 | 北京华封集芯电子有限公司 | Chip and chip design method |
| CN116130461A (en) * | 2022-12-21 | 2023-05-16 | 武汉新芯集成电路制造有限公司 | Test structure and test method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6396075B1 (en) * | 1998-05-27 | 2002-05-28 | Texas Instruments Incorporated | Transient fuse for change-induced damage detection |
| US6372525B1 (en) * | 1999-12-20 | 2002-04-16 | Taiwan Semiconductor Manufacturing Company | Wafer-level antenna effect detection pattern for VLSI |
| CN101197300B (en) * | 2007-12-25 | 2011-11-09 | 上海宏力半导体制造有限公司 | PPID monitoring method in integrated circuit production process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102142429B (en) * | 2010-01-28 | 2013-02-27 | 中芯国际集成电路制造(上海)有限公司 | Plasma induced damage (PID) detection structure and manufacture method thereof |
| CN103779331A (en) * | 2012-10-25 | 2014-05-07 | 中芯国际集成电路制造(上海)有限公司 | Plasma induced damage detecting structure and manufacture method |
| CN103779331B (en) * | 2012-10-25 | 2016-09-07 | 中芯国际集成电路制造(上海)有限公司 | Plasma induced damage detection structure and preparation method |
| CN103941068A (en) * | 2013-01-22 | 2014-07-23 | 中芯国际集成电路制造(上海)有限公司 | On-chip sensor for measuring threshold voltage drifting |
| CN105355577A (en) * | 2014-08-21 | 2016-02-24 | 中芯国际集成电路制造(上海)有限公司 | Plasma damage test structure and manufacturing method thereof |
| CN107452715B (en) * | 2016-04-28 | 2021-06-08 | 英飞凌科技股份有限公司 | Semiconductor device and method for testing gate insulation of transistor structure |
| CN107452715A (en) * | 2016-04-28 | 2017-12-08 | 英飞凌科技股份有限公司 | Semiconductor devices and method for the gate insulator of test transistor structure |
| CN113497002A (en) * | 2020-04-07 | 2021-10-12 | 长鑫存储技术有限公司 | PID test structure and semiconductor test structure |
| WO2021203889A1 (en) * | 2020-04-07 | 2021-10-14 | 长鑫存储技术有限公司 | Pid test structure and semiconductor test structure |
| CN113497002B (en) * | 2020-04-07 | 2024-02-06 | 长鑫存储技术有限公司 | PID test structure and semiconductor test structure |
| CN116130461A (en) * | 2022-12-21 | 2023-05-16 | 武汉新芯集成电路制造有限公司 | Test structure and test method |
| CN116093022A (en) * | 2023-04-10 | 2023-05-09 | 北京华封集芯电子有限公司 | Chip and chip design method |
| CN116093022B (en) * | 2023-04-10 | 2024-05-10 | 北京华封集芯电子有限公司 | Chip and chip design method |
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