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CN103296010A - 屏蔽插入机构及具有集成的电磁屏蔽物的半导体封装 - Google Patents

屏蔽插入机构及具有集成的电磁屏蔽物的半导体封装 Download PDF

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Publication number
CN103296010A
CN103296010A CN2012103711735A CN201210371173A CN103296010A CN 103296010 A CN103296010 A CN 103296010A CN 2012103711735 A CN2012103711735 A CN 2012103711735A CN 201210371173 A CN201210371173 A CN 201210371173A CN 103296010 A CN103296010 A CN 103296010A
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shielding
tube core
active tube
electromagnetic screen
dielectric layer
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CN103296010B (zh
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桑帕施·K·V·卡里卡兰
胡坤忠
赵子群
雷佐尔·拉赫曼·卡恩
彼得·沃伦坎普
陈向东
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Avago Technologies International Sales Pte Ltd
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Zyray Wireless Inc
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Abstract

本发明涉及屏蔽插入机构及具有集成的电磁屏蔽物的半导体封装。在本发明中公开了位于顶部有源管芯与底部有源管芯之间用于屏蔽所述有源管芯避免电磁噪声的屏蔽插入机构的多种实施方式。一种实施方式包括插入机构介质层、所述插入机构介质层内的硅通孔（TSV）、以及电磁屏蔽物。TSV将电磁屏蔽物连接到第一固定电位上。所述电磁屏蔽物可以包括侧向延伸横过屏蔽插入机构的导电层格栅。所述屏蔽插入机构还可以包括连接到另一固定电位上的另一个电磁屏蔽物。本发明还公开了具有集成的电磁屏蔽物的半导体封装。

Description

屏蔽插入机构及具有集成的电磁屏蔽物的半导体封装
技术领域
本发明总体涉及半导体领域，具体涉及用于屏蔽有源管芯避免电磁噪声的屏蔽插入机构及具有集成的电磁屏蔽物的半导体封装。
背景技术
对于减小半导体封装尺寸同时增强功能性存在日益增长的需要。这种需要典型地导致半导体封装设计成容纳多于一个半导体管芯，其中每个管芯都可以是包含众多晶体管以及多层互连的复合管芯。在运行期间，所述复合管芯产生流过管芯上多个互连的大量瞬态电流。大量的瞬态电流以及伴随的瞬态电压进而导致由每个管芯产生的大量的电磁噪声。由于高级封装包括紧密接近的多个管芯，来自一个管芯的电磁噪声对封装内其他管芯会具有非常不希望的影响。更具体地，由一个管芯产生的电磁噪声典型地在所述封装内其他管芯中诱导不希望的噪声电流以及噪声电压。由于半导体封装尺寸减小，以及邻近管芯之间分隔减小，以及当将多于两个管芯封装在同一个封装内时，加剧了诱导不希望噪声的问题。
此外，每个半导体封装可能暴露于来自系统中其他部件（例如其他有噪声的半导体封装）的外部电磁噪声。减少电磁噪声的影响是高级封装设计的重要目标。
发明内容
本发明是针对具有集成的电磁屏蔽物的半导体封装，基本上如在至少一个附图中所示和/或与其相结合进行说明，更全面地如在以下对本申请的描述中提出的。
本发明的一方面，提供一种位于顶部有源管芯与底部有源管芯之间用于屏蔽所述顶部有源管芯以及所述底部有源管芯避免电磁噪声的屏蔽插入机构，所述屏蔽插入机构包括：
插入机构介质层；
所述插入机构介质层内的硅通孔（TSV）；
通过所述TSV连接到固定电位上的电磁屏蔽物。
优选地，本申请的插入机构介质层，其中所述电磁屏蔽物包括导电层格栅。
优选地，本申请的插入机构介质层，其中所述电磁屏蔽物全部地布置在所述插入机构介质层内。
优选地，本申请的插入机构介质层，其中所述电磁屏蔽物部分地布置在所述插入机构介质层内。
优选地，本申请的插入机构介质层，其中所述固定电位是接地电位。
优选地，本申请的插入机构介质层，其中所述固定电位是Vdd电位。
优选地，本申请的插入机构介质层，进一步包括连接到另外的固定电位上的另外的电磁屏蔽物。
优选地，本申请的插入机构介质层，其中所述另外的电磁屏蔽物至少部分地重叠所述电磁屏蔽物。
优选地，本申请的插入机构介质层，其中所述固定电位是Vdd电位，而所述另外的固定电位是接地电位。
本发明另一方面，提供一种半导体封装，包括：
底部有源管芯；
位于所述底部有源管芯之上的屏蔽插入机构；
位于所述屏蔽插入机构之上的顶部有源管芯，所述屏蔽插入机构用于屏蔽所述顶部有源管芯以及所述底部有源管芯避免电磁噪声；
所述屏蔽插入机构具有插入机构介质层、所述插入机构介质层内的硅通孔（TSV）、以及通过所述TSV连接到固定电位上的电磁屏蔽物。
优选地，本申请的半导体封装，其中所述屏蔽插入机构侧向地延伸超过所述底部有源管芯以及所述顶部有源管芯。
优选地，本申请的半导体封装，其中所述屏蔽插入机构的一部分侧向地延伸超过所述底部有源管芯以及所述顶部有源管芯，所述TSV位于所述屏蔽插入机构的所述部分内；所述屏蔽插入机构进一步包括位于所述屏蔽插入机构的所述部分底部表面上的焊料凸起，所述焊料凸起连接到所述TSV上。
优选地，本申请的半导体封装，其中所述电磁屏蔽物包括导电层格栅。
优选地，本申请的半导体封装，其中所述电磁屏蔽物全部地布置在所述插入机构介质层内。
优选地，本申请的半导体封装，其中所述固定电位是接地电位或Vdd电位。
本发明的又一方面，提供一种半导体封装，包括：
底部有源管芯；
位于所述底部有源管芯之上的屏蔽插入机构；
位于所述屏蔽插入机构之上的顶部有源管芯，所述屏蔽插入机构用于屏蔽所述顶部有源管芯以及所述底部有源管芯避免电磁噪声；
所述屏蔽插入机构具有通过线焊连接到固定电位上的电磁屏蔽物。
优选地，本申请的半导体封装，其中所述屏蔽插入机构的一部分侧向地延伸超过所述底部有源管芯以及所述顶部有源管芯；所述屏蔽插入机构进一步包括位于所述屏蔽插入机构的所述部分顶部表面上的外周垫，所述外周垫连接到所述电磁屏蔽物上，并且所述线焊连接到所述外周垫上。
优选地，本申请的半导体封装，其中所述电磁屏蔽物包括导电层格栅。
优选地，本申请的半导体封装，其中所述屏蔽插入机构进一步包括插入机构介质层，所述电磁屏蔽物全部地布置在所述插入机构介质层内。
优选地，本申请的半导体封装，其中所述固定电位是接地电位或Vdd电位。
附图说明
图1显示了具有堆叠在底部有源管芯上的顶部有源管芯的半导体封装的一个实施方式的横截面视图。
图2显示了具有堆叠在屏蔽插入机构上，进一步地堆叠在底部有源管芯上的顶部有源管芯的半导体封装的一个实施方式的横截面视图。
图3A显示了屏蔽插入机构的一个实施方式的横截面视图。
图3B显示了图3A中所示的屏蔽插入机构的俯视图。
图4显示了包括具有焊料凸起的屏蔽插入机构的半导体封装的一个实施方式的横截面视图。
图5显示了包括具有线焊的屏蔽插入机构的半导体封装的一个实施方式的横截面视图。
具体实施方式
下面的说明包含有关本发明实施方式的具体信息。本领域技术人员应当理解的是本发明能够以与在此具体讨论不同的方式实施。本申请的附图以及它们伴随的详细说明仅针对示例性实施方式。除非另有说明，这些图中类似或对应的元件可以通过类似或对应的参考号进行表示。此外，本申请中的附图和说明通常不是按照比例的，并且不旨在对应于实际相关尺寸。
图1表示使用已知技术制造的半导体封装的一个实例的横截面视图。如图1中所示，半导体封装100包括顶部有源管芯110以及底部有源管芯130。顶部有源管芯110包括位于基板118上的介质层116。顶部有源管芯110包括晶体管112，它们是通过互连114相互连接的众多晶体管的实例。如图1中可见，互连114可以部分地布置在介质层116内。互连114可以进一步将晶体管112连接到硅通孔（TSV）120上。TSV120可以延伸完全通过介质层116以及基板118（如图1中所示）。虽然图1说明了具有4个TSV120的顶部有源管芯110，在其他实施方式中，顶部有源管芯110可以包括不同数量的TSV120。另外，顶部有源管芯110还可以包括微凸起（microbump）122，在这个实施方式中这些微凸起连接到TSV120上。
底部有源管芯130包括位于基板138上的介质层136。底部有源管芯130包括通过互连134相互连接的晶体管132。如图1中可见，互连134可以部分地布置在介质层136内。互连134可以进一步将晶体管132连接到TSV140上。TSV140可以延伸完全通过介质层136以及基板138（如图1中所示）。虽然图1说明了具有4个TSV140的底部有源管芯130，在其他实施方式中，底部有源管芯130可以包括不同数量的TSV140。另外，底部有源管芯130还可以包括可以连接到TSV140上的微凸起142。此外，微凸起142将顶部有源管芯110连接到底部有源管芯130上。微凸起142能够以电方式以及机械方式将TSV120连接到TSV140上。
在图1中，顶部有源管芯110和底部有源管芯130具有类似的尺寸和复杂度。然而，在其他实施方式中，顶部有源管芯110和底部有源管芯130可以不相似。此外，在其他实施方式中，为了讨论简洁的目的，半导体封装100可以包括图1中未显示的其他特征。
当电流流过典型地在多个金属层中互连金属的半导体管芯的信号通道时，产生了电磁场以及噪声。在半导体封装100中，互连114和134分别是顶部有源管芯110和底部有源管芯130信号通道的实例。在常规工作期间，流过互连134的瞬态电流生成电磁场102。在图1中，电磁场102的电场部分以虚线箭头形式指示，而电磁场102的磁场部分以点线椭圆形形式指示。如图1中可见，电磁场102使互连114与134之间电磁耦合，因此产生电磁噪声。由于电磁场102，电磁噪声不令人希望地在由互连114和134传输的信号中产生串扰噪声。
更具体地，由于由互连134中的电流产生的磁场，电磁场102在互连114中诱导了电流。由于由互连134产生的电场，电磁场102还可以使互连114与134之间电容耦合。此外，由于堆叠（图1中未显示）内另外的或不相邻的管芯之间可能发生电磁耦合，串扰噪声可能不限于顶部有源管芯110以及底部有源管芯130。即使串扰噪声较小，信号上的串扰噪声可能损害这些有源管芯的功能。
转到图2，图2表示包括屏蔽插入机构的一个实施方式的半导体封装的横截面视图。如图2中所示，半导体封装200包括底部有源管芯230、屏蔽插入机构250、以及顶部有源管芯210。顶部有源管芯210可以相应于图1中的顶部有源管芯110。底部有源管芯230可以相应于图1中的底部有源管芯130。
顶部有源管芯210包括位于基板218上的介质层216。顶部有源管芯210还包括通过互连214相互连接的晶体管212。如图2中可见，互连214可以部分地布置在介质层216内。互连214可以进一步将晶体管212连接到TSV220上。TSV220可以延伸完全通过介质层216以及基板218（如图2中所示）。虽然图2说明了具有4个TSV220的顶部有源管芯210，在其他实施方式中，顶部有源管芯210可以包括不同数量的TSV220。另外，顶部有源管芯210还包括可以连接到TSV220上的微凸起222。
此外，晶体管212、互连214、介质层216、基板218、TSV220、以及微凸起222可以分别相应于图1中的晶体管112、互连114、介质层116、基板118、TSV120、以及微凸起122。
底部有源管芯230包括位于基板238上的介质层236。底部有源管芯230还包括通过互连234相互连接的晶体管232。如图2中可见，互连234可以部分地布置在介质层236内。互连234可以进一步将晶体管232连接到TSV240上。TSV240可以延伸完全通过介质层236以及基板238（如图2中所示）。虽然图2说明了具有4个TSV240的底部有源管芯230，在其他实施方式中，底部有源管芯230可以包括不同数量的TSV240。另外，底部有源管芯230还包括可以连接到TSV240上的微凸起242。此外，微凸起242将屏蔽插入机构250附连到底部有源管芯230上。微凸起242能够以电方式以及机械方式将TSV240连接到TSV260、270以及272上。
虽然在图2中顶部有源管芯210和底部有源管芯230具有类似的尺寸和复杂度，在其他实施方式中，顶部有源管芯210和底部有源管芯230可以不相似。此外，晶体管232、互连234、介质层236、基板238、TSV240、以及微凸起242可以分别相应于图1的晶体管132、互连134、介质层136、基板138、TSV140、以及微凸起142。
屏蔽插入机构250包括位于基板258上的介质层256。屏蔽插入机构250进一步包括电磁屏蔽物252以及电磁屏蔽物254。在图2中所示的实施方式中，电磁屏蔽物252连接到电磁屏蔽物252附近最外面的TSV上，即TSV 270。类似地，电磁屏蔽物254连接到电磁屏蔽物254附近最外面的TSV上，即图2中的TSV272。电磁屏蔽物252和254可以全部地布置在介质层256内。如图2中所示，在介质层256内电磁屏蔽物254重叠电磁屏蔽物252。在本实例中，电磁屏蔽物252和254彼此不接触地重叠。这样，电磁屏蔽物252和254可以连接到相应的固定电位上。电磁屏蔽物252可以连接到Vdd电位（或者接地电位）上，而电磁屏蔽物254可以连接到接地电位（或者Vdd电位）上。
图2表示电磁屏蔽物252和254的示例性实施方式。然而，例如在其他实施方式中，电磁屏蔽物252和254可以不重叠。例如，电磁屏蔽物252和254可以具有小于图2中所述的尺寸，使得在介质层256内它们不重叠。在其他实施方式中，电磁屏蔽物252和254可以彼此连接，或者另外地连接到同一个固定电位上。可选地，电磁屏蔽物252和254可以连接到任何其他固定电位上。此外，在其他实施方式中，电磁屏蔽物252和254可以连接到其他TSV260、270、以及272上。然而，电磁屏蔽物252和254可以直接连接到相应的固定电位上，或可以通过任何其他装置进行连接，例如通过互连264和266以及微凸起262。
TSV260、270、以及272可以延伸完全通过介质层256以及基板258（如图2中所示）。虽然图2说明了包括4个TSV的屏蔽插入机构250，在其他实施方式中，屏蔽插入机构250可以包括不同数量的TSV。屏蔽插入机构250还包括可以分别将TSV260、270、以及272连接到TSV220上的微凸起262（如图2中可见）。微凸起262进一步将顶部有源管芯210附连到屏蔽插入机构250上。还是如图2所示，顶部有源管芯210、屏蔽插入机构250、以及底部有源管芯230可以通过至少TSV220、260、270、272、和240、以及微凸起262和242进行电连接。
在常规工作期间，流过底部有源管芯230的互连234的瞬态电流产生电磁场202。在图2中，电磁场202的电场部分以虚线箭头形式指示，而电磁场202的磁场部分以点线椭圆形指示。然而，与图1相对比，屏蔽插入机构250屏蔽了顶部有源管芯210的互连214避免与底部有源管芯230的互连234电磁耦合。具体地，电磁场202使互连234与电磁屏蔽物252和254，而不是与互连234电磁耦合。实际上，屏蔽插入机构250基本上消除了电磁场202。例如，电磁场202在电磁屏蔽物252和254中而不是在互连214中诱导电流。电磁场202还可以使互连234与电磁屏蔽物252和254而不是与互连214之间电容耦合。
然而，如图2中可见，剩余的电磁场204仍然可以使顶部有源管芯210的互连214与底部有源管芯230的互连234电磁耦合。与图1中电磁场102相比较，由于电磁场202电磁噪声被显著地降低。这样，与不具备屏蔽插入机构的半导体封装100相比较，具有屏蔽插入机构250的半导体封装200可以有利地具有降低的电磁噪声。
进一步如图2中可见，电磁屏蔽物252和254连接到固定电位上。通过将电磁屏蔽物252和254连接到电位上，屏蔽插入机构250提供了去耦电容的额外优点，这可以为电源完整性提供另外的益处。例如，在图2中，电磁屏蔽物252连接到Vdd电位上，而电磁屏蔽物254连接到接地电位上。这样，电磁屏蔽物252和254可以在Vdd和接地电位之间形成去耦电容。
转到图3A和3B，图3A和3B表示屏蔽插入机构的一个实施方式。图3A表示屏蔽插入机构350的横截面视图，而图3B表示屏蔽插入机构350的俯视图。屏蔽插入机构350可以相应于图2中的屏蔽插入机构250。具体地，介质层356、基板358、TSV360、微凸起362、互连364、互连366、TSV370、TSV372、电磁屏蔽物352、以及电磁屏蔽物354可以分别相应于图2中的介质层256、基板258、TSV260、微凸起262、互连264、互连266、TSV270、TSV272、电磁屏蔽物252、以及电磁屏蔽物254。为了简洁的目的，屏蔽插入机构350与屏蔽插入机构250之间的相似处将不再进行讨论。
在图3B中，基板358被介质层356遮盖，并且微凸起362未显示。此外，为了说明布置在介质层356顶部表面的互连364和366，以及布置在介质层356内的电磁屏蔽物252和254，介质层356的多个部分未显示。
电磁屏蔽物352和354是由排列成格栅的导电材料（例如金属）制造的。例如，如图3B中可见，电磁屏蔽物352包括导电层的栅格。类似地，电磁屏蔽物354包括导电层的栅格。另外如图3A中可见，电磁屏蔽物354布置在介质层356内，虽然上述电磁屏蔽物352也布置在介质层356内。这种排布方式导致电磁屏蔽物354至少部分地重叠电磁屏蔽物352（如图3A和3B中所示）。然而，在其他实施方式中，电磁屏蔽物352和354可以采取其他形状（例如平板），并且还可以配置成不重叠。
图3B进一步显示了TSV360、370、以及372的一个实施方式。在图3B中，屏蔽插入机构350包括沿着屏蔽插入机构350的外部边缘成行排列的TSV，例如TSV370以及TSV372。屏蔽插入机构350进一步包括远离外部边缘内部成行的TSV，例如TSV360。这种TSV排布方式可以反映有源管芯（例如图2中的顶部有源管芯210以及底部有源管芯230）的TSV排布方式。
在图3B中所示的实施方式中，互连364仅将电磁屏蔽物352沿着外部边缘连接到TSV上，即TSV370。类似地，互连366仅将电磁屏蔽物354沿着外部边缘连接到TSV上，即TSV372。在其他实施方式中，电磁屏蔽物352和354可以连接到其他TSV360上。
在图3A和3B中，电磁屏蔽物352和354分别直接连接到第一和第二固定电位上。然而，图4和5表示用于电连接电磁屏蔽物的可替代的实施方式。
现在转到图4，图4表示根据屏蔽插入机构的一个实施方式的半导体封装的横截面视图。图4说明了半导体封装400，包括底部有源管芯430、位于底部有源管芯430上的屏蔽插入机构450、以及位于屏蔽插入机构450上的顶部有源管芯410。包括晶体管432、互连434、介质层436、基板438、TSV440、以及微凸起442的底部有源管芯430可以分别相应于图2中的底部有源管芯230、晶体管232、互连234、介质层236、基板238、TSV240、以及微凸起242。同样地，包括晶体管412、互连414、介质层416、基板418、TSV420、以及微凸起422的顶部有源管芯410可以分别相应于图2中的顶部有源管芯210、晶体管212、互连214、介质层216、基板218、TSV220、以及微凸起222。为了简洁的目的，顶部有源管芯410和底部有源管芯430将不再进行讨论。
屏蔽插入机构450可以相应于图2中的屏蔽插入机构250。此外，电磁屏蔽物452和454、介质层456、基板458、TSV460、微凸起462、互连464和466、以及TSV470和TSV472可以分别相应于图2中的电磁屏蔽物252和254、介质层256、基板258、TSV260、微凸起262、互连264和266、以及TSV270和TSV272。为了简洁的目的，屏蔽插入机构450与屏蔽插入机构250之间的相似处将不再进行讨论。
在图4中说明的实施方式中，相对于顶部有源管芯410以及底部有源管芯430，屏蔽插入机构450在大小上与屏蔽插入机构350和250不同。如图4中所示，屏蔽插入机构450侧向地延伸超过顶部有源管芯410以及底部有源管芯430。具体地在图4中，屏蔽插入机构450在两侧侧向地延伸超过顶部有源管芯410以及底部有源管芯430，这不是限制性特征。
TSV470和472布置在侧向地延伸超过顶部有源管芯410以及底部有源管芯430的屏蔽插入机构450的部分内。TSV470和472分别通过互连464和466连接到电磁屏蔽物452和454上。TSV470和472未连接到底部有源管芯430的TSV440或顶部有源管芯410的TSV420上。相反地，TSV470和472连接到焊料凸起474上。如图4中可见，焊料凸起474布置在侧向地延伸超过顶部有源管芯410以及底部有源管芯430的屏蔽插入机构450的部分的底部表面上。焊料凸起474可以连接到第一和第二固定电位上（例如Vdd或接地电位）。在图4中，焊料凸起474是常规的焊料凸起（例如C4凸起），这允许更容易地外部连接到半导体封装400上。
焊料凸起474有利地布置在有源管芯边界外部。焊料凸起474可以提供连接到半导体封装400可以附连到其上的封装基板上（图4中未显示）。焊料凸起474进一步允许电磁屏蔽物452和454电连接到通过有源管芯的TSV不可使用的电位上。例如，在图4中，沿着半导体封装400的一侧可以将TSV420、460、以及440连接到第一电位上，并且可以沿着另一侧将TSV420、460、以及440连接到第二电位上。然而，TSV470和472与TSV420、460、以及440电分离。因此，TSV470和472可以通过焊料凸起474将电磁屏蔽物452和454分别连接到第三和第四电位上。
参考图5，图5表示屏蔽插入机构的另一个实施方式的横截面视图。半导体封装500包括底部有源管芯530、位于底部有源管芯530上的屏蔽插入机构550、以及位于屏蔽插入机构550上的底部有源管芯510。包括晶体管532、互连534、介质层536、基板538、TSV540、以及微凸起542的底部有源管芯530基团分别相应于图2中的底部有源管芯230、晶体管232、互连234、介质层236、基板238、TSV240、以及微凸起242。同样地，包括晶体管512、互连514、介质层516、基板518、TSV520、以及微凸起522的顶部有源管芯510可以分别相应于图2中的顶部有源管芯210、晶体管212、互连214、介质层216、基板218、TSV220、以及微凸起222。为了简洁的目的，顶部有源管芯510以及底部有源管芯530将不再进行讨论。
屏蔽插入机构550可以相应于图2中的屏蔽插入机构250。此外，电磁屏蔽物552和554、介质层556、基板558、TSV560、微凸起562、以及互连564和566可以分别相应于图2中的电磁屏蔽物252和254、介质层256、基板258、TSV260、微凸起262、以及互连264和266。为了简洁的目的，屏蔽插入机构450与屏蔽插入机构250和350之间的相似处将不再进行讨论。
类似于图4中的屏蔽插入机构450，屏蔽插入机构550在两侧侧向地延伸超过顶部有源管芯510以及底部有源管芯530（虽然侧面的数量没有限制）。此外，类似于电磁屏蔽物452和454，电磁屏蔽物552和554可以电连接到通过有源管芯的任何TSV不可使用的电位上。不同于屏蔽插入机构450，电磁屏蔽物552和554通过线焊570和572连接到第一和第二固定电位上。如图5中可见，线焊570和572可以外部连接到半导体封装500上。例如，线焊570和572可以连接到半导体封装500附连到其上的封装基板（图5中未显示）上的电位上。另外，线焊570和572通过外周垫576分别连接到电磁屏蔽物552和554上。如图5所示，线焊570和572以及外周垫576布置在有源管芯边界外面。
外周垫576位于屏蔽插入机构550的介质层556的顶部表面上。具体地，外周垫576布置在侧向地延伸超过顶部有源管芯510以及底部有源管芯530的屏蔽插入机构550的部分之上（如图5所示）。线焊570和572可以连接到Vdd和/或接地电位，或者其他固定电位上。线焊570和572允许更简单地外部连接，并且允许进一步设计灵有源。
线焊570和572提供了超过由电磁屏蔽物552和554所提供的屏蔽作用的额外电磁屏蔽作用的额外的益处。如图5中可见，通常将电磁屏蔽物552和554限制到顶部有源管芯510以及底部有源管芯530的尺寸。由于线焊570和572分别连接到与电磁屏蔽物552和554相同的固定电位上，线焊570和572提供了类似的电磁屏蔽作用。线焊570和572延伸超过电磁屏蔽物552和554，并且因此可以提供沿着半导体封装500的对应侧面的电磁屏蔽作用。
因此，通过将电磁屏蔽物置于堆叠的有源管芯的有源区域之间，在此公开的概念的各种实施方式有利地屏蔽有源管芯避免电磁噪声。此外，公开的实施方式有利地能够生产具有电磁屏蔽物的插入机构。所述的实施方式公开了位于顶部有源管芯与底部有源管芯之间的屏蔽插入机构，并且具有插入机构介质层、通过所述插入机构介质层的TSV、以及通过所述TSV连接到固定电位上的电磁屏蔽物。其结果是，本发明的概念有利地能够在互相堆叠的有源管芯之间进行电磁屏蔽。
从上述说明中可以清楚的是，可以使用各种技术来实现本申请中所述的概念，而不偏离这些概念的范围。此外，尽管已经具体地参考某些实施方式说明了这些概念，本领域普通技术人员应当理解的是，可以在形式和详细内容方面进行改变，而不偏离这些概念的精神和范围。这样，在所有方面而言，所述的实施方式应当认为是示例性的，而不是限制性的。还应当理解的是本申请不限于此处所述的具体实施方式，而是有可能进行多种重新排布、修改、以及替换，而不偏离本发明的范围。

Claims (10)

1.一种位于顶部有源管芯与底部有源管芯之间用于屏蔽所述顶部有源管芯以及所述底部有源管芯避免电磁噪声的屏蔽插入机构，所述屏蔽插入机构包括：
插入机构介质层；
所述插入机构介质层内的硅通孔（TSV）；
通过所述TSV连接到固定电位上的电磁屏蔽物。
2.根据权利要求1所述的屏蔽插入机构，其中所述电磁屏蔽物包括导电层格栅。
3.根据权利要求1所述的屏蔽插入机构，其中所述电磁屏蔽物全部地布置在所述插入机构介质层内。
4.根据权利要求1所述的屏蔽插入机构，其中所述电磁屏蔽物部分地布置在所述插入机构介质层内。
5.根据权利要求1所述的屏蔽插入机构，进一步包括连接到另外的固定电位的另外的电磁屏蔽物，其中所述另外的电磁屏蔽物至少部分地重叠所述电磁屏蔽物。
6.一种半导体封装，包括：
底部有源管芯；
位于所述底部有源管芯之上的屏蔽插入机构；
位于所述屏蔽插入机构之上的顶部有源管芯，所述屏蔽插入机构用于屏蔽所述顶部有源管芯以及所述底部有源管芯避免电磁噪声；
所述屏蔽插入机构具有插入机构介质层、所述插入机构介质层内的硅通孔（TSV）、以及通过所述TSV连接到固定电位上的电磁屏蔽物。
7.根据权利要求6所述的半导体封装，其中所述屏蔽插入机构侧向地延伸超过所述底部有源管芯以及所述顶部有源管芯。
8.根据权利要求6所述的半导体封装，其中所述屏蔽插入机构的一部分侧向地延伸超过所述底部有源管芯以及所述顶部有源管芯，所述TSV位于所述屏蔽插入机构的所述部分内；
所述屏蔽插入机构进一步包括位于所述屏蔽插入机构的所述部分底部表面上的焊料凸起，所述焊料凸起连接到所述TSV上。
9.一种半导体封装，包括：
底部有源管芯；
位于所述底部有源管芯之上的屏蔽插入机构；
位于所述屏蔽插入机构之上的顶部有源管芯，所述屏蔽插入机构用于屏蔽所述顶部有源管芯以及所述底部有源管芯避免电磁噪声；
所述屏蔽插入机构具有通过线焊连接到固定电位上的电磁屏蔽物。
10.根据权利要求9所述的半导体封装，其中所述屏蔽插入机构的一部分侧向地延伸超过所述底部有源管芯以及所述顶部有源管芯；
所述屏蔽插入机构进一步包括位于所述屏蔽插入机构的所述部分顶部表面上的外周垫，所述外周垫连接到所述电磁屏蔽物上，并且所述线焊连接到所述外周垫上。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106356350A (zh) * 2016-10-11 2017-01-25 广东顺德中山大学卡内基梅隆大学国际联合研究院 一种基于硅通孔互连的系统级封装的电磁耦合抑制方法
CN112786530A (zh) * 2019-11-01 2021-05-11 美光科技公司 封装焊料tsv插入互连
US11587912B2 (en) 2019-11-01 2023-02-21 Micron Technology, Inc. High density pillar interconnect conversion with stack to substrate connection
US11631644B2 (en) 2019-11-01 2023-04-18 Micron Technology, Inc. High density pillar interconnect conversion with stack to substrate connection

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US20140339688A1 (en) * 2013-05-15 2014-11-20 Cavendish Kinetics, Inc. Techniques for the cancellation of chip scale packaging parasitic losses
US9214433B2 (en) * 2013-05-21 2015-12-15 Xilinx, Inc. Charge damage protection on an interposer for a stacked die assembly
US9530730B2 (en) 2013-11-08 2016-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Configurable routing for packaging applications
US9583420B2 (en) 2015-01-23 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufactures
US9281297B2 (en) 2014-03-07 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Solution for reducing poor contact in info packages
US9786633B2 (en) 2014-04-23 2017-10-10 Massachusetts Institute Of Technology Interconnect structures for fine pitch assembly of semiconductor structures and related techniques
US9449947B2 (en) 2014-07-01 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package for thermal dissipation
WO2016025451A1 (en) 2014-08-11 2016-02-18 Massachusetts Institute Of Technology Interconnect structures for assembly of multi-layer semiconductor devices
TWI575695B (zh) * 2014-10-21 2017-03-21 瑞昱半導體股份有限公司 電子裝置和電磁輻射抑制方法
CN105555108B (zh) * 2014-10-28 2018-09-04 瑞昱半导体股份有限公司 电子装置和电磁辐射抑制方法
US9881904B2 (en) 2014-11-05 2018-01-30 Massachusetts Institute Of Technology Multi-layer semiconductor devices fabricated using a combination of substrate and via structures and fabrication techniques
US9971970B1 (en) 2015-04-27 2018-05-15 Rigetti & Co, Inc. Microwave integrated quantum circuits with VIAS and methods for making the same
WO2017015432A1 (en) 2015-07-23 2017-01-26 Massachusetts Institute Of Technology Superconducting integrated circuit
US10134972B2 (en) 2015-07-23 2018-11-20 Massachusetts Institute Of Technology Qubit and coupler circuit structures and coupling techniques
US10199553B1 (en) 2015-11-05 2019-02-05 Massachusetts Institute Of Technology Shielded through via structures and methods for fabricating shielded through via structures
US10242968B2 (en) 2015-11-05 2019-03-26 Massachusetts Institute Of Technology Interconnect structure and semiconductor structures for assembly of cryogenic electronic packages
US10381541B2 (en) 2016-10-11 2019-08-13 Massachusetts Institute Of Technology Cryogenic electronic packages and methods for fabricating cryogenic electronic packages
US10535597B2 (en) * 2017-01-13 2020-01-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US11121301B1 (en) 2017-06-19 2021-09-14 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafers and their methods of manufacture
WO2019004991A1 (en) * 2017-06-25 2019-01-03 Intel Corporation ASSEMBLIES OF QUANTUM CALCULATORS
US11041211B2 (en) 2018-02-22 2021-06-22 Xilinx, Inc. Power distribution for active-on-active die stack with reduced resistance
CN112242386B (zh) * 2019-07-16 2024-07-05 江苏长电科技股份有限公司 Sip封装结构
US11270977B2 (en) 2019-11-08 2022-03-08 Xilinx, Inc. Power delivery network for active-on-active stacked integrated circuits
KR20220127624A (ko) 2021-03-11 2022-09-20 에스케이하이닉스 주식회사 이미지 센싱 장치
CN115602684B (zh) * 2022-08-12 2024-07-05 东科半导体(安徽)股份有限公司 集成结构的制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050101116A1 (en) * 2003-11-10 2005-05-12 Shih-Hsien Tseng Integrated circuit device and the manufacturing method thereof
US20080073756A1 (en) * 2006-09-22 2008-03-27 Infineon Technologies Ag Module with a shielding and/or heat dissipating element
US20080079115A1 (en) * 2006-09-29 2008-04-03 Freescale Semiconductor, Inc. Electronic device including an inductor and a process of forming the same
US20100164076A1 (en) * 2008-12-26 2010-07-01 Jun-Ho Lee Stacked semiconductor package
US20100244223A1 (en) * 2009-03-25 2010-09-30 Cho Namju Integrated circuit packaging system with an integral-interposer-structure and method of manufacture thereof

Family Cites Families (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6002168A (en) 1997-11-25 1999-12-14 Tessera, Inc. Microelectronic component with rigid interposer
KR100282025B1 (ko) * 1998-11-27 2001-02-15 안달 무선통신용 다층 세라믹 블록
JP2001203318A (ja) 1999-12-17 2001-07-27 Texas Instr Inc <Ti> 複数のフリップチップを備えた半導体アセンブリ
JP3597754B2 (ja) 2000-04-24 2004-12-08 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
CN1901177B (zh) 2000-09-25 2010-05-12 揖斐电株式会社 半导体元件及其制造方法、多层印刷布线板及其制造方法
US6709898B1 (en) 2000-10-04 2004-03-23 Intel Corporation Die-in-heat spreader microelectronic package
US6525407B1 (en) 2001-06-29 2003-02-25 Novellus Systems, Inc. Integrated circuit package
JP4595265B2 (ja) 2001-08-13 2010-12-08 日本テキサス・インスツルメンツ株式会社 半導体装置の製造方法
JP2004079701A (ja) 2002-08-14 2004-03-11 Sony Corp 半導体装置及びその製造方法
TWI278048B (en) 2003-11-10 2007-04-01 Casio Computer Co Ltd Semiconductor device and its manufacturing method
TWI245388B (en) 2005-01-06 2005-12-11 Phoenix Prec Technology Corp Three dimensional package structure of semiconductor chip embedded in substrate and method for fabricating the same
TWI269423B (en) 2005-02-02 2006-12-21 Phoenix Prec Technology Corp Substrate assembly with direct electrical connection as a semiconductor package
TWI264094B (en) 2005-02-22 2006-10-11 Phoenix Prec Technology Corp Package structure with chip embedded in substrate
US7326592B2 (en) 2005-04-04 2008-02-05 Infineon Technologies Ag Stacked die package
US7208345B2 (en) 2005-05-11 2007-04-24 Infineon Technologies Ag Method of manufacturing a semiconductor device comprising stacked chips and a corresponding semiconductor device
US7585702B1 (en) 2005-11-08 2009-09-08 Altera Corporation Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate
US7981726B2 (en) 2005-12-12 2011-07-19 Intel Corporation Copper plating connection for multi-die stack in substrate package
US7390700B2 (en) 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
US7714453B2 (en) 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
US8581381B2 (en) 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
DE102006032251A1 (de) 2006-07-12 2008-01-17 Infineon Technologies Ag Verfahren zum Herstellen von Chip-Packages sowie derartig hergestelltes Chip-Package
US7473577B2 (en) 2006-08-11 2009-01-06 International Business Machines Corporation Integrated chip carrier with compliant interconnect
KR100840788B1 (ko) 2006-12-05 2008-06-23 삼성전자주식회사 칩 적층 패키지 및 그 제조 방법
US20080157322A1 (en) 2006-12-27 2008-07-03 Jia Miao Tang Double side stacked die package
JP4926692B2 (ja) 2006-12-27 2012-05-09 新光電気工業株式会社 配線基板及びその製造方法と半導体装置
DE102007019552B4 (de) 2007-04-25 2009-12-17 Infineon Technologies Ag Verfahren zur Herstellung eines Substrats mit Durchführung sowie Substrat und Halbleitermodul mit Durchführung
KR100923562B1 (ko) 2007-05-08 2009-10-27 삼성전자주식회사 반도체 패키지 및 그 형성방법
KR100865125B1 (ko) 2007-06-12 2008-10-24 삼성전기주식회사 반도체 패키지 및 그 제조방법
KR101458538B1 (ko) 2007-07-27 2014-11-07 테세라, 인코포레이티드 적층형 마이크로 전자 유닛, 및 이의 제조방법
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
KR101348748B1 (ko) 2007-08-24 2014-01-08 삼성전자주식회사 재배선 기판을 이용한 반도체 패키지 제조방법
US7834464B2 (en) 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
US7618849B2 (en) 2007-10-22 2009-11-17 Broadcom Corporation Integrated circuit package with etched leadframe for package-on-package interconnects
US8030136B2 (en) 2008-05-15 2011-10-04 Stats Chippac, Ltd. Semiconductor device and method of conforming conductive vias between insulating layers in saw streets
US8350377B2 (en) 2008-09-25 2013-01-08 Wen-Kun Yang Semiconductor device package structure and method for the same
US20100133534A1 (en) 2008-12-03 2010-06-03 Byung Tai Do Integrated circuit packaging system with interposer and flip chip and method of manufacture thereof
US8008125B2 (en) 2009-03-06 2011-08-30 General Electric Company System and method for stacked die embedded chip build-up
US8263434B2 (en) 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
US8344512B2 (en) * 2009-08-20 2013-01-01 International Business Machines Corporation Three-dimensional silicon interposer for low voltage low power systems
KR101099577B1 (ko) * 2009-09-18 2011-12-28 앰코 테크놀로지 코리아 주식회사 전자파 차폐 및 열방출 수단을 갖는 반도체 패키지
US20110241185A1 (en) * 2010-04-05 2011-10-06 International Business Machines Corporation Signal shielding through-substrate vias for 3d integration
US8455995B2 (en) 2010-04-16 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. TSVs with different sizes in interposers for bonding dies
KR101680082B1 (ko) 2010-05-07 2016-11-29 삼성전자 주식회사 웨이퍼 레벨 패키지 및 웨이퍼 레벨 패키지의 형성방법
US8674513B2 (en) 2010-05-13 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for substrate
US8372666B2 (en) 2010-07-06 2013-02-12 Intel Corporation Misalignment correction for embedded microelectronic die applications
US9007273B2 (en) * 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
TWI416679B (zh) 2010-12-06 2013-11-21 Ind Tech Res Inst 半導體結構及其製造方法
US8299371B2 (en) 2010-12-20 2012-10-30 Endicott Interconnect Technologies, Inc. Circuitized substrate with dielectric interposer assembly and method
US8617987B2 (en) 2010-12-30 2013-12-31 Stmicroelectronics Pte Ltd. Through hole via filling using electroless plating
US9064781B2 (en) 2011-03-03 2015-06-23 Broadcom Corporation Package 3D interconnection and method of making same
US8508045B2 (en) 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
US8779562B2 (en) * 2011-03-24 2014-07-15 Stats Chippac Ltd. Integrated circuit packaging system with interposer shield and method of manufacture thereof
TWI506738B (zh) 2011-06-09 2015-11-01 Unimicron Technology Corp 封裝結構及其製法
US20120319293A1 (en) 2011-06-17 2012-12-20 Bok Eng Cheah Microelectronic device, stacked die package and computing system containing same, method of manufacturing a multi-channel communication pathway in same, and method of enabling electrical communication between components of a stacked-die package
US20130000968A1 (en) 2011-06-30 2013-01-03 Broadcom Corporation 1-Layer Interposer Substrate With Through-Substrate Posts
US8587123B2 (en) 2011-09-27 2013-11-19 Broadcom Corporation Multi-chip and multi-substrate reconstitution based packaging
US8659126B2 (en) * 2011-12-07 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit ground shielding structure
US8922013B2 (en) 2011-11-08 2014-12-30 Stmicroelectronics Pte Ltd. Through via package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050101116A1 (en) * 2003-11-10 2005-05-12 Shih-Hsien Tseng Integrated circuit device and the manufacturing method thereof
US20080073756A1 (en) * 2006-09-22 2008-03-27 Infineon Technologies Ag Module with a shielding and/or heat dissipating element
US20080079115A1 (en) * 2006-09-29 2008-04-03 Freescale Semiconductor, Inc. Electronic device including an inductor and a process of forming the same
US20100164076A1 (en) * 2008-12-26 2010-07-01 Jun-Ho Lee Stacked semiconductor package
US20100244223A1 (en) * 2009-03-25 2010-09-30 Cho Namju Integrated circuit packaging system with an integral-interposer-structure and method of manufacture thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106356350A (zh) * 2016-10-11 2017-01-25 广东顺德中山大学卡内基梅隆大学国际联合研究院 一种基于硅通孔互连的系统级封装的电磁耦合抑制方法
CN106356350B (zh) * 2016-10-11 2019-04-05 广东顺德中山大学卡内基梅隆大学国际联合研究院 一种基于硅通孔互连的系统级封装的电磁耦合抑制方法
CN112786530A (zh) * 2019-11-01 2021-05-11 美光科技公司 封装焊料tsv插入互连
US11587912B2 (en) 2019-11-01 2023-02-21 Micron Technology, Inc. High density pillar interconnect conversion with stack to substrate connection
US11631644B2 (en) 2019-11-01 2023-04-18 Micron Technology, Inc. High density pillar interconnect conversion with stack to substrate connection
US11973062B2 (en) 2019-11-01 2024-04-30 Micron Technology, Inc. High density pillar interconnect conversion with stack to substrate connection

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US20130221499A1 (en) 2013-08-29
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