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CN102569251B - 三维封装用金属间化合物填充的垂直通孔互连结构及制备方法 - Google Patents

三维封装用金属间化合物填充的垂直通孔互连结构及制备方法 Download PDF

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CN102569251B
CN102569251B CN201210041014.9A CN201210041014A CN102569251B CN 102569251 B CN102569251 B CN 102569251B CN 201210041014 A CN201210041014 A CN 201210041014A CN 102569251 B CN102569251 B CN 102569251B
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National Center for Advanced Packaging Co Ltd
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Abstract

本发明涉及一种三维封装用金属间化合物填充的垂直通孔互连结构及制备方法,其包括衬底,所述衬底内设有至少一个垂直贯通穿透衬底的通孔;所述通孔的内壁生长有绝缘层,并在所述生长绝缘层的通孔内填充有金属间化合物层,所述金属间化合物层与绝缘层间设有粘附层。本发明衬底内设有至少一个垂直贯通的通孔,通孔的内壁上生长有绝缘层,并在通孔内填充金属间化合物层,金属间化合物层与绝缘层间具有粘附层;通过金属间化合物层能够完成三维堆叠中所需的电连接,整个形成制作过程方便,降低了工艺复杂度及制作成本;从而能够在集成电路上制作垂直互连结构,也能够在无源基板上制作转接板,提高合格率,安全可靠。

Description

三维封装用金属间化合物填充的垂直通孔互连结构及制备方法
技术领域
本发明涉及一种垂直互连结构及制备方法,尤其是一种三维封装用金属间化合物填充的垂直通孔互连结构及制备方法,属于微电子封装三维集成技术领域。
背景技术
系统级封装(SiP)是微电子关键技术之一,满足了电子器件的高频高速、多功能、高性能、小体积和高可靠性的要求,是电子技术发展的方向。随着集成电路特征尺寸达到纳米级,晶体管向更高密度、更高的时钟频率发展,封装也向更高密度的方向发展,集成电路产品也从二维向三维发展。
硅通孔(TSV)的三维集成技术是实现3D-SiP的关键技术之一,是具有极大影响的新核心技术,具有极其广阔的应用前景;因此受到各工业国家、重要企业和学术界的极大关注,现在已经并持续投入大量资源进行研发。硅通孔技术具有很多技术挑战,特别是其工艺制程复杂,包括硅孔刻蚀、绝缘层/阻挡层/种子层沉积、通孔填充、化学机械研磨、晶圆键合、拆键合、晶圆减薄、金属再布线制作、凸点制备等。
TSV技术在应用方面存在的主要问题仍是工艺复杂,成本高。对于硅通孔的填充材料和方式,大致有如下几种:(1)、电镀填孔;(2)、化学气象沉积(CVD);(3)、液态钎料填充;(4)、导电胶填充。利用电镀填孔,主要是以铜电镀为主,其优点是铜具有良好的导电性,缺点是电镀需要良好的种子层制作,电镀时间较长,电镀工艺复杂,成本高;而且对于孔径小于5微米的孔,电镀填孔难以实现。化学气相沉积的主要材料是钨,可以实现小孔径通孔的填充,主要问题是工艺复杂,填充时间长,成本高,导电性稍差。钎料填充,是利用低熔点钎料在液态下填充微孔,具有快速,低成本等优点。(参考文献Ko Y.-K.,Fujii H.T.,Sato Y.S.,Lee C.-W.,and Yoo S.Microelectron Eng 2012;89:62-64.)但缺点是钎料导电性较差,与硅材料的CTE(Coefficient of thermal expansion,热膨胀系数)相差较大,带来应力问题,而且钎料熔点低,在后续工艺制程过程中会带来很多问题。利用导电胶填充,也可以简化填充工艺,但导电性很差,难以填充直径较小的孔。
发明内容
本发明的目的是克服现有技术中存在的不足,提供一种三维封装用金属间化合物填充的垂直通孔互连结构及制备方法,其能有效降低制作成本,简化工艺步骤,提高合格率,安全可靠。
按照本发明提供的技术方案,所述三维封装用金属间化合物填充的垂直通孔互连结构,包括衬底,所述衬底内设有至少一个垂直贯通穿透衬底的通孔;所述通孔内由垂直方向连续的金属间化合物填充,所述金属间化合物层与衬底间设有粘附层。
所述衬底与粘附层包括绝缘层,粘附层通过绝缘层粘附于通孔的内壁上。
所述金属间化合物层与粘附层间还包括残余金属层,金属间化合物层通过残余金属层与粘附层相连。
所述金属间化合物层通过填充在通孔内的高温金属层与低熔点钎料填充体热扩散形成。
所述高温金属层为Cu、Ni、Ag、Pd、Au或Fe中材料的一种或几种;低熔点钎料填充体为Sn、In、SnAg、SnIn、SnBi、SnPb、SnAgCu、InAg、InSn中材料的一种或几种。
所述金属间化合物层为Cu-Sn、Ni-Sn、Cn-In、Ni-In、Ag-Sn、Au-Sn、Ag-In、Au-In等中的一种或几种。
所述金属间化合物层内包括高温金属相,高温金属相的熔点高于300度。
所述绝缘层的材料为SiO2,SixN1-x中的一种或几种。
一种三维封装用金属间化合物填充的垂直通孔互连结构制备方法,所述垂直互连结构制备方法包括如下步骤:
a、提供衬底,并在衬底内形成所需垂直贯通穿透衬底的通孔;
b、在上述衬底的表面上淀积粘附层,所述粘附层覆盖于衬底的表面并覆盖于通孔的内壁表面;
c、在上述衬底的表面设置与衬底绝缘的高温金属层,所述高温金属层覆盖衬底的表面并覆盖于通孔内对应粘附层的表面;
d、在上述通孔内填充低熔点钎料,以在通孔内形成低熔点钎料填充体;
e、对上述形成低熔点钎料填充体的衬底表面平整化,抛光衬底对应的表面,以使得通孔内的低熔点钎料填充体与抛光后衬底的表面平齐;
f、在所需的温度下,对低熔点钎料填充体及高温金属层进行热扩散处理,直至低熔点钎料填充体全部融化后与高温金属层形成金属间化合物层。
所述步骤d中,通过将衬底插入熔融的低熔点钎料熔池或在真空环境下灌封熔融的低熔点钎料,以在通孔内形成所需的低熔点钎料填充体。
所述衬底的材料包括硅、砷化镓,氮化镓或玻璃。
所述步骤f中,通孔内包括残余金属层或高温金属相,
所述高温金属相的熔点高于300度,高温金属相包括Ag3Sn、Cu6Sn5、富Pb相或富Bi相。
所述步骤b中,衬底为导体或半导体衬底时,在衬底表面淀积绝缘层,所述绝缘层覆盖于衬底的表面并覆盖通孔的内壁表面;当衬底及通孔内形成绝缘层后,粘附层覆盖衬底及通孔内绝缘层的表面。
所述绝缘层的材料为SiO2,SixN1-x中的一种或几种。
所述高温金属层为Cu、Ni、Ag、Pd、Au或Fe中材料的一种或几种。
低熔点钎料填充体为Sn、In、SnAg、SnIn、SnBi、SnPb、SnAgCu、InAg、InSn中材料的一种或几种。
所述粘附层的材料为Ti、TiN或Ta。
本发明的优点:衬底内设有至少一个垂直贯通的通孔,通孔的内壁上生长有绝缘层,并在通孔内填充金属间化合物层,金属间化合物层与绝缘层间具有粘附层;通过金属间化合物层能够完成三维堆叠中所需的电连接,整个形成制作过程方便,降低了工艺复杂度及制作成本;从而能够在集成电路上制作垂直互连结构,也能够在无源基板上制作转接板,提高合格率,安全可靠。
附图说明
图1为本发明的结构示意图。
图2为本发明具有残留金属层与残留金属相的结构示意图。
图3为本发明制作转接板后的使用状态图。
图4~图10为本发明的具体工艺步骤剖视图,其中:
图4为在通孔内生长得到绝缘层后的剖视图。
图5为在通孔内淀积得到粘附层后的剖视图。
图6为在通孔内得到高温金属层后的剖视图。
图7为在通孔内填充得到低熔点钎料填充体后的剖视图。
图8为平整抛光后的结构示意图。
图9为高温金属与低熔点钎料填充体热扩散后形成金属间化合物后的剖视图。
图10为高温金属与低熔点钎料填充体热扩散后具有残余金属层后的剖视图。
附图标记说明:10-衬底、12-通孔、20-绝缘层、24-高温金属层、26-低熔点钎料填充体、30-粘附层、32-残余金属层、36-高温金属相及40-金属间化合物层。
具体实施方式
下面结合具体附图和实施例对本发明作进一步说明。
如图1、图2、图9和图10所示:本发明中的垂直互连结构包括衬底10,所述衬底10的材料为硅、砷化镓,氮化镓或玻璃,衬底10内设有至少一个垂直贯通穿透衬底10的通孔12。为了实现互连封装,当衬底10为导体或半导体材料时,通孔12的内壁上生长有绝缘层20,所述绝缘层20为SiO2,SixN1-x中的一种或几种。在内壁生长有绝缘层20的通孔12内填充有金属间化合物层40,所述金属间化合物层40与绝缘层20间设有粘附层30,通过粘附层30能够使得金属间化合物层40在形成过程中能有效填充在通孔12内,金属间化合物层40填充满整个通孔12。粘附层30的材料为Ti、TiN或Ta。当衬底10为绝缘材料时,通孔12内可以不设置绝缘层20,在通孔12内直接设置粘附层30。
金属间化合物层40为通孔12内的高温金属层24与低熔点钎料填充体26在经过所需的热扩散后形成;形成金属间化合物层40的过程中,由于高温金属层24的厚度等不同,在粘附层30与金属间化合物层40间还残留有残余金属层32;由于低熔点钎料填充体26的设置不同,在金属间化合物层40内可能有高温金属相36;例如高温金属层24为Cu,低熔点钎料填充体26采用SnBi,当Sn与Cu扩散反应,Sn耗尽后富Bi相会剩余下来,即在金属间化合物层40内得到富Bi相。所述高温金属层24为Cu、Ni、Ag、Pd、Au或Fe中的一种或几种;低熔点钎料填充体26为Sn、In、SnAg、SnIn、SnBi、SnPb、SnAgCu、InAg、InSn中的一种或几种。所述金属间化合物层40为Cu-Sn、Ni-Sn、Cn-In、Ni-In、Ag-Sn、Au-Sn、Ag-In、Au-In中的一种或几种。所述高温金属相36包括Ag3Sn、Cu6Sn5、富Pb相或富Bi相。
如图4~图10所示:上述垂直的互连结构可以通过下述具体工艺步骤实现,具体地为:
a、提供衬底10,并在衬底10内形成所需垂直贯通穿透衬底10的通孔12;
本发明实施例中,衬底10选择8寸硅晶圆,并将所述硅晶圆的厚度减薄至300微米;通过常规工艺在硅晶圆内形成通孔12,所述通孔12的孔径一般为30微米;
b、在上述衬底10的表面上淀积粘附层30,所述粘附层30覆盖于衬底10的表面并覆盖于通孔12的内壁表面;
如图4所示衬底10为导体或半导体衬底时,在衬底10表面淀积绝缘层20,所述绝缘层20覆盖于衬底10的表面并覆盖通孔12的内壁表面;当衬底10及通孔12内形成绝缘层20后,粘附层30覆盖衬底10及通孔12内绝缘层20的表面;在硅晶圆的表面热氧化生长氧化层,得到位于衬底10表面及通孔12内壁上的绝缘层20;
如图5所示:本发明实施例中,通过在衬底10表面上淀积Ti,所述Ti层的厚度在几十到几百微米之间,可以根据需要进行设定,以此作为粘附层30和阻挡层;淀积Ti的过程中,会同时覆盖通孔12内对应绝缘层20;
c、在上述衬底10的表面设置与衬底10绝缘隔离的高温金属层24,所述高温金属层24覆盖衬底10的表面并覆盖于通孔12内对应粘附层30的表面;
如图6所示:所述高温金属层24的形成过程可以先在上述粘附层30上沉积金属,然后在电镀或化学镀至所需的厚度;本发明具体实施时,高温金属层24采用Cu,先通过物理气相沉积Cu,然后在电镀至6微米;当通孔12内有绝缘层20时,高温金属层24通过绝缘层24与衬底10相绝缘隔离;
d、在上述通孔12内填充低熔点钎料,以在通孔12内形成低熔点钎料填充体26;
如图7所示:在通孔12内填充低熔点钎料时,可以将衬底10插入熔融的低熔点钎料熔池内,或者在真空环境下灌封熔融低熔点钎料;由于表面张力的作用,在短时间内,就可以完成填充;本发明的具体实施中,低熔点钎料为Sn,填充过程中的温度高于Sn的熔点,比如可以在260度;
e、对上述形成低熔点钎料填充体26的衬底10表面平整化,抛光衬底10对应的表面,以使得通孔12内的低熔点钎料填充体26与抛光后衬底10的表面平齐;
如图8所示:在通孔12内通过填充低熔点钎料形成低熔点钎料填充体26后,低熔点钎料填充体26的两端会形成凸点,所述凸点的高度高于衬底10的表面;因此通过平整化抛光操作将凸点及衬底10表面的一些材料层去除;所述平整化可以采用机械化学抛光(CMP)或其他平整化工艺;
f、在所需的温度下,对低熔点钎料填充体26及高温金属层24进行热扩散处理,直至低熔点钎料填充体26全部融化后与高温金属层24形成金属间化合物层40。
为了形成所需的金属间化合物层40,需要在所需的温度下进行热扩散处理;热扩散处理的时间以能够使低熔点钎料填充体26扩散融化完为止;当采用那个本发明中前述的材料时,金属间化合物层40为Cu6Sn5、Cu3Sn或Cu6Sn5、Cu3Sn两者的混合。当高温金属层24超过一定厚度,在热扩散后就会有残余,如图2和图10中的残余金属层32。
图3为当形成本发明的垂直互连结构后制作转接板的结构示意图。在转接板的正面具有两层布线以及微凸点,在背面具有一层布线及微凸点,通过转接板能够完成集成电路的封装。
本发明衬底10内设有至少一个垂直贯通的通孔12,在通孔12内由垂直方向上连续的金属间化合物层40填充,金属间化合物层40与衬底10间具有粘附层30;通过金属间化合物层40能够完成三维堆叠中所需的电连接,整个形成制作过程方便,降低了工艺复杂度及制作成本;从而能够在集成电路上制作垂直互连结构,也能够在无源基板上制作转接板,提高合格率,安全可靠。
以上所述仅为本发明的具体实施例,并不用以限制本发明,本实施例中所用材料和工艺条件仅限于本实施例,凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。

Claims (14)

1.一种三维封装用金属间化合物填充的垂直通孔互连结构,包括衬底(10),所述衬底(10)内设有至少一个垂直贯通穿透衬底(10)的通孔(12);其特征是:所述通孔(12)内由垂直方向连续的金属间化合物(40)填充,所述金属间化合物层(40)与衬底(10)间设有粘附层(30);
所述金属间化合物层(40)通过填充在通孔(12)内的高温金属层(24)与低熔点钎料填充体(26)热扩散形成;
所述高温金属层(24)为Cu、Ni、Ag、Pd、Au或Fe中材料的一种或几种;低熔点钎料填充体(26)为Sn、In、SnAg、SnIn、SnBi、SnPb、SnAgCu、InAg、InSn中材料的一种或几种。
2.根据权利要求1所述的三维封装用金属间化合物填充的垂直通孔互连结构,其特征是:所述衬底(10)与粘附层(30)包括绝缘层(20),粘附层(30)通过绝缘层(20)粘附于通孔(12)的内壁上。
3.根据权利要求1或2所述的三维封装用金属间化合物填充的垂直通孔互连结构,其特征是:所述金属间化合物层(40)与粘附层(30)间还包括残余金属层(32),金属间化合物层(40)通过残余金属层(32)与粘附层(30)相连。
4.根据权利要求1或2所述的三维封装用金属间化合物填充的垂直通孔互连结构,其特征是:所述金属间化合物层(40)为Cu-Sn、Ni-Sn、Cn-In、Ni-In、Ag-Sn、Au-Sn、Ag-In、Au-In等中的一种或几种。
5.根据权利要求1或2所述的三维封装用金属间化合物填充的垂直通孔互连结构,其特征是:所述金属间化合物层(40)内包括高温金属相(36),高温金属相(36)的熔点高于300度。
6.根据权利要求2所述的三维封装用金属间化合物填充的垂直通孔互连结构,其特征是:所述绝缘层(20)的材料为SiO2, SixN1-x中的一种或几种。
7.一种三维封装用金属间化合物填充的垂直通孔互连结构制备方法,其特征是,所述垂直互连结构制备方法包括如下步骤:
(a)、提供衬底(10),并在衬底(10)内形成所需垂直贯通穿透衬底(10)的通孔(12);
(b)、在上述衬底(10)的表面上淀积粘附层(30),所述粘附层(30)覆盖于衬底(10)的表面并覆盖于通孔(12)的内壁表面;
(c)、在上述衬底(10)的表面设置与衬底(10)绝缘的高温金属层(24),所述高温金属层(24)覆盖衬底(10)的表面并覆盖于通孔(12)内对应粘附层(30)的表面;
(d)、在上述通孔(12)内填充低熔点钎料,以在通孔(12)内形成低熔点钎料填充体(26);
(e)、对上述形成低熔点钎料填充体(26)的衬底(10)表面平整化,抛光衬底(10)对应的表面,以使得通孔(12)内的低熔点钎料填充体(26)与抛光后衬底(10)的表面平齐;
(f)、在所需的温度下,对低熔点钎料填充体(26)及高温金属层(24)进行热扩散处理,直至低熔点钎料填充体(26)全部融化后与高温金属层(24)形成金属间化合物层(40);
所述高温金属层(24)为Cu、Ni、Ag、Pd、Au或Fe中材料的一种或几种;
低熔点钎料填充体(26)为Sn、In、SnAg、SnIn、SnBi、SnPb、SnAgCu、InAg、InSn中材料的一种或几种。
8.根据权利要求7所述的三维封装用金属间化合物填充的垂直通孔互连结构制备方法,其特征是:所述步骤(d)中,通过将衬底(10)插入熔融的低熔点钎料熔池或在真空环境下灌封熔融的低熔点钎料,以在通孔(12)内形成所需的低熔点钎料填充体(26)。
9.根据权利要求7所述的三维封装用金属间化合物填充的垂直通孔互连结构制备方法,其特征是:所述衬底(10)的材料包括硅、砷化镓,氮化镓或玻璃。
10.根据权利要求8所述的三维封装用金属间化合物填充的垂直通孔互连结构制备方法,其特征是:所述步骤(f)中,通孔(12)内包括残余金属层(32)或高温金属相(36)。
11.根据权利要求10所述的三维封装用金属间化合物填充的垂直通孔互连结构制备方法,其特征是:所述高温金属相(36)的熔点高于300度,高温金属相(36)包括Ag3Sn、Cu6Sn5、富Pb相或富Bi相。
12.根据权利要求7所述的三维封装用金属间化合物填充的垂直通孔互连结构制备方法,其特征是:所述步骤(b)中,衬底(10)为导体或半导体衬底时,在衬底(10)表面淀积绝缘层(20),所述绝缘层(20)覆盖于衬底(10)的表面并覆盖通孔(12)的内壁表面;当衬底(10)及通孔(12)内形成绝缘层(20)后,粘附层(30)覆盖衬底(10)及通孔(12)内绝缘层(20)的表面。
13.根据权利要求12所述的三维封装用金属间化合物填充的垂直通孔互连结构制备方法,其特征是:所述绝缘层(20)的材料为SiO2, SixN1-x中的一种或几种。
14.根据权利要求7所述的三维封装用金属间化合物填充的垂直通孔互连结构制备方法,其特征是:所述粘附层(30)的材料为Ti、TiN或Ta。
CN201210041014.9A 2012-02-22 2012-02-22 三维封装用金属间化合物填充的垂直通孔互连结构及制备方法 Active CN102569251B (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465504A (zh) * 2014-12-10 2015-03-25 华进半导体封装先导技术研发中心有限公司 金属间合物填充材料的转接板的制造工艺

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102569251B (zh) * 2012-02-22 2014-07-02 华进半导体封装先导技术研发中心有限公司 三维封装用金属间化合物填充的垂直通孔互连结构及制备方法
CN102925024B (zh) * 2012-11-15 2015-07-08 中国科学院深圳先进技术研究院 绝缘膜用组合物及三维垂直孔的孔壁上形成绝缘膜的方法
CN104101967B (zh) * 2014-07-31 2016-02-24 华进半导体封装先导技术研发中心有限公司 一种光通信装置及止动孔的形成方法
JP6539992B2 (ja) * 2014-11-14 2019-07-10 凸版印刷株式会社 配線回路基板、半導体装置、配線回路基板の製造方法、半導体装置の製造方法
CN104409363B (zh) * 2014-11-19 2017-12-01 清华大学 转接板及其制作方法、封装结构
CN107004599B (zh) * 2014-12-17 2020-02-18 三井化学株式会社 基板中间体、贯通通孔电极基板及贯通通孔电极形成方法
CN104701249B (zh) * 2015-02-09 2017-08-22 大连理工大学 一种金属间化合物填充的三维封装垂直通孔及其制备方法
CN104701283B (zh) * 2015-02-09 2017-12-19 大连理工大学 金属间化合物填充三维封装垂直通孔及其制备方法
CN104674335B (zh) * 2015-02-09 2018-01-16 大连理工大学 金属间化合物薄膜的制备方法
CN105118815B (zh) * 2015-08-13 2017-09-29 上海航天电子通讯设备研究所 一种基于铝基板的三维封装用垂直互连结构及其制备方法
CN106449573A (zh) * 2016-11-16 2017-02-22 宁波麦思电子科技有限公司 一种具有垂直通孔互连的金属材质的转接板及其制作方法
CN107293484A (zh) * 2017-07-11 2017-10-24 华进半导体封装先导技术研发中心有限公司 一种转接板制造方法
CN107359137A (zh) * 2017-07-11 2017-11-17 华进半导体封装先导技术研发中心有限公司 一种用于制造转接板的方法
WO2021158241A1 (en) * 2020-02-07 2021-08-12 Innovent Technologies, Llc Method and apparatus for the manufacture of silicon via substrate
CN116391251A (zh) * 2020-10-30 2023-07-04 华为技术有限公司 膜层穿孔的形成方法、半导体器件及芯片
CN115319114B (zh) * 2022-08-18 2023-12-19 福州大学 一种使用选区激光熔化工艺制备SnBi-xFe低熔点复合材料的方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101217118A (zh) * 2007-01-05 2008-07-09 国际商业机器公司 用于制造具有导电通孔的硅载体的方法及其制造的半导体
CN101853804A (zh) * 2009-04-03 2010-10-06 南茂科技股份有限公司 半导体装置的制造方法
CN102318041A (zh) * 2009-02-17 2012-01-11 埃托特克德国有限公司 用于电沉积铜的工艺,在穿硅通孔(tsv)中的芯片间、芯片到晶片间和晶片间的互连

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5693564A (en) * 1994-12-22 1997-12-02 Intel Corporation Conductor fill reflow with intermetallic compound wetting layer for semiconductor fabrication
JP3634984B2 (ja) * 1999-07-30 2005-03-30 京セラ株式会社 配線基板
JP3990347B2 (ja) * 2003-12-04 2007-10-10 ローム株式会社 半導体チップおよびその製造方法、ならびに半導体装置
KR20100021856A (ko) * 2008-08-18 2010-02-26 삼성전자주식회사 관통 전극을 갖는 반도체장치의 형성방법 및 관련된 장치
US8344513B2 (en) * 2009-03-23 2013-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier for through-silicon via
JP5250582B2 (ja) * 2010-04-22 2013-07-31 有限会社 ナプラ 充填用基材及びそれを用いた充填方法
JP6118015B2 (ja) * 2011-05-12 2017-04-19 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation シリコンボードにおけるシリコン貫通配線(tsv)の形成
CN102569251B (zh) * 2012-02-22 2014-07-02 华进半导体封装先导技术研发中心有限公司 三维封装用金属间化合物填充的垂直通孔互连结构及制备方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101217118A (zh) * 2007-01-05 2008-07-09 国际商业机器公司 用于制造具有导电通孔的硅载体的方法及其制造的半导体
CN102318041A (zh) * 2009-02-17 2012-01-11 埃托特克德国有限公司 用于电沉积铜的工艺,在穿硅通孔(tsv)中的芯片间、芯片到晶片间和晶片间的互连
CN101853804A (zh) * 2009-04-03 2010-10-06 南茂科技股份有限公司 半导体装置的制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465504A (zh) * 2014-12-10 2015-03-25 华进半导体封装先导技术研发中心有限公司 金属间合物填充材料的转接板的制造工艺

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