Nothing Special   »   [go: up one dir, main page]

CN101752273A - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

Info

Publication number
CN101752273A
CN101752273A CN200910225178A CN200910225178A CN101752273A CN 101752273 A CN101752273 A CN 101752273A CN 200910225178 A CN200910225178 A CN 200910225178A CN 200910225178 A CN200910225178 A CN 200910225178A CN 101752273 A CN101752273 A CN 101752273A
Authority
CN
China
Prior art keywords
mentioned
supporting bracket
semiconductor device
manufacture method
protection film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN200910225178A
Other languages
English (en)
Other versions
CN101752273B (zh
Inventor
小六泰辅
冈田修
桑原治
盐田纯司
藤井信充
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Publication of CN101752273A publication Critical patent/CN101752273A/zh
Application granted granted Critical
Publication of CN101752273B publication Critical patent/CN101752273B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)

Abstract

本发明涉及用树脂保护膜覆盖着半导体衬底的底面及侧面的半导体器件的制造方法。首先，在与划片道及其两侧对应的部分的半导体晶片及密封膜等上形成槽。在此状态下，通过形成槽，半导体晶片被分离为各个硅衬底。接着，在包含槽内在内的各硅衬底的底面形成树脂保护膜。在此情况下，半导体晶片被分离为各个硅衬底，但是由于在柱状电极及密封膜的上表面间隔着粘接剂层粘贴了支撑板，所以能够使得在形成树脂保护膜时，包含分离的各个硅衬底的整体不易翘曲。

Description

半导体器件的制造方法
技术领域
本发明涉及用树脂保护膜覆盖着半导体衬底的底面及侧面的半导体器件的制造方法。
背景技术
在(日本)特许第4103896号公报中，已知有所谓的CSP(Chip SizePackage，芯片尺寸封装)。在该半导体器件中，在设在半导体衬底上的绝缘膜的上表面设有多条布线，在布线的连接焊盘部上表面设有柱状电极，在包含布线在内的绝缘膜的上表面设有密封膜，使得该上表面与柱状电极的上表面为同一平面，在柱状电极的上表面设有焊料球。在此情况下，为了使得半导体衬底的下表面及侧面不露出，而用树脂保护膜覆盖着半导体衬底的下表面及侧面。
然而，在(日本)特许第4103896号公报中，首先，准备下述构件：在晶片状态的半导体衬底(以下称为半导体晶片)的上表面侧，形成了绝缘膜、布线、柱状电极及密封膜。接着，使半导体晶片的上下反转。接着，在半导体晶片的底面侧(与形成了密封膜等的面相反的面侧)的各半导体器件形成区域间通过半切(half cut)而形成规定宽度的槽，该槽到达密封膜的中间。在此状态下，半导体晶片通过形成槽而被分离为各个半导体晶片。
接着，在包含槽内在内的各半导体衬底的底面形成树脂保护膜。接着，使包含各半导体衬底的整体的上下反转。接着，在柱状电极的上表面形成焊料球。接着，在槽的宽度方向中央部切断密封膜及树脂保护膜。这样，得到了用树脂保护膜覆盖着半导体衬底的底面及侧面的构造的半导体器件。
然而，在(日本)特许第4103896号公报中，只是在上下反转了的半导体晶片的底面侧通过半切而形成槽直至密封膜的途中后，在包含槽内在内的各半导体衬底的底面形成了树脂保护膜，即，只是在通过形成槽而将半导体晶片分离为各个半导体衬底的状态下形成了树脂保护膜，所以有下述问题：半切步骤及以后的步骤中的强度降低，包含各半导体衬底的整体会比较大地翘曲，所以难以维持质量，而且各步骤的控制变得困难。
发明内容
因此，本发明的目的在于提供一种半导体器件的制造方法，能够使得在形成保护半导体衬底的树脂保护膜时，包含各半导体衬底的整体不易翘曲。
根据本发明的第1方面，提供一种半导体器件的制造方法，包含以下步骤：准备下述构件：在一面上形成了集成电路的半导体晶片的该一面上形成了绝缘膜，在上述绝缘膜上形成了电极用连接焊盘部并连接在上述集成电路上，在上述电极用连接焊盘部上形成了外部连接用凸起电极，在上述外部连接用凸起电极的周围形成了密封膜；在上述外部连接用凸起电极及上述密封膜上，间隔着粘接剂层粘贴具有多个小孔的支撑板；在与划片道及其两侧对应的部分的上述半导体晶片的底面侧，形成到达上述密封膜的厚度的中间位置的槽；在包含上述槽内的上述半导体晶片的底面，形成树脂保护膜；从上述支撑板的小孔浸透剥离液来溶解并除去上述粘接剂层，由此从上述外部连接用凸起电极及上述密封膜上分离上述支撑板；以比上述槽的宽度小的宽度，切断上述密封膜及上述树脂保护膜；得到多个在从上述半导体衬底的侧面到上述密封膜的中间位置的侧面及半导体衬底的底面形成了上述树脂保护膜的半导体器件。
根据该发明，在外部连接用凸起电极及密封膜上粘贴着支撑板的状态下，在包含槽内在内的半导体晶片(各半导体衬底)的底面形成了树脂保护膜，所以能够使得在形成保护半导体衬底的树脂保护膜时，包含各半导体衬底的整体不易翘曲。
附图说明
图1是通过本发明的制造方法制造出的半导体器件的一例的剖面图。
图2是在图1所示的半导体器件的制造方法的一例中、最初准备的构件的剖面图。
图3是上接图2的工序的剖面图。
图4是上接图3的工序的剖面图。
图5是上接图4的工序的剖面图。
图6是上接图5的工序的剖面图。
图7是上接图6的工序的剖面图。
图8是上接图7的工序的剖面图。
图9是上接图8的工序的剖面图。
图10是上接图9的工序的剖面图。
图11是上接图10的工序的剖面图。
图12是上接图11的工序的剖面图。
图13是上接图12的工序的剖面图。
图14是上接图13的工序的剖面图。
图15是上接图14的工序的剖面图。
具体实施方式
图1示出通过本发明的制造方法制造出的半导体器件的一例的剖面图。该半导体器件一般称为CSP，包括硅衬底(半导体衬底)1。在硅衬底1的上表面形成了构成规定功能的集成电路的元件，例如晶体管、二极管、电阻、电容等元件(未图示)，在该上表面周边部，设有连接在上述集成电路的各元件上的由铝类金属等构成的连接焊盘2。连接焊盘2只图示了2个，但是实际上在硅衬底1的上表面周边部排列了多个。
在除了连接焊盘2的中央部以外的硅衬底1的上表面设有由氧化硅等构成的钝化膜(绝缘膜)，连接焊盘2的中央部经由钝化膜3上所设的开口部4露出。在钝化膜3的上表面设有由聚酰亚胺类树脂等构成的保护膜(绝缘膜)5。在与钝化膜3的开口部4对应的部分的保护膜5上设有开口部6。
在保护膜5的上表面设有布线7。布线7为双层构造：基底金属层8，设在保护膜5的上表面，由铜等构成；和上部金属层9，设在基底金属层8的上表面，由铜等构成。布线7的一端部经由钝化膜3及保护膜5的开口部4、6连接在连接焊盘2上。在布线7的连接焊盘部(电极用连接焊盘部)上表面设有由铜构成的柱状电极(外部连接用凸起(bump)电极)10。
在硅衬底1的底面及硅衬底1、钝化膜3和保护膜5的侧面设有由环氧类树脂等构成的树脂保护膜11。在此情况下，硅衬底1、钝化膜3及保护膜5的侧面所设的树脂保护膜11的上部呈直线状凸出到比保护膜5的上表面更上侧。在此状态下，硅衬底1的底面及硅衬底1、钝化膜3和保护膜5的侧面由树脂保护膜11覆盖。
在包含布线7在内的保护膜5的上表面及其周围的树脂保护膜11的上表面设有由环氧类树脂等构成的密封膜12。柱状电极10被设得使得其上表面与密封膜12的上表面为同一平面或低几μm。在柱状电极10的上表面设有焊料球13。
接着，说明该半导体器件的制造方法的一例。首先，如图2所示，准备下述构件：在晶片状态的硅衬底(以下称为半导体晶片21)上形成了连接焊盘2、钝化膜3、保护膜5、由基底金属层8及上部金属层9构成的双层构造的布线7、柱状电极10、及密封膜12。这种半导体晶片21的制造方法是已知的，详细情况请参考例如(日本)特许第3955059号的图2～图7及说明书的相关部分。
在此情况下，半导体晶片21的厚度比图1所示的硅衬底1的厚度厚一定的程度。此外，包含柱状电极10的上表面在内的密封膜12的上表面是平坦的。这里，在图2中，标号22所示的区域是与划片道对应的区域。
准备了图2所示的构件之后，接着，如图3所示，在柱状电极10及密封膜12的上表面间隔着粘接剂层23粘贴支撑板24。在此情况下，作为粘接剂层23，最好是非水溶性的高分子化合物，尤其是从耐热性考虑，最好是丙烯酸类树脂，但是不限于此，也可以采用酚醛树脂、环氧树脂、酰胺树脂(amide resin)等。作为粘接剂层23的材料的一例，可以参考(日本)特开2005-191550号公报。支撑板24由比半导体晶片21稍大的圆形的、具有多个小孔(未图示)的玻璃板、金属板、陶瓷板等构成。支撑板24的厚度例如是0.7至1.0mm。小孔在支撑板24的整个面相隔均匀的间隔，是贯通厚度方向的贯通孔。
然后，首先，在柱状电极10及密封膜12的上表面通过旋涂法等来涂敷用于形成粘接剂层23的液状粘接剂。接着，进行预烘烤，使粘接剂层23中的溶剂挥发，使粘接剂层23固化、干燥。接着，在真空中一边加热，一边在粘接剂层23的上表面粘贴由具有多个小孔(未图示)的玻璃板等构成的支撑板24。在真空下粘贴由玻璃板等构成的支撑板24，是为了使空气不进入支撑板24和粘接剂层23之间。
接着，如图4所示，在支撑板24的上表面，粘贴用于覆盖多个小孔的第1保护带25。作为第1保护带25，可以采用在基材上附有丙烯酸类粘接剂的带。基材可以从聚乙烯等聚烯烃类、PET(聚对苯二甲酸乙二醇酯)、EVA(乙烯-醋酸乙烯共聚物)等中选择。但是，第1保护带25仅用于防止研磨半导体晶片21的底面的硅时使用的研磨水的浸入，所以不限于此。第1保护带25的作用将在后面说明。接着，上下反转图4所示的构件，而如图5所示，将半导体晶片21的底面(与形成了密封膜12等的面相反的面)向上。载置在工作台(未图示)上，真空吸附而固定。接着，如图6所示，用研磨砥石(未图示)适当研磨半导体晶片21的底面侧，使半导体晶片21的厚度适当变薄。此时，为了除去磨屑及冷却砥石，使用水。该研磨水混有硅的磨屑等，所以不干净。此外，磨屑一旦侵入小孔，则不易清洗，所以会污染剥离支撑板24时所用的剥离液，或者落在密封膜12的上表面。但是，在此情况下，在支撑板24的下表面粘贴着第1保护带25，所以研磨时所用的水不会侵入支撑板24的小孔。因此，磨屑不会进入支撑板24的小孔，堵塞小孔，所以可以重复使用支撑板24。接着，将第1保护带25从支撑板24的下表面剥离。其中，支撑板24也可以在使半导体晶片21的厚度适当变薄后粘贴。
接着，如图7所示，将支撑板24的下表面粘贴到划片带(dicing tape)26的上表面。关于划片，与用研磨砥石研磨半导体晶片21的底面侧的情况相比，带不易剥落。因此，划片带26的胶的厚度在第1保护带25的胶的厚度的1/10以下。结果，划片带26与第1保护带25相比较，粘着力弱，带的厚度也薄。接着，如图8所示，准备刀27。该刀27由圆盘状的砥石构成，其刀尖的剖面形状大致为コ字形(或者大致为U字形)，其厚度比划片道22的宽度厚一定程度。
然后，用该刀27，在与划片道22及其两侧对应的部分的半导体晶片21、钝化膜3、保护膜5及密封膜12上形成槽28。在此情况下，槽28的深度直至密封膜12的途中，例如为密封膜12的厚度的1/2以上，最好为1/3以上。在此状态下，通过形成槽28，半导体晶片21被分离为各个硅衬底1(分离为单个的硅衬底1)。接着，将支撑板24从划片带26的上表面剥离。其中，该工序也可以通过采用半切用的划片装置，不粘贴到划片带上来加工。
接着，如图9所示，在包含槽28内在内的各硅衬底1的底面侧，通过旋涂法、丝网印刷法等来涂敷由环氧类树脂等构成的热固性树脂，使其固化，来形成树脂保护膜11。固化温度为150～250℃，处理时间为1小时左右。在此情况下，半导体晶片21虽然被分离为各个硅衬底1，但是在柱状电极10及密封膜12的底面间隔着粘接剂层23粘贴着支撑板24，所以能够使得在涂敷由环氧类树脂等热固性树脂构成的树脂保护膜11、使其固化时，包含分离的各个硅衬底1的整体不易翘曲，进而能够使得在其后的工序中不易因翘曲而带来麻烦。
接着，如图10所示，在支撑板24的下表面，粘贴用于覆盖多个小孔的第2保护带29。第2保护带29的作用将在后面说明。接着，如图11所示，用研磨砥石(未图示)适当研磨树脂保护膜11的上表面侧，使树脂保护膜11的厚度适当变薄，而且使树脂保护膜11的上表面平坦化。在此情况下，在支撑板24的下表面粘贴着第2保护带29，所以研磨时所用的水不会侵入支撑板24的小孔。而且，该研磨工序是为了使半导体器件进一步薄型化而进行的。
接着，将第2保护带29从支撑板24的下表面剥离，接着，整体上下反转，如图12所示，将形成了硅衬底1的密封膜12等的面侧向上。接着，将图12所示的构件浸渍到低分子醇或PGMEA(Propyleneglycolmonomethylether acstate Methoxypropyl acetate，丙二醇单甲基醚醋酸酯)等剥离液中，或者，从支撑板24的上表面侧喷涂由上述材料构成的剥离液，则剥离液浸透支撑板24的小孔而到达粘接剂层23，粘接剂层23溶解而被除去，如图13所示，在支撑板24和柱状电极10及密封膜12之间形成空间，支撑板24从柱状电极10及密封膜12的上表面分离。接着，清洗柱状电极10及密封膜12的上表面，除去粘接剂层23的残留物。
接着，如图14所示，在柱状电极10的上表面形成焊料球13。在此情况下，在柱状电极10的上表面形成了毛刺或氧化膜的情况下，将柱状电极10的上表面蚀刻几μm，来除去它们。接着，如图15所示，沿槽28内的中央部的划片道22切断密封膜12及树脂保护膜11。在此情况下，作为刀，采用其宽度与划片道22同一宽度者，所以如图15所示，从硅衬底1、钝化膜3、保护膜5及直至密封膜12的中间位置的各膜的侧面所设的密封保护膜11的中间位置切断密封膜12，使得密封膜12形成该密封膜12的侧面。其结果是，如图1所示，得到多个用树脂保护膜11覆盖着硅衬底1的底面及侧面的构造的半导体器件。

Claims (10)

1.一种半导体器件的制造方法，包含以下步骤：
准备下述构件：在一面上形成了集成电路的半导体晶片的该一面上形成了绝缘膜，在上述绝缘膜上与上述集成电路连接地形成了布线，在上述布线的电极用连接焊盘部上形成了外部连接用凸起电极，在上述外部连接用凸起电极的周围形成了密封膜；
在上述外部连接用凸起电极及上述密封膜上，间隔着粘接剂层粘贴具有多个小孔的支撑板；
在与划片道及其两侧对应的部分的上述半导体晶片的底面侧，形成到达上述密封膜的厚度的中间位置的槽；
在包含上述槽内的上述半导体晶片的底面，形成树脂保护膜；
从上述支撑板的小孔浸透剥离液来溶解并除去上述粘接剂层，由此从上述外部连接用凸起电极及上述密封膜上分离上述支撑板；
以比上述槽的宽度小的宽度，切断上述密封膜及上述树脂保护膜。
2.如权利要求1所述的半导体器件的制造方法，其中，将上述支撑板粘贴到上述粘接剂层上是在真空中一边加热一边进行的。
3.如权利要求1所述的半导体器件的制造方法，其中，在粘贴上述支撑板之后或粘贴上述支撑板之前，具有研磨上述半导体晶片的底面侧而使该半导体晶片的厚度变薄的步骤。
4.如权利要求3所述的半导体器件的制造方法，其中，在研磨上述半导体晶片之前，具有在上述支撑板上粘贴保护带的步骤；在研磨上述半导体晶片之后，具有剥离上述保护带的步骤。
5.如权利要求1所述的半导体器件的制造方法，其中，在形成了上述树脂保护膜之后，具有研磨上述树脂保护膜的上表面侧而使该树脂保护膜变薄、并且上述树脂保护膜的上表面平坦化的步骤。
6.如权利要求5所述的半导体器件的制造方法，其中，在研磨上述树脂保护膜之前，具有在上述支撑板上粘贴其他保护带的步骤；在研磨上述树脂保护膜之后，具有剥离上述其他保护带的步骤。
7.如权利要求1所述的半导体器件的制造方法，其中，上述粘接剂层由非水溶性的高分子化合物构成。
8.如权利要求7所述的半导体器件的制造方法，其中，上述剥离液由低分子醇或丙二醇单甲基醚醋酸酯PGMEA构成。
9.如权利要求1所述的半导体器件的制造方法，其中，在从上述外部连接用凸起电极及上述密封膜上分离了上述支撑板之后，具有在上述外部连接用凸起电极上形成焊料球的步骤。
10.如权利要求9所述的半导体器件的制造方法，其中，上述外部连接用凸起电极是在上述电极用连接焊盘部上形成的柱状电极。
CN2009102251785A 2008-12-10 2009-12-09 半导体器件的制造方法 Expired - Fee Related CN101752273B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008314022A JP4742252B2 (ja) 2008-12-10 2008-12-10 半導体装置の製造方法
JP314022/2008 2008-12-10

Publications (2)

Publication Number Publication Date
CN101752273A true CN101752273A (zh) 2010-06-23
CN101752273B CN101752273B (zh) 2012-11-21

Family

ID=42231537

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009102251785A Expired - Fee Related CN101752273B (zh) 2008-12-10 2009-12-09 半导体器件的制造方法

Country Status (5)

Country Link
US (1) US20100144095A1 (zh)
JP (1) JP4742252B2 (zh)
KR (1) KR101124782B1 (zh)
CN (1) CN101752273B (zh)
TW (1) TW201034074A (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102683279A (zh) * 2010-03-12 2012-09-19 新科金朋有限公司 半导体器件和形成牺牲保护层以在单体化期间保护半导体管芯边缘的方法
CN103109350A (zh) * 2010-09-30 2013-05-15 飞思卡尔半导体公司 处理半导体晶片的方法、半导体晶片以及半导体器件
US8786100B2 (en) 2010-03-15 2014-07-22 Stats Chippac, Ltd. Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die
US9252066B2 (en) 2007-12-14 2016-02-02 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer
US9318441B2 (en) 2007-12-14 2016-04-19 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die
US9548240B2 (en) 2010-03-15 2017-01-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package
US9666500B2 (en) 2007-12-14 2017-05-30 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
CN110265309A (zh) * 2019-05-30 2019-09-20 全球能源互联网研究院有限公司 功率芯片预封装、封装方法及其结构、晶圆预封装结构

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022057265A (ja) * 2020-09-30 2022-04-11 ラピスセミコンダクタ株式会社 半導体装置及び半導体装置の製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5292686A (en) * 1991-08-21 1994-03-08 Triquint Semiconductor, Inc. Method of forming substrate vias in a GaAs wafer
JP3816253B2 (ja) * 1999-01-19 2006-08-30 富士通株式会社 半導体装置の製造方法
JP3865184B2 (ja) * 1999-04-22 2007-01-10 富士通株式会社 半導体装置の製造方法
US6491083B2 (en) * 2001-02-06 2002-12-10 Anadigics, Inc. Wafer demount receptacle for separation of thinned wafer from mounting carrier
JP2006135272A (ja) * 2003-12-01 2006-05-25 Tokyo Ohka Kogyo Co Ltd 基板のサポートプレート及びサポートプレートの剥離方法
US8716592B2 (en) * 2004-07-12 2014-05-06 Quanex Ig Systems, Inc. Thin film photovoltaic assembly method
JP4652030B2 (ja) * 2004-11-29 2011-03-16 東京応化工業株式会社 サポートプレートの貼り付け方法
JP4042749B2 (ja) * 2005-02-21 2008-02-06 カシオ計算機株式会社 半導体装置の製造方法
US7390688B2 (en) * 2005-02-21 2008-06-24 Casio Computer Co.,Ltd. Semiconductor device and manufacturing method thereof
JP2006229112A (ja) * 2005-02-21 2006-08-31 Casio Comput Co Ltd 半導体装置およびその製造方法
JP3859682B1 (ja) * 2005-09-08 2006-12-20 東京応化工業株式会社 基板の薄板化方法及び回路素子の製造方法

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9559029B2 (en) 2007-12-14 2017-01-31 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer
US10998248B2 (en) 2007-12-14 2021-05-04 JCET Semiconductor (Shaoxing) Co. Ltd. Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die
US9252066B2 (en) 2007-12-14 2016-02-02 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer
US9318441B2 (en) 2007-12-14 2016-04-19 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die
US9666500B2 (en) 2007-12-14 2017-05-30 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
US10204866B2 (en) 2010-03-12 2019-02-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation
US8907476B2 (en) 2010-03-12 2014-12-09 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation
CN102683279B (zh) * 2010-03-12 2015-07-22 新科金朋有限公司 半导体器件和形成牺牲保护层以在单体化期间保护半导体管芯边缘的方法
CN102683279A (zh) * 2010-03-12 2012-09-19 新科金朋有限公司 半导体器件和形成牺牲保护层以在单体化期间保护半导体管芯边缘的方法
US9558958B2 (en) 2010-03-12 2017-01-31 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation
US9548240B2 (en) 2010-03-15 2017-01-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package
US9472452B2 (en) 2010-03-15 2016-10-18 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die
US9754867B2 (en) 2010-03-15 2017-09-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package
US8786100B2 (en) 2010-03-15 2014-07-22 Stats Chippac, Ltd. Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die
CN103109350A (zh) * 2010-09-30 2013-05-15 飞思卡尔半导体公司 处理半导体晶片的方法、半导体晶片以及半导体器件
CN110265309A (zh) * 2019-05-30 2019-09-20 全球能源互联网研究院有限公司 功率芯片预封装、封装方法及其结构、晶圆预封装结构

Also Published As

Publication number Publication date
JP4742252B2 (ja) 2011-08-10
TW201034074A (en) 2010-09-16
US20100144095A1 (en) 2010-06-10
KR101124782B1 (ko) 2012-03-27
JP2010140987A (ja) 2010-06-24
KR20100067050A (ko) 2010-06-18
CN101752273B (zh) 2012-11-21

Similar Documents

Publication Publication Date Title
CN101752273B (zh) 半导体器件的制造方法
KR101043836B1 (ko) 반도체 장치의 제조 방법
US7445963B2 (en) Semiconductor package having an interfacial adhesive layer
KR100517075B1 (ko) 반도체 소자 제조 방법
KR100786740B1 (ko) 반도체 장치의 제조 방법, 반도체 장치, 회로 기판 및 전자기기
US7476565B2 (en) Method for forming filling paste structure of WL package
US20080318396A1 (en) Grooving Bumped Wafer Pre-Underfill System
CN101752272B (zh) 半导体器件的制造方法
US20120074565A1 (en) Semiconductor device provided with rear protective film on other side of semiconductor substrate and manufacturing method of the same
US20070190688A1 (en) Method for manufacturing semiconductor device with protection layer
JP2007123362A (ja) デバイスの製造方法
CN101752274A (zh) 半导体装置的制造方法
JP2000040711A (ja) 樹脂封止型半導体装置とその製造方法
US11764066B2 (en) Peeling method for peeling off substrate from support plate
JP2006190987A (ja) パッケージ構造とその製造方法
JPH1174230A (ja) 薄膜半導体装置の製造方法
JP2006140303A (ja) 半導体装置の製造方法
CN100433250C (zh) 半导体装置制造方法、半导体装置、电路基板
JP2006073577A (ja) 半導体ウエハの薄型加工方法
US20080142939A1 (en) Tools structure for chip redistribution and method of the same
JP2010147355A (ja) 半導体装置の製造方法
JP2010147354A (ja) 半導体装置の製造方法
JP2010147292A (ja) 半導体装置の製造方法
KR20070040538A (ko) 보호 수단을 이용한 반도체 칩 분리 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: ZHAOZHUANGWEI CO., LTD.

Free format text: FORMER OWNER: CASIO COMPUTER CO., LTD.

Effective date: 20120314

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20120314

Address after: Tokyo, Japan, Japan

Applicant after: Casio Computer Co Ltd

Address before: Tokyo, Japan, Japan

Applicant before: CASIO Computer Co., Ltd.

C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20121121

Termination date: 20141209

EXPY Termination of patent right or utility model