CN101192371B

CN101192371B - signal interface circuit of LED display module group

Info

Publication number: CN101192371B
Application number: CN200610157141XA
Authority: CN
Inventors: 魏洵佳
Original assignee: Konka Group Co Ltd
Current assignee: Konka Group Co Ltd
Priority date: 2006-11-28
Filing date: 2006-11-28
Publication date: 2011-05-11
Anticipated expiration: 2026-11-28
Also published as: CN101192371A

Abstract

The invention discloses a signal interface circuit for an LED display module group. The invention adopts an LVDS serial communication link which delivers high data transmission speed, large data transmission amount and has good anti-interference performance to replace a universal parallel circuit. The input of the interface circuit comprises one way of differential clock input and two ways of differential data inputs and one way of differential data generates the RGB data through the displacement under the effect of the differential clock input. The RGB data used for an LED module group is obtained through the data under the effect of the high-speed latch signal; the other way of differential data generates the LED control signal data under the effect of the differential clock input and the LED control signal data respectively enters a second latch, a decoding and data expander and an LED displacement clock generator; among which, the decoding and data expander generates an LED row scanning signal and simultaneously inputs the LED row scanning signal into the second latch; the second latch outputs the row latch, row disabling and row scanning signal used for the LED module group under the effect of the high-speed latch signal. The LED displacement clock generator generates the displacement clock signal required for the LED module group so as to realize the video display of the RGB data.

Description

LED shows the signal interface circuit of module

Technical field

The present invention relates to the LED display control technology of electronic applications, relate in particular to the signaling interface technology of LED display control technology.

Background technology

In recent years, flat pannel display (FPD, Flat Panel Display) technology is constantly progressive, as the light emitting diode of constantly bringing forth new ideas (LED, Light Emitting Diode), LCD (LCD, Liquid CrystalDisplay), plasma display (PDP, Plasma Display Plasma Display) and Organic Light Emitting Diode (OLED, OrganicLight-Emitting Diode) etc. display technique appears at the front page of each medium again and again, and wherein the LED performance is particularly outstanding for this.Why LED is subjected to extensively paying attention to and being developed rapidly, be because itself has lot of advantages, for example: the brightness height, operating voltage is low, power consumption is little, it is integrated to be easy to, drive simple, the life-span is long, shock-resistant and stable performance, so its development prospect is very wide.At present just towards high brightness more, more high weather resistance and luminous density, uniformity of luminance, panchromaticization development.Because LED display has above-mentioned advantage, makes it show in large tracts of land, is widely used in fields such as physical culture, advertisement, finance, exhibition, traffic, airports especially.

The technical scope of LED display mainly comprises semiconductor photoelectric device technology, electronic circuit technology, integrated circuit technique, frame treatment technology, the information transmission technology, computer networking technology and electronic product manufacturing and electronic product installation work correlation technique.The control system of display screen has comprised that switching, control, conversion and digitized processing, optical fiber or the kilomega network communication of vision signal, realization, LED driving and the LED of gray scale show many physical circuit designs such as signal access of module.

Wherein, show in the signal interface circuit design of module at all-colour LED, each road RGB data and control signal generally all adopt the parallel transfer pattern, it needs multi-disc CMOS 74HC245 (or 74HC244) to make bus driver, also needs row decoding device (as 74HC138) to make row decoding during dynamic scan.Be 1/4 for example in dutycycle, resolution is in the RGB full-color LED module design of 16 row * 16 row, the RGB data have 12, control signal has 5, when transfer rate is 20MHz, need 3 74HC245, a slice 74HC138, and adopting 20P socket and 20 core flat cables, the buffering of finishing RGB data and LED sweep signal drives, deciphers and transmits.Nearly 17 of data that this parallel transfer pattern transmits and control signals illustrate the I/O resource that has taken more FPGA, so cost is higher, the casing wiring also seems very numerous and diverse.In the face of present LED display system is complicated day by day, the development trend that real-time, reliability and quality requirements are more and more higher is necessary to develop the serial signal place in circuit that a kind of single link speed is fast, transmitted data amount is big, anti-interference is good.

Summary of the invention

In view of this, the present invention's purpose is to provide a kind of LED to show the signal interface circuit of module, and it has adopted the transmission data fast several times, the LVDS serial communication standard that transmitted data amount is big, anti-interference is good, make that LVDS single link speed is fast, transmitted data amount is big.

A kind of LED shows the signal interface circuit of module, this circuit mainly comprises first, second two shift registers, first, second two latchs, decoding and data extender, a LED shift clock generator, high speed latch signal generator and the input of one road differential clocks, the input of two-way differential data, wherein, the input of one road differential clocks enters first, second shift register and high speed latch signal generator by a differential received unit, and the high speed latch signal generator produces a high speed latch signal and enters first, second latch; One road differential data enters first shift register by a differential received unit, and under the differential clocks input action, displacement produces the RGB data, and these data are exported the RGB data of using for the LED module by latches under the effect of high speed latch signal; Another road differential data enters second shift register by a differential received unit, under the differential clocks input action, second shift register produces the LED control signal data, enter second latch respectively, decoding and data extender, LED shift clock generator, decoding wherein and data extender produce the LED line scan signals and are input to second latch simultaneously, second latch is exported the row of using for the LED module and is latched under the effect of high speed latch signal, row turn-offs and line scan signals, LED shift clock generator produces the required shift clock signal of LED module, to realize the demonstration of RGB data.

Described LED shows that the signal interface circuit of module comprises that also 2 select 1 gate, when the required shift clock frequency of LED module≤15MHz, the second road differential data input can be unsettled need not, only with the input of first via differential data, and select the data strobe signal DSET of 1 gate position, the end output of first shift register to be made as the data input of second shift register by receiving 2.

Described LED shows that the signal interface circuit of module comprises that also 2 select 1 gate, when this frequency＞15MHz, the input of the LVDS data of first, second differential received unit all is used, and can select the data strobe signal DSET of 1 gate the data input signal of the second differential received unit to be made as the data input of second shift register by receiving 2.

Described first shift register produces 12 RGB data, under the high speed latch signal effect that latch signal generator produces, and the described output of first latches RD (3-0), GD (3-0), 12 RGB data of BD (3-0).

Described second shift register produces 12 LED control signal data, wherein 2 signals are as the input of second latch, 6 signals are as the input of decoding and data extender, 2 signals are as the input of LED shift clock generator, also have 2 signals and WD (1-0) to join and lead to LED shift clock generator.

Described decoding and data extender produce low 4 line scanning output signals and high 4 line scan signals, and high 4 line scan signals can change the output of 4 bit data extension bits under data expansion gating input HSET effect; 8 outputs of decoding and data extender are as the input of second latch.

Described second latch latchs 1 capable latch signal of LED of output under the effect of high speed latch signal, 1 capable cut-off signals of LED, low 4 LED line scan signals, high 4 LED line scan signals or 4 LED data extension bits, high 4 capable extension bits are in order to support 8 line scannings, and 4 LED data extension bits show in order to the virtual support pixel.

Described LED shift clock generator produces one group of level Four LED and shows the required shift clock signal of module, two outputs by 2 the dial input WD (1-0) or second shift register, choose the shift clock signal of a correspondence in proper order according to LED demonstration module, show the required shift clock SCLK of module as this LED, to realize the locating and displaying of RGB data.

Described first, second shift register is 12 for shift register, and first latch is 12 latchs, and second latch is 10 latchs, and decoding and data extender are 4～8 row decodings and data extender.

Described LED shows that the signal interface circuit of module is 44-Pin TQFP encapsulation or 48-Pin TQFP encapsulation.

Compared with prior art, LED of the present invention shows that the signal interface circuit of module shows the module signal interface circuit by the LED that introduces a kind of LVDS of having interface, it adopts 2～3 high speed LVDS serial links, utilize the internal resource of chip to finish the data of LED demonstration module and intercepting, driving and the decoding of control signal, it only needs 4～6 signal wires and 5～7P socket, can realize that LED shows buffering driving, decoding and the transmitting function of module total data and control signal, virtual support pixel demonstration simultaneously, scanning or static drive.

Description of drawings

Fig. 1 is the LVDS signal interface circuit pin assignments synoptic diagram of the 44-Pin TQFP encapsulation of the present invention's better embodiment;

Fig. 2 is the LVDS signal interface circuit pin assignments synoptic diagram of the 48-Pin TQFP encapsulation of the present invention's better embodiment;

Fig. 3 shows the LVDS signal interface circuit internal logic block diagram of module for the LED of better embodiment of the present invention.

Embodiment

For the purpose, technical scheme, the advantage that make the present invention is clearer and more definite, clear, the present invention's technical scheme is described in further detail below in conjunction with embodiment, accompanying drawing.

LVDS (Low Voltage Differential Signal) is a low-voltage differential signal, and the LVDS interface claims the RS644 bus interface again, is present a kind of data transmission and interfacing.

The most basic LVDS device comprises lvds driver and receiver.The driver of LVDS is formed by driving the right current source of differential lines, and electric current is generally 3.5mA.The LVDS receiver has very high input impedance, so most of electric current of driver output all flows through the build-out resistor of 100 Ω, and produces the voltage of about 350mV at the input end of receiver.When driver overturn, it changed the direction of current of the resistance of flowing through, and therefore produced effective logical one and logical zero state.

The application model of LVDS can have four kinds of forms: 1) unidirectional point-to-point (point to point), this is the typical application pattern.2) two-way point-to-point (bidirectional point to point) can realize two-way half-duplex operation by a pair of twisted-pair feeder.Can constitute by driver and the receiver of the LVDS of standard; But better way is to adopt the bus lvds driver, i.e. BLVDS, and this all connects load design for the bus two ends.3) multiple-limb form (multi drop), promptly a driver connects a plurality of receivers, when identical data will be passed to a plurality of load, can adopt this application form.4) multipoint configuration (multipoint), this moment, multi-point bus was supported a plurality of drivers, also can adopt the BLVDS driver, it can provide two-way half-duplex operation, but at any one time, a drive operation can only be arranged, thereby the arbitration agreement of right of priority that sends and bus needs all to select different software protocols and hardware plan for use according to different application scenarios.

For the LED of the present invention's better embodiment shows that the LVDS signal interface circuit of module mainly contains two kinds, as shown in Figure 1, the LVDS signal interface circuit pin assignments synoptic diagram that shows the 44-Pin TQFP encapsulation of module for the LED of the present invention's better embodiment.As shown in Figure 2, the LVDS signal interface circuit pin assignments synoptic diagram that shows the 48-Pin TQFP encapsulation of module for the LED of the present invention's better embodiment.Be explanation below to pin:

SD0+ high-speed-differential data input 0+

SD0-high-speed-differential data input 0-

SD1+ high-speed-differential data input 1+

SD1-high-speed-differential data input 1-

The input of HCLK+ high-frequency clock+

The input of HCLK-high-frequency clock-

The input of WD (1-0) LED shift clock gating

The input of DSET SD1 data strobe

The input of HSET data expansion gating

RD (3-0) LED 4 road red data serials output

GD (3-0) LED 4 road green data serials output

BD (3-0) LED 4 road blue chromatic numbers are exported according to serial

The output of SCLK LED shift clock

The capable latch signal output of/LATCH LED

The output of/EN LED cut-off signals

Low 4 line scan signals output of H (3-0) LED

XD (3..0)/H (7-4) LED 4 road growth data serials output or high 4 line scan signals output

VCL chip difference 3.3V power supply

VDD chip 3.3V power supply

GND chip ground

The empty pin of NC

The LED of better embodiment of the present invention shows that a kind of LED with LVDS interface of the signal interface circuit introducing of module shows the module signal interface circuit, be used for the access of LED module data and control signal by the special chip that is provided with LVDS difference string line interface, its application transport speed is up to the LVDS differential communication signal of hundreds of Mbps, only need 2～3 pairs of twisted-pair feeders, ground wire and 5～7P socket, can realize that LED shows the transmission of total data and control signal between module, and the internal resource that utilizes chip is finished the data of LED demonstration module and the intercepting of control signal, drive and decoding, the virtual support pixel shows simultaneously, 4-8 line scanning or static drive.

At present, integrated cheaply IC, its LVDS I/O data output rate can reach hundreds of Mbps, adopts non-category 5 twisted pair can pass 15 meters, and in the better embodiment of the present invention the LVDS data rate can up to 360Mbps or more than.This LVDS signal interface circuit is supported the multi-disc bus connecting mode, and adopt 10.00mm * 10.00mm 44-Pin TQFP encapsulation (as shown in Figure 1) or 7.00mm * 7.00mm 48-Pin microminiature TQFP to encapsulate (as shown in Figure 2), help the design of little spacing LED and 4 layers of pcb board.

The LED of better embodiment of the present invention shows that the LVDS signal interface circuit internal logic block diagram of module can be with reference to figure 3, as shown in Figure 3, this LED shows that the LVDS signal interface circuit of module mainly comprises two 12

bit shift register

21,22,12

latch

23,10 latchs 24, one 4～8 row decoding and data extender 25, select 1 gate 26 for one 2,27, one high speed latch signal generators 28 of a LED shift clock generator and three differential received

unit

29A, 29B, 29C.

LED show the LVDS signal interface circuit of module have two-way LVDS data input signal SD0 ± and SD1 ±, promptly by differential received

unit

29A, 29C input, but in actual applications, can be only with the two-way differential data input of differential received unit 29A one road differential data input (SD0 ±) or differential received

unit

29A, 29C (SD0 ±, SD1 ±), this depends on the frequency of the LED shift clock output of employing.When this frequency is low (during as frequency≤15MHz), only with differential received unit 29A one road SD0 ±, can be input to 2 by data strobe signal DSET and select 1 gate 26, select 1 gate 26 that the data input that SD1 is made as shift register 22, the SD1 of differential received unit 29C ± unsettled are exported in the position, end of shift register 21 by 2.When this frequency is higher (as frequency＞15MHz), the LVDS data input signal SD0 of two-way differential received

unit

29A, 29C ± and SD1 ± all be used, can be input to 2 by data strobe signal DSET and select 1 gate 26, select 1 gate 26 with the data input signal SD1 of differential received unit 29C ± the be made as data input of shift register 22 by 2.

Followingly be input as the principle of work explanation that example is carried out the LVDS signal interface circuit, but one of ordinary skill in the art appreciates that technical scheme of the present invention is not limited thereto with two-way LVDS data.

High-speed-differential data input SD0 ± enter shift register 21 by differential received unit 29A, under the high speed shift clock HCLK effect that LED shift clock generator 27 produces, shift register 21 produces 12 RGB data, latchs output RD (3-0), GD (3-0), 12 RGB data of BD (3-0) by latch 23 again under the high speed latch signal HLATCH effect that high speed latch signal generator 28 produces.High-speed-differential data input SD1 ± enter shift register 22 by differential received unit 29C, under high speed shift clock HCLK effect, produce 12 LED control signal data, the input of 2 signals as 10 latchs 24 wherein arranged, the input of 6 signals as 4～8 row decodings and data extender 25 arranged, the input of 2 signals as LED shift clock generator 27 arranged, also have 2 signals and WD (1-0) to join, also lead to LED shift clock generator 27.4～8 row decodings and data extender 25 produce low 4 line scanning output signals and high 4 line scan signals, and high 4 line scan signals can change 4 bit data extension bits XD (3-0) output under data expansion gating input HSET effect.8 outputs of 4～8 row decodings and data extender 25 are as the input of 10 latchs 24.10 latchs 24 latch 1 capable latch signal/LATCH of LED of output, 1 the capable cut-off signals/EN of LED, low 4 LED line scan signals H (3-0), high 4 LED line scan signals H (7-4) or 4 LED data extension bits XD (3-0) under high speed latch signal HLATCH effect.High 4 capable extension bits H (7-4) are in order to support 8 line scannings, and 4 LED data extension bits XD (3-0) show in order to the virtual support pixel.LED shift clock generator 27 produces one group of required shift clock signal of level Four LED module constant current chip, two outputs by 2 dial input WD (1-0) or shift register 22, choose the shift clock signal of a correspondence in proper order according to the LED module, as the required shift clock SCLK of LED module constant current chip at the corresponding levels, to realize the locating and displaying of RGB data.

The LED of above-mentioned better embodiment shows the special chip that have LVDS difference string line interface of module by introducing, because output is corresponding with the shift register position, so function of output pin, except that line scanning H (7-0) and shift clock SCLK, all the other can be defined voluntarily by the user, only need arrange the order of serial data stream to get final product as required, this has brought dirigibility for the design of pcb board.

And, above-mentioned better embodiment LED show that the LVDS signal interface circuit of module also has following advantage:

1. the LED that introduces a kind of LVDS of having interface shows the module signal interface circuit, it adopts 2～3 high speed LVDS serial links, only need 4～6 signal wires and 5～7P socket, can realize that LED shows buffering driving, decoding and the transmitting function of module total data and control signal.

When 2.LED the frequency of shift clock output is low, only with the input of one road LVDS data, when frequency is higher, available two-way LVDS data input.

3. utilize the internal resource of chip to finish the data of LED demonstration module and intercepting, driving and the decoding of control signal, virtual support pixel demonstration simultaneously, 4-8 line scanning or static drive.

4.LVDS data rate can up to 360Mbps or more than, and supporting bus linkage function.

5. the function of output pin except that line scanning H (7-0) and shift clock SCLK, can be defined voluntarily by the user.

6. adopt 10.00mm * 10.00mm 44-Pin or 7.00mm * 7.00mm 48-Pin microminiature TQFP encapsulation, it has reduced the quantity of signal connecting line between LED demonstration module significantly, makes LED casing wires design more succinct, and cost reduces.Reduce the I/O mouth output of scan control plate FPGA significantly, allow to adopt the FPGA or the simpler device of littler encapsulation, further reduced cost.

Though the present invention is described with reference to current better embodiment; but those skilled in the art will be appreciated that; above-mentioned better embodiment only is used for illustrating the present invention; be not to be used for limiting protection scope of the present invention; any within the spirit and principles in the present invention scope; any modification of being done, equivalence replacement, improvement etc. all should be included within the scope of the present invention.

Claims

1. a LED shows the signal interface circuit of module, it is characterized in that: this circuit mainly comprises first, the second two shift registers, first, the second two latchs, decoding and data extender, a LED shift clock generator, high speed latch signal generator and the input of one road differential clocks, first, the input of the second road differential data, wherein, the input of one road differential clocks enters first by the 3rd differential received unit, second shift register and high speed latch signal generator, the high speed latch signal generator produces a high speed latch signal and enters first, second latch; First via differential data enters first shift register by the first differential received unit, under the differential clocks input action, displacement produces the RGB data, and these data show the RGB data that module is used by the output of first latches for LED under the effect of high speed latch signal; The second road differential data enters second shift register by the second differential received unit, under the differential clocks input action, second shift register produces the LED control signal data, enter second latch respectively, decoding and data extender, LED shift clock generator, decoding wherein and data extender produce the LED line scan signals and are input to second latch simultaneously, second latch is exported under the effect of high speed latch signal for LED and is shown that the row that module is used latchs, row turn-offs and line scan signals, LED shift clock generator produces LED and shows the required shift clock signal of module, shows with the video of realizing the RGB data.

2. LED as claimed in claim 1 shows the signal interface circuit of module, it is characterized in that: described LED shows that the signal interface circuit of module comprises that also 2 select 1 gate, when LED shows the required shift clock frequency of module≤15MHz, the second road differential data input can be unsettled need not, only with the input of first via differential data, and select the data strobe signal DSET of 1 gate position, the end output of first shift register to be made as the data input of second shift register by receiving 2.

3. LED as claimed in claim 1 shows the signal interface circuit of module, it is characterized in that: described LED shows that the signal interface circuit of module comprises that also 2 select 1 gate, when this frequency＞15MHz, the input of the LVDS data of first, second differential received unit all is used, and can select the data strobe signal DSET of 1 gate the data input signal of the second differential received unit to be made as the data input of second shift register by receiving 2.

4. LED as claimed in claim 1 shows the signal interface circuit of module, it is characterized in that: described first shift register produces 12 RGB data, under the latch signal effect that latch signal generator produces, the described output of first latches RD (3-0), GD (3-0), 12 RGB data of BD (3-0).

5. LED as claimed in claim 1 shows the signal interface circuit of module, it is characterized in that: described decoding and data extender produce low 4 line scanning output signals and high 4 line scan signals, high 4 line scan signals can change the output of 4 bit data extension bits under data expansion gating input HSET effect; 8 outputs of decoding and data extender are as the input of second latch.

6. the signal interface circuit that shows module as each described LED of claim 1-5, it is characterized in that: described first, second shift register is 12 for shift register, first latch is 12 latchs, second latch is 10 latchs, and decoding and data extender are 4～8 row decodings and data extender.

7. show the signal interface circuit of module as each described LED of claim 1-5, it is characterized in that: described LED shows that the signal interface circuit of module is 44-Pin TQFP encapsulation or 48-Pin TQFP encapsulation.