CN109545754A - A kind of encapsulating structure of chip, packaging method, display device - Google Patents
A kind of encapsulating structure of chip, packaging method, display device Download PDFInfo
- Publication number
- CN109545754A CN109545754A CN201811399916.3A CN201811399916A CN109545754A CN 109545754 A CN109545754 A CN 109545754A CN 201811399916 A CN201811399916 A CN 201811399916A CN 109545754 A CN109545754 A CN 109545754A
- Authority
- CN
- China
- Prior art keywords
- chip
- groove
- circuit board
- region
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 99
- 238000012856 packing Methods 0.000 claims abstract description 86
- 229920002120 photoresistant polymer Polymers 0.000 claims description 79
- 238000005530 etching Methods 0.000 claims description 16
- 230000014759 maintenance of location Effects 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 239000003292 glue Substances 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 abstract description 14
- 238000005516 engineering process Methods 0.000 abstract description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 13
- 230000004308 accommodation Effects 0.000 description 13
- 230000001965 increasing effect Effects 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 239000000945 filler Substances 0.000 description 4
- 230000005611 electricity Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention discloses a kind of encapsulating structure of chip, packaging method, display device, it is related to encapsulation technology field, to solve when being packaged to chip, after carrying out underfill operation, the problem of being easy to generate hole phenomenon between chip and circuit board, leading to the reliability reduction of chip package.The encapsulating structure of the chip includes: circuit board, the packing material that the chip in chip package region is arranged in and is filled between chip and circuit board；Wherein chip includes that multiple pins, pin are electrically connected with corresponding pad correspondingly with multiple pads on circuit board, forms conductive part；Circuit board corresponds between adjacent conductive portion in the region in gap, and at least partly region is provided with the first groove；And/or chip corresponds between adjacent conductive portion in the region in gap, at least partly region is provided with the second groove.The encapsulating structure of chip provided by the invention is for providing driving signal.
Description
Technical field
The present invention relates to encapsulation technology field more particularly to a kind of encapsulating structures of chip, packaging method, display device.
Background technique
Flip-chip packaged technique is a kind of deposition tin ball on the pin of flip-chip, then overturns flip-chip and heats,
Packaged type using the tin ball of melting by flip-chip in conjunction with circuit board.Chip is packaged using this packaged type
When, after by chip in conjunction with circuit board, underfill can be also carried out between chip and circuit board using packing material, is carried out
The main purpose of underfill is: increasing the contact area between chip and circuit board, promotes the knot between chip and circuit board
Intensity is closed, discharges the thermal stress between chip and circuit board, and play a protective role to tin ball.
But with the enhancing of chip transmittability, the pin number of chip increases, so that by chip and circuit board
In conjunction with rear, between chip and circuit board pin, the pad being connect on circuit board with pin, and for connecting the two
The density of tin ball increases, and in this way when carrying out underfill operation, resistance suffered by packing material will increase, simultaneously because filling
Material is very fast in the fringe region flowing velocity of chip, and in the intermediate region of chip by pin, the resistance of pad and tin ball
Cause flowing velocity slower, cause the intermediate region generation hole phenomenon of chip after encapsulation, and then seriously affects chip package
Reliability.
Summary of the invention
The purpose of the present invention is to provide a kind of encapsulating structure of chip, packaging method, display devices, for solving right
When chip is packaged, after carrying out underfill operation, it is easy to generate hole phenomenon between chip and circuit board, leads to core
The problem of reliability of piece encapsulation reduces.
To achieve the goals above, the invention provides the following technical scheme:
The first aspect of the present invention provides a kind of encapsulating structure of chip, comprising:
Circuit board, the chip package region of the circuit board include spaced multiple pads；
The chip in the chip package region is set, and the chip includes multiple correspondingly with the multiple pad
Pin, the pin orthographic projection of orthographic projection and the corresponding pad on the circuit board on the circuit board at least
It partly overlaps, the pin is electrically connected with the corresponding pad, forms conductive part；
The packing material being filled between the chip and the circuit board；
The circuit board corresponds between the adjacent conductive part in the region in gap, and at least partly it is recessed to be provided with first for region
Slot；And/or
The chip corresponds between the adjacent conductive part in the region in gap, and at least partly it is recessed to be provided with second for region
Slot.
Optionally, it is recessed that the whole region that the circuit board corresponds to gap between the adjacent conductive part is provided with first
Slot；And/or
The whole region that the chip corresponds to gap between the adjacent conductive part is provided with the second groove.
Optionally, stream when first groove is filled between the chip and the circuit board along the packing material
Dynamic direction extends；Or the first groove edge is filled between the chip and the circuit board perpendicular to the packing material
When flow direction extend；
And/or
Flow direction when second groove is filled between the chip and the circuit board along the packing material
Extend；Or second groove is along stream when being filled between the chip and the circuit board perpendicular to the packing material
Dynamic direction extends.
Optionally, first groove is equal to perpendicular to the width on its own extending direction and is located at first groove
The pad of two sides is perpendicular to the distance on the first groove extending direction；And/or
Second groove is perpendicular to the width on its own extending direction, equal to being located at drawing for the second groove two sides
Foot is perpendicular to the distance on the second groove extending direction.
Optionally, the circuit board is provided with third groove around the neighboring area of all conductive parts；And/or
The chip is provided with the 4th groove around the neighboring area of all conductive parts.
Optionally, the depth of first groove and the third groove on the direction of the vertical circuit board is 1/
Between 3H~1/2H, H is the thickness of the circuit board；And/or
The depth of second groove and the 4th groove on the direction of the vertical circuit board is in 1/3D~1/
Between 2D, D is thickness of the chip on the direction of the vertical circuit board.
The technical solution of encapsulating structure based on said chip, the second aspect of the present invention provide a kind of display device, packet
Include the encapsulating structure of said chip.
The technical solution of encapsulating structure based on said chip, the third aspect of the present invention provide a kind of encapsulation side of chip
Method, comprising:
A circuit board is made, the chip package region of the circuit board is arranged at intervals with multiple pads；
Make a chip, the chip includes and the multiple pad multiple pins correspondingly；
The step of one circuit board of the production, specifically includes: corresponding to gap between the adjacent pad in the circuit board
At least partly region in region makes the first groove；And/or the step of one chip of the production, specifically includes: in the core
Piece corresponds at least partly region between the adjacent pin in the region in gap and makes the second groove；
The chip is welded on to the chip package region of the circuit board, make the pin on the circuit board just
Project, the pin and the corresponding weldering least partially overlapped with orthographic projection of the corresponding pad on the circuit board
Disk is electrically connected, and forms conductive part；
The packing material of injection flow between the chip and the circuit board, when the packing material fills up the electricity
Behind gap between road plate and the chip, the packing material is solidified.
Optionally, the step of one circuit board of the production also specifically includes:
Third groove is made around the neighboring area of all pads in the circuit board；
And/or
The step of one chip of the production, also specifically includes:
The 4th groove is made around the neighboring area of all pins in the chip.
Optionally, it is specifically included the step of forming first groove and the third groove on the circuit board:
The first photoresist is formed in the side that the circuit board is formed with the pad；
First photoresist is exposed, the first photoresist retention area is formed and the first photoresist removes region,
Wherein the first photoresist removal region is corresponding with first groove and third groove region, and described first
Photoresist retention area is corresponding with other regions in addition to first groove and third groove region；
Develop to the first photoresist after exposure, first photoresist in first photoresist removal region will be located at
Removal；
The circuit board for being located at first photoresist removal region is performed etching, first groove and described the are formed
Three grooves；
The step of forming second groove and four groove on the chip specifically includes:
The second photoresist is formed in the side that the chip is formed with the pin；
Second photoresist is exposed, the second photoresist retention area is formed and the second photoresist removes region,
Wherein the second photoresist removal region is corresponding with second groove and the 4th groove region, and described second
Photoresist retention area is corresponding with other regions in addition to second groove and the 4th groove region；
Develop to the second photoresist after exposure, second photoresist in second photoresist removal region will be located at
Removal；
The chip for being located at second photoresist removal region is performed etching, second groove and the described 4th are formed
Groove.
In technical solution provided by the invention, corresponded between adjacent conductive portion in the region in gap in circuit board, at least portion
Subregion is provided with the first groove；And/or it is corresponded between adjacent conductive portion in the region in gap in chip, at least partly region
It is provided with the second groove；So that the accommodation space being formed between chip and circuit board increases on the direction perpendicular to circuit board
Greatly, i.e., so that the flowing space of packing material becomes larger in the intermediate region of chip on the direction perpendicular to circuit board, according to flat
Row flat-plate theory, when filling packing material between chip and circuit board, packing material resistance suffered by the intermediate region of chip
Reduce, packing material has faster flowing velocity in the intermediate region of chip so that packing material can more evenly,
Underfill process is faster completed, effectively prevents generating hole in the intermediate region of chip, ensure that chip package
Reliability.In addition, since flowing velocity of the packing material in chip and circuit board is accelerated, so that the charging efficiency of packing material
It improves, to preferably improve the production efficiency of chip-packaging structure.
In addition, being increased by way of forming groove in technical solution provided by the invention and being formed in chip and circuit board
Between accommodation space ensure that the reliability of chip package in the case where not changing the thickness of encapsulating structure of chip.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present invention, constitutes a part of the invention, this hair
Bright illustrative embodiments and their description are used to explain the present invention, and are not constituted improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is the schematic cross-section of the encapsulating structure of chip in the prior art；
Fig. 2 is in the prior art to the schematic cross-section of injection fillers material between chip and circuit board；
Fig. 3 is in the prior art to the schematic top plan view of injection fillers material between chip and circuit board；
Fig. 4 is the schematic cross-section for forming hole between chip and circuit board in the prior art；
Fig. 5 is the schematic top plan view for forming hole between chip and circuit board in the prior art；
Fig. 6 is the first schematic cross-section of the encapsulating structure of chip provided in an embodiment of the present invention；
Fig. 7 is the second schematic cross-section of the encapsulating structure of chip provided in an embodiment of the present invention；
Fig. 8 is the third schematic cross-section of the encapsulating structure of chip provided in an embodiment of the present invention；
Fig. 9 is the schematic cross-section provided in an embodiment of the present invention to injection fillers material between chip and circuit board；
Figure 10 is that packing material provided in an embodiment of the present invention fills up the schematic cross-section between chip and circuit board；
Figure 11 is that packing material provided in an embodiment of the present invention fills up the schematic top plan view between chip and circuit board；
Figure 12 is a kind of extension mode of the second groove provided in an embodiment of the present invention；
Figure 13 is another extension mode of the second groove provided in an embodiment of the present invention.
Appended drawing reference:
1- circuit board, 10- pad,
2- chip, 20- pin,
3- packing material, 4- conductive part,
40- tin ball, 5- hole,
The first groove of 61-, the second groove of 62-,
63- third groove, the 4th groove of 64-.
Specific embodiment
The encapsulating structure for the chip that embodiment provides in order to further illustrate the present invention, packaging method, display device, below
It is described in detail in conjunction with Figure of description.
As shown in Figure 1, core when by the encapsulation of chip 2 on the circuit card 1, usually by the encapsulation of chip 2 on the circuit card 1
Piece packaging area, the chip package region include with the one-to-one pad 10 of pin 20 in chip 2, when encapsulation, first in core
Tin ball 40 is deposited on the pin 20 of piece 2, then chip 2 is formed with to the side of pin 20 towards circuit board 1, made in chip 2
Each pin 20 is contacted with pad 10 corresponding on circuit board 1, then is added to the tin ball 40 between pin 20 and pad 10
Heat realizes the electric connection between pin 20 and corresponding pad 10；As shown in Figures 2 and 3, underfill behaviour is then carried out
Make, i.e., using syringe from a side of chip 2 to injection fillers material 3 between chip 2 and circuit board 1, packing material 3 is from chip
2 side is flowed between chip 2 and circuit board 1, until having filled whole spaces between chip 2 and circuit board 1.
As shown in Figure 4 and Figure 5, with the enhancing of 2 transmittability of chip, 20 quantity of pin of chip 2 increases, so that will
After chip 2 is combined with circuit board 1, the density of pin 20, pad 10 and tin ball 40 between chip 2 and circuit board 1 increases
Add, so that suffered resistance increases in 3 flow process of packing material, and since packing material 3 is in the fringe region of chip 2
Flowing velocity is very fast, slower by the resistance flowing velocity of pin 20, pad 10 and tin ball 40 in the intermediate region of chip 2, leads
It causes the intermediate region of chip 2 after encapsulating to be easy to produce hole 5, and then seriously affects the reliability of the encapsulation of chip 2.
To solve the above-mentioned problems, the present inventor it has been investigated that can by increase chip 2 and circuit board 1 it
Between the accommodation space of receiving packing material 3 that is formed solve the above problems.Specifically, Fig. 6-Fig. 8, Figure 10, this hair are please referred to
Bright embodiment provides a kind of encapsulating structure of chip, comprising: circuit board 1, chip 2 and packing material 3；Wherein, circuit board 1
Chip package region includes spaced multiple pads 10；The chip package region of circuit board 1 is arranged in chip 2, and chip 2 wraps
It includes and exists with the one-to-one multiple pins 20 of multiple pads 10, the orthographic projection of pin 20 on the circuit card 1 with corresponding pad 10
Orthographic projection on circuit board 1 is least partially overlapped, and pin 20 is electrically connected with corresponding pad 10, forms conductive part 4；Fill material
Material 3 is filled between chip 2 and circuit board 1；Circuit board 1 corresponds between adjacent conductive portion 4 in the region in gap, at least partly area
Domain is provided with the first groove 61；And/or between the corresponding adjacent conductive portion 4 of chip 2 in the region in gap, at least partly region is set
It is equipped with the second groove 62.
Specifically, when by the encapsulation of chip 2 on the circuit card 1, tin ball 40 is first deposited on the pin 20 of chip 2, then
Chip 2 is formed with the side of pin 20 and circuit board 1 is formed with pad 10 side is opposite, make each pin 20 in chip 2
It is contacted with pad 10 corresponding on circuit board 1, then the tin ball 40 between pin 20 and pad 10 is heated, so that drawing
It is electrically connected between foot 20 and corresponding pad 10, forms conductive part 4, which can be realized in chip 2 and circuit board 1
Between transmit signal；Since pin 20 protrudes from chip 2, pad 10 protrudes from circuit board 1, therefore, by pin 20 with it is corresponding
Chip 2 be electrically connected to form after conductive part 4, between chip 2 and circuit board 1, the receiving formed around each conductive part 4 is empty
Between, as shown in figure 9, using the packing material 3 of syringe injection flow between chip 2 and circuit board 1, when packing material 3 is filled out
Behind gap between full circuit board 1 and chip 2, packing material 3 is solidified, to complete chip 2 being encapsulated in circuit board 1
On.
According to the specific structure of the encapsulating structure of said chip and encapsulation process it is found that chip provided in an embodiment of the present invention
Encapsulating structure in, between the corresponding adjacent conductive portion 4 of circuit board 1 in the region in gap, at least partly region is provided with first
Groove 61；And/or between the corresponding adjacent conductive portion 4 of chip 2 in the region in gap, at least partly it is recessed to be provided with second for region
Slot 62；So that the accommodation space being formed between chip 2 and circuit board 1 is increased up (such as Fig. 6-in the side perpendicular to circuit board 1
Height L of the accommodation space in the direction perpendicular to circuit board 1 is got higher in Fig. 8), i.e., so that in the intermediate region of chip 2 vertical
In on the direction of circuit board 1, the flowing space of packing material 3 becomes larger, according to parallel flat theory, chip 2 and circuit board 1 it
Between fill packing material 3 when, the resistance suffered by the intermediate region of chip 2 of packing material 3 reduce, packing material 3 is in chip 2
Between region there is faster flowing velocity so that packing material 3 more evenly faster can complete underfill mistake
Journey effectively prevents generating hole in the intermediate region of chip 2, ensure that the reliability that chip 2 encapsulates.
In addition, since flowing velocity of the packing material 3 in chip 2 and circuit board 1 is accelerated, so that packing material 3 is filled out
Efficiency raising is filled, to preferably improve the production efficiency of chip-packaging structure.
In addition, being increased by way of forming groove and being formed in the encapsulating structure of chip provided in an embodiment of the present invention
Accommodation space between chip 2 and circuit board 1 ensure that chip 2 in the case where not changing the thickness of encapsulating structure of chip
The reliability of encapsulation.
It is to be appreciated that parallel flat theory refers to: filling has mobility in the space formed by upper and lower parallel-plate
When material, when the distance between upper and lower parallel-plate increases, the resistance that is flowed between upper and lower plate of material with mobility
Reduce, so that the material with mobility being capable of more rapidly being filled in up and down between plate more evenly.
Further, the whole region in gap is provided with the first groove between the corresponding adjacent conductive portion 4 of foregoing circuit plate 1
61；And/or the whole region in gap is provided with the second groove 62 between the corresponding adjacent conductive portion 4 of chip 2.
Specifically, as shown in Figure 10 and Figure 11, the whole region in gap is equal between the corresponding adjacent conductive portion 4 of circuit board 1
First groove 61 is set, and/or, the whole region in gap is respectively provided with the second groove between the corresponding adjacent conductive portion 4 of chip 2
62, so that it is empty to increase the receiving being formed between chip 2 and circuit board 1 to a greater extent on the direction for falling in circuit board 1
Between, so that packing material 3 is suffered by the intermediate region of chip 2 when filling packing material 3 between chip 2 and circuit board 1
Resistance further decreases, packing material 3 the intermediate region of chip 2 flowing velocity, and flowing uniformity further promoted,
Hole is generated in the intermediate region of chip 2 to more effectively avoid, ensure that the reliability that chip 2 encapsulates.
The size of the first groove 61 and the second groove 62 mentioned in above-described embodiment and specific set-up mode are varied,
In some embodiments, flowing side when settable first groove 61 is filled between chip 2 and circuit board 1 along packing material 3
To extension；Or first groove 61 prolong along flow direction when being filled between chip 2 and circuit board 1 perpendicular to packing material 3
It stretches；And/or as shown in figure 13, flow direction when the second groove 62 is filled between chip 2 and circuit board 1 along packing material 3
Extend；As shown in figure 12 or the second groove 62 is along stream when being filled between chip 2 and circuit board 1 perpendicular to packing material 3
Dynamic direction extends.
Specifically, when the first groove 61 of setting and/or the second groove 62 are filled in chip 2 and circuit board 1 along packing material 3
Between when flow direction when extending, packing material 3 can be more advantageous to and quickly flowed, to realize efficient filling.And
When be arranged the first groove 61 and/or the second groove 62 along be filled between chip 2 and circuit board 1 perpendicular to packing material 3 when
When flow direction extends, packing material 3 can be more advantageous to and uniformly spread between chip 2 and circuit board 1, preferably guaranteed
The uniformity of filling.
Preferably, flowing side when settable first groove 61 is filled between chip 2 and circuit board 1 along packing material 3
To extension, and the second groove 62 is set simultaneously along flowing when being filled between chip 2 and circuit board 1 perpendicular to packing material 3
Direction extends；Or settable first groove 61 is along stream when being filled between chip 2 and circuit board 1 perpendicular to packing material 3
Dynamic direction extends, and flowing side when the second groove 62 is filled between chip 2 and circuit board 1 along packing material 3 is arranged simultaneously
To extension；Above two set-up mode is more advantageous to packing material 3 and quickly, is uniformly filled between chip 2 and circuit board 1,
The reliability and packaging efficiency of the encapsulation of chip 2 can preferably be promoted.
Further, settable first groove 61 perpendicular to the width on its own extending direction, be equal to be located at this
The pad 10 of one groove, 61 two sides is perpendicular to the distance on 61 extending direction of the first groove；And/or second groove 62 vertical
Width on its own extending direction prolongs equal to the pin 20 for being located at 62 two sides of the second groove perpendicular to the second groove 62
Stretch the distance on direction.
Specifically, above-mentioned set-up mode enables to the first groove 61 and the second groove 62 to have maximum width, so that
The accommodation space being formed between chip 2 and circuit board 1 maximizes, thus when packing material 3 flows in accommodation space, it is suffered
Resistance maximally reduces, packing material 3 the intermediate region of chip 2 flowing velocity, and flowing uniformity it is effective
It is promoted, generates hole in the intermediate region of chip 2 to more effectively avoid, ensure that the reliability that chip 2 encapsulates.
Further, as Figure 6-Figure 8, around the periphery of whole conductive parts 4 in circuit board 1 provided by the above embodiment
Region is provided with third groove 63；And/or the neighboring area in chip 2 around whole conductive parts 4 is provided with the 4th groove 64.
Specifically, above-mentioned set-up mode is enabled in the fringe region of chip 2 on the direction perpendicular to circuit board 1,
The flowing space of packing material 3 becomes larger so that packing material 3 by chip 2 fringe region inflow when, perpendicular to circuit board
The flow distance in 1 direction, packing material 3 increases, to slow down speed when 3 edge region of packing material flows into, makes
Packing material 3 fills the speed of entire accommodation space and becomes more uniform so that packing material 3 can more evenly, fastly
The completion underfill process of speed ensure that chip 2 encapsulates to effectively prevent generating hole in the intermediate region of chip 2
Reliability.
Further, as Figure 6-Figure 8, the first groove 61 provided by the above embodiment, the second groove 62, third groove
63 and the 4th the depth of groove 64 can be arranged according to actual needs, illustratively, the first groove 61 and third groove 63 are vertical
For depth h on the direction of circuit board 1 between 1/3H~1/2H, H is the thickness of circuit board 1；And/or 62 He of the second groove
For depth d of 4th groove 64 on the direction of perpendicular circuit board 1 between 1/3D~1/2D, D is chip 2 in perpendicular circuit board
Thickness on 1 direction.
Specifically, the depth of the first groove 61, the second groove 62, third groove 63 and the 4th groove 64 is arranged above-mentioned
Range not only increases the appearance being formed between chip 2 and circuit board 1 compared with limits on the direction perpendicular to circuit board 1
It receives space, and will not have a adverse impact to the working performance of chip 2 and circuit board 1.So that the encapsulating structure of chip exists
While guaranteeing good working performance, the reliability that chip 2 encapsulates preferably ensure that.
The embodiment of the invention also provides a kind of display device, the encapsulating structure including chip provided by the above embodiment.
Since the reliability that the encapsulating structure of chip provided by the above embodiment encapsulates is higher, and there is good workability
Can, therefore, display device provided in an embodiment of the present invention is when including the encapsulating structure of chip provided by the above embodiment, equally
It can be realized good working performance, and there is good reliability.
The embodiment of the invention also provides a kind of packaging methods of chip, for realizing chip provided by the above embodiment
Encapsulating structure, the packaging method include:
A circuit board 1 is made, the chip package region of circuit board 1 is arranged at intervals with multiple pads 10；
A chip 2 is made, chip 2 includes and the one-to-one multiple pins 20 of multiple pads 10；
The step of making circuit board 1 specifically includes: between the corresponding adjacent pad 10 of circuit board 1 in the region in gap
At least partly region makes the first groove 61；And/or the step of one chip 2 of production, specifically includes: corresponding to adjacent draw in chip 2
At least partly region between foot 20 in the region in gap makes the second groove 62；
Chip 2 is welded on to the chip package region of circuit board 1, make the orthographic projection of pin 20 on the circuit card 1 with it is corresponding
The orthographic projection on the circuit card 1 of pad 10 it is least partially overlapped, pin 20 is electrically connected with corresponding pad 10, is formed conductive
Portion 4；
The packing material 3 of injection flow between chip 2 and circuit board 1, when packing material 3 fills up circuit board 1 and chip 2
Between gap after, packing material 3 is solidified.
Specifically, when making circuit board 1, circuit board 1 chip package region production room every setting multiple pads
10, multiple pad 10 is the convex block for protruding from circuit board 1；When making chip 2, which can be flip-chip, in core
The multiple pins 20 made on piece 2 are the convex block for protruding from chip 2；Moreover, when making circuit board 1, it can be right in circuit board 1
At least partly region between adjacent pad 10 in the region in gap is answered to make the first groove 61；And/or when making chip 2,
At least partly region between adjacent leads 20 in the region in gap can be corresponded in chip 2 make the second groove 62；Then in core
Tin ball 40 is deposited on the pin 20 of piece 2, then chip 2 is formed with the side of pin 20 and circuit board 1 is formed with the one of pad 10
Side is opposite, contacts each pin 20 in chip 2 with pad 10 corresponding on circuit board 1, then to positioned at pin 20 and pad 10
Between tin ball 40 heated so that the electric connection between pin 20 and corresponding pad 10, form conductive part 4, this is led
Electric portion 4 can be realized and transmit signal between chip 2 and circuit board 1；Since pin 20 protrudes from chip 2, pad 10 is protruded from
Circuit board 1, therefore, after pin 20 is electrically connected to form conductive part 4 with corresponding chip 2, chip 2 and circuit board 1 it
Between, the accommodation space for surrounding each conductive part 4 is formed, the filling material of syringe injection flow between chip 2 and circuit board 1 is utilized
Material 3, after packing material 3 fills up the gap between circuit board 1 and chip 2, packing material 3 is solidified, thus complete by
Chip 2 encapsulates on the circuit card 1.
In the packaging method of chip provided in an embodiment of the present invention, the gap between the corresponding adjacent conductive portion 4 of circuit board 1
In region, at least partly region forms the first groove 61；And/or the region in gap between adjacent conductive portion 4 is corresponded in chip 2
In, at least partly region forms the second groove 62；So that the accommodation space being formed between chip 2 and circuit board 1 perpendicular to
The side of circuit board 1 is increased up, i.e., so that in the intermediate region of chip 2 on the direction perpendicular to circuit board 1, packing material 3
The flowing space become larger, according to parallel flat theory, between chip 2 and circuit board 1 fill packing material 3 when, packing material 3
The resistance suffered by the intermediate region of chip 2 reduces, and packing material 3 has faster flowing velocity in the intermediate region of chip 2, from
And enable packing material 3 more evenly, underfill process is faster completed, is effectively prevented in the centre of chip 2
Region generates hole, ensure that the reliability that chip 2 encapsulates.
In addition, since flowing velocity of the packing material 3 in chip 2 and circuit board 1 is accelerated, so that packing material 3 is filled out
Efficiency raising is filled, to preferably improve the packaging efficiency of chip 2.
In addition, being increased by way of forming groove and being formed in the packaging method of chip provided in an embodiment of the present invention
Accommodation space between chip 2 and circuit board 1 ensure that chip 2 in the case where not changing the thickness of encapsulating structure of chip
The reliability of encapsulation.
Further, the step of one circuit board 1 of production provided by the above embodiment also specifically includes: surrounding in circuit board 1
The neighboring area of whole pads 10 makes third groove 63；And/or the step of one chip 2 of production, also specifically includes: in chip 2
The 4th groove 64 is made around the neighboring area of whole pins 20.
Specifically, above-mentioned third groove 63 can be formed in a same patterning processes with the first groove 61, the 4th groove 64
Can be with the second groove 62 with being formed in a patterning processes, and made third groove 63 and the 4th groove 64 can be with
Surround the whole conductive parts 4 being formed between chip 2 and circuit board 1.
It is above-mentioned that third groove 63 is set on the circuit card 1, and the 4th groove 64 is set on chip 2 and is enabled in core
On the direction perpendicular to circuit board 1, the flowing space of packing material 3 becomes larger the fringe region of piece 2, so that packing material 3 exists
When being flowed by the fringe region of chip 2, in the direction perpendicular to circuit board 1, the flow distance of packing material 3 increases, to subtract
Speed when 3 edge region of packing material flows into is delayed, so that the speed that packing material 3 fills entire accommodation space becomes more
Add uniformly so that packing material 3 can more evenly, quickly finish underfill process, to effectively prevent in core
The intermediate region of piece 2 generates hole, ensure that the reliability that chip 2 encapsulates.
The step of forming the first groove 61 and third groove 63 on the circuit card 1 above-mentioned in some embodiments, can specifically wrap
It includes:
The first photoresist is formed in the side that circuit board 1 is formed with pad 10；
First photoresist is exposed, the first photoresist retention area is formed and the first photoresist removes region, wherein
First photoresist remove region it is corresponding with the first groove 61 and 63 region of third groove, the first photoresist retention area and
Other regions in addition to 63 region of the first groove 61 and third groove are corresponding；
Develop to the first photoresist after exposure, the first photoresist for being located at the first photoresist removal region is gone
It removes；
The circuit board 1 for being located at the first photoresist removal region is performed etching, the first groove 61 and third groove 63 are formed.
Specifically, the side that can be formed with pad 10 on the circuit card 1 is coated with to form the first photoresist, then using including
The mask plate of transmission region and lightproof area is exposed the first photoresist, forms the first photoresist retention area and the first light
Photoresist removes region, wherein the first photoresist removal region is corresponding with the first groove 61 and 63 region of third groove, the
One photoresist retention area is corresponding with other regions in addition to 63 region of the first groove 61 and third groove；Then sharp
Developed with developer solution to the first photoresist after exposure, the first photoresist that will be located at the first photoresist removal region is gone
It removes, the circuit board 1 for being located at the first photoresist removal region is exposed, finally to the electricity for being located at the first photoresist removal region
Road plate 1 performs etching, and forms the first groove 61 and third groove 63.
It is noted that specifically circuit board 1 can be performed etching using wet-etching technique when being performed etching to circuit board 1, but
It is not limited only to this.In addition when being performed etching to circuit board 1, the conductive film layer etched into circuit board 1 is avoided, i.e., to be guaranteed
After performing etching to circuit board 1, circuit board 1 still has stable working performance.
It is above-mentioned in some embodiments to be specifically included the step of forming the second groove 62 and the 4th groove 64 on chip 2:
The second photoresist is formed in the side that chip 2 is formed with pin 20；
Second photoresist is exposed, the second photoresist retention area is formed and the second photoresist removes region, wherein
Second photoresist remove region it is corresponding with the second groove 62 and 64 region of the 4th groove, the second photoresist retention area and
Other regions in addition to the second groove 62 and 64 region of the 4th groove are corresponding；
Develop to the second photoresist after exposure, the second photoresist for being located at the second photoresist removal region is gone
It removes；
The chip 2 for being located at the second photoresist removal region is performed etching, the second groove 62 and the 4th groove 64 are formed.
Specifically, the side that pin 20 can be formed on chip 2 is coated with to form the second photoresist, then using including saturating
The mask plate of light region and lightproof area is exposed the second photoresist, forms the second photoresist retention area and the second photoetching
Glue removes region, wherein the second photoresist removal region is corresponding with the second groove 62 and 64 region of the 4th groove, second
Photoresist retention area is corresponding with other regions in addition to the second groove 62 and 64 region of the 4th groove；Then it utilizes
Developer solution develops to the second photoresist after exposure, and the second photoresist that will be located at the second photoresist removal region is gone
It removes, the chip 2 for being located at the second photoresist removal region is exposed, finally to the chip for being located at the second photoresist removal region
2 perform etching, and form the second groove 62 and the 4th groove 64.
It is noted that can specifically be performed etching using dry carving technology to chip 2, but not only when being performed etching to chip 2
It is limited to this.In addition when being performed etching to chip 2, the conductive film layer etched into chip 2 is avoided, i.e., to be guaranteed to chip
After 2 perform etching, chip 2 still has stable working performance.
Unless otherwise defined, the technical term or scientific term that the disclosure uses should be tool in fields of the present invention
The ordinary meaning for thering is the personage of general technical ability to be understood." first ", " second " used in the disclosure and similar word are simultaneously
Any sequence, quantity or importance are not indicated, and are used only to distinguish different component parts." comprising " or "comprising" etc.
Similar word means that the element or object before the word occur covers the element or object for appearing in the word presented hereinafter
And its it is equivalent, and it is not excluded for other elements or object.The similar word such as " connection " or " connected " is not limited to physics
Or mechanical connection, but may include electrical connection, it is either direct or indirectly."upper", "lower",
"left", "right" etc. is only used for indicating relative positional relationship, and after the absolute position for being described object changes, then the relative position is closed
System may also correspondingly change.
It is appreciated that ought such as layer, film, region or substrate etc element be referred to as be located at another element "above" or "below"
When, which " direct " can be located at "above" or "below" another element, or may exist intermediary element.
In the description of above embodiment, particular features, structures, materials, or characteristics can be at any one or more
It can be combined in any suitable manner in a embodiment or example.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
1. a kind of encapsulating structure of chip, comprising:
Circuit board, the chip package region of the circuit board include spaced multiple pads；
The chip in the chip package region is set, and the chip includes and the multiple pad is one-to-one multiple draws
Foot, the pin is in orthographic projection at least portion of the orthographic projection with the corresponding pad on the circuit board on the circuit board
Divide overlapping, the pin is electrically connected with the corresponding pad, forms conductive part；
The packing material being filled between the chip and the circuit board；
It is characterized in that, the circuit board corresponds between the adjacent conductive part in the region in gap, at least partly region is arranged
There is the first groove；And/or
The chip corresponds between the adjacent conductive part in the region in gap, and at least partly region is provided with the second groove.
2. the encapsulating structure of chip according to claim 1, which is characterized in that the circuit board corresponds to the adjacent conduction
The whole region in gap is provided with the first groove between portion；And/or
The whole region that the chip corresponds to gap between the adjacent conductive part is provided with the second groove.
3. the encapsulating structure of chip according to claim 1, which is characterized in that
Flow direction when first groove is filled between the chip and the circuit board along the packing material extends；
Or first groove is along flowing side when being filled between the chip and the circuit board perpendicular to the packing material
To extension；
And/or
Flow direction when second groove is filled between the chip and the circuit board along the packing material extends；
Or second groove is along flowing side when being filled between the chip and the circuit board perpendicular to the packing material
To extension.
4. the encapsulating structure of chip according to claim 3, which is characterized in that
First groove exists perpendicular to the width on its own extending direction equal to the pad for being located at the first groove two sides
Perpendicular to the distance on the first groove extending direction；And/or
Second groove exists perpendicular to the width on its own extending direction equal to the pin for being located at the second groove two sides
Perpendicular to the distance on the second groove extending direction.
5. the encapsulating structure of chip according to any one of claims 1 to 4, which is characterized in that
The circuit board is provided with third groove around the neighboring area of all conductive parts；And/or
The chip is provided with the 4th groove around the neighboring area of all conductive parts.
6. the encapsulating structure of chip according to claim 5, which is characterized in that
The depth of first groove and the third groove on the direction of the vertical circuit board 1/3H~1/2H it
Between, H is the thickness of the circuit board；And/or
The depth of second groove and the 4th groove on the direction of the vertical circuit board 1/3D~1/2D it
Between, D is thickness of the chip on the direction of the vertical circuit board.
7. a kind of display device, which is characterized in that the encapsulating structure including chip such as according to any one of claims 1 to 6.
8. a kind of packaging method of chip characterized by comprising
A circuit board is made, the chip package region of the circuit board is arranged at intervals with multiple pads；
Make a chip, the chip includes and the multiple pad multiple pins correspondingly；
The step of one circuit board of the production, specifically includes: corresponding to the region in gap between the adjacent pad in the circuit board
In at least partly region make the first groove；And/or the step of one chip of the production, specifically includes: in the chip pair
At least partly region between the adjacent pin in the region in gap is answered to make the second groove；
The chip is welded on to the chip package region of the circuit board, makes orthographic projection of the pin on the circuit board
Least partially overlapped with orthographic projection of the corresponding pad on the circuit board, the pin and the corresponding pad are electric
Property connection, formed conductive part；
The packing material of injection flow between the chip and the circuit board, when the packing material fills up the circuit board
Behind gap between the chip, the packing material is solidified.
9. the packaging method of chip according to claim 8, which is characterized in that the step of one circuit board of the production also has
Body includes:
Third groove is made around the neighboring area of all pads in the circuit board；
And/or
The step of one chip of the production, also specifically includes:
The 4th groove is made around the neighboring area of all pins in the chip.
10. the packaging method of chip according to claim 9, which is characterized in that form described on the circuit board
The step of one groove and the third groove, specifically includes:
The first photoresist is formed in the side that the circuit board is formed with the pad；
First photoresist is exposed, the first photoresist retention area is formed and the first photoresist removes region, wherein
First photoresist removal region is corresponding with first groove and third groove region, first photoetching
It is corresponding with other regions in addition to first groove and third groove region that glue retains region；
Develop to the first photoresist after exposure, the first photoresist for being located at first photoresist removal region is gone
It removes；
The circuit board for being located at first photoresist removal region is performed etching, first groove is formed and the third is recessed
Slot；
The step of forming second groove and four groove on the chip specifically includes:
The second photoresist is formed in the side that the chip is formed with the pin；
Second photoresist is exposed, the second photoresist retention area is formed and the second photoresist removes region, wherein
Second photoresist removal region is corresponding with second groove and the 4th groove region, second photoetching
It is corresponding with other regions in addition to second groove and the 4th groove region that glue retains region；
Develop to the second photoresist after exposure, the second photoresist for being located at second photoresist removal region is gone
It removes；
The chip for being located at second photoresist removal region is performed etching, second groove and described 4th recessed is formed
Slot.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811399916.3A CN109545754B (en) | 2018-11-22 | 2018-11-22 | Chip packaging structure, chip packaging method and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811399916.3A CN109545754B (en) | 2018-11-22 | 2018-11-22 | Chip packaging structure, chip packaging method and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109545754A true CN109545754A (en) | 2019-03-29 |
| CN109545754B CN109545754B (en) | 2021-01-26 |
Family
ID=65849335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811399916.3A Active CN109545754B (en) | 2018-11-22 | 2018-11-22 | Chip packaging structure, chip packaging method and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109545754B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110707053A (en) * | 2019-11-13 | 2020-01-17 | 东莞市新懿电子材料技术有限公司 | Chip packaging structure and chip packaging method |
| CN110707052A (en) * | 2019-11-13 | 2020-01-17 | 东莞市新懿电子材料技术有限公司 | Chip packaging structure |
| CN114975130A (en) * | 2022-05-31 | 2022-08-30 | 浙江禾芯集成电路有限公司 | Packaging method of packaging structure of vertical MOSFET chip |
| CN115023024A (en) * | 2021-09-26 | 2022-09-06 | 荣耀终端有限公司 | Circuit board and electronic equipment |
| CN115090981A (en) * | 2022-06-29 | 2022-09-23 | 中机智能装备创新研究院(宁波)有限公司 | Grain wear-resistant coating brazing preparation method and preparation device |
| WO2023042615A1 (en) * | 2021-09-14 | 2023-03-23 | ローム株式会社 | Semiconductor device and mounting structure for semiconductor element |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288451B1 (en) * | 1998-06-24 | 2001-09-11 | Vanguard International Semiconductor Corporation | Flip-chip package utilizing a printed circuit board having a roughened surface for increasing bond strength |
| CN1334601A (en) * | 2000-07-25 | 2002-02-06 | 日本电气株式会社 | Flip-chip semiconductor device and mfg. method thereof |
| US6750546B1 (en) * | 2001-11-05 | 2004-06-15 | Skyworks Solutions, Inc. | Flip-chip leadframe package |
| JP2006222126A (en) * | 2005-02-08 | 2006-08-24 | Murata Mfg Co Ltd | Circuit board |
| WO2008111345A1 (en) * | 2007-03-09 | 2008-09-18 | Nec Corporation | Electronic device, and electronic device manufacturing method |
| US20090160039A1 (en) * | 2007-12-20 | 2009-06-25 | National Semiconductor Corporation | Method and leadframe for packaging integrated circuits |
| JP2013131508A (en) * | 2010-04-06 | 2013-07-04 | Murata Mfg Co Ltd | Electronic device |
| CN103531560A (en) * | 2013-10-31 | 2014-01-22 | 矽力杰半导体技术(杭州)有限公司 | Chip packaging structure and manufacturing method thereof |
| CN103633037A (en) * | 2012-08-27 | 2014-03-12 | 国碁电子(中山)有限公司 | Encapsulation structure and manufacturing method thereof |
-
2018
- 2018-11-22 CN CN201811399916.3A patent/CN109545754B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288451B1 (en) * | 1998-06-24 | 2001-09-11 | Vanguard International Semiconductor Corporation | Flip-chip package utilizing a printed circuit board having a roughened surface for increasing bond strength |
| CN1334601A (en) * | 2000-07-25 | 2002-02-06 | 日本电气株式会社 | Flip-chip semiconductor device and mfg. method thereof |
| US6750546B1 (en) * | 2001-11-05 | 2004-06-15 | Skyworks Solutions, Inc. | Flip-chip leadframe package |
| JP2006222126A (en) * | 2005-02-08 | 2006-08-24 | Murata Mfg Co Ltd | Circuit board |
| WO2008111345A1 (en) * | 2007-03-09 | 2008-09-18 | Nec Corporation | Electronic device, and electronic device manufacturing method |
| US20090160039A1 (en) * | 2007-12-20 | 2009-06-25 | National Semiconductor Corporation | Method and leadframe for packaging integrated circuits |
| JP2013131508A (en) * | 2010-04-06 | 2013-07-04 | Murata Mfg Co Ltd | Electronic device |
| CN103633037A (en) * | 2012-08-27 | 2014-03-12 | 国碁电子(中山)有限公司 | Encapsulation structure and manufacturing method thereof |
| CN103531560A (en) * | 2013-10-31 | 2014-01-22 | 矽力杰半导体技术(杭州)有限公司 | Chip packaging structure and manufacturing method thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110707053A (en) * | 2019-11-13 | 2020-01-17 | 东莞市新懿电子材料技术有限公司 | Chip packaging structure and chip packaging method |
| CN110707052A (en) * | 2019-11-13 | 2020-01-17 | 东莞市新懿电子材料技术有限公司 | Chip packaging structure |
| WO2023042615A1 (en) * | 2021-09-14 | 2023-03-23 | ローム株式会社 | Semiconductor device and mounting structure for semiconductor element |
| CN115023024A (en) * | 2021-09-26 | 2022-09-06 | 荣耀终端有限公司 | Circuit board and electronic equipment |
| CN115023024B (en) * | 2021-09-26 | 2023-10-20 | 荣耀终端有限公司 | Circuit board and electronic equipment |
| CN114975130A (en) * | 2022-05-31 | 2022-08-30 | 浙江禾芯集成电路有限公司 | Packaging method of packaging structure of vertical MOSFET chip |
| CN115090981A (en) * | 2022-06-29 | 2022-09-23 | 中机智能装备创新研究院(宁波)有限公司 | Grain wear-resistant coating brazing preparation method and preparation device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109545754B (en) | 2021-01-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109545754A (en) | A kind of encapsulating structure of chip, packaging method, display device | |
| JP4536603B2 (en) | Manufacturing method of semiconductor device, mounting substrate for semiconductor device, and semiconductor device | |
| CN204834611U (en) | Lead frame and unit, semiconductor package structure and unit thereof | |
| JP2006190951A (en) | Light emitting diode package and its manufacturing process | |
| KR101569577B1 (en) | Package-on-package structures and methods for forming the same | |
| CN104520988A (en) | Methods for flip chip stacking | |
| CN107958882A (en) | Encapsulating structure of chip and preparation method thereof | |
| CN105390570A (en) | LED packaging structure and manufacturing method | |
| CN107403771A (en) | Semiconductor package and its method for packing | |
| JP2009177061A (en) | Semiconductor apparatus and method of manufacturing the same | |
| CN109065560A (en) | The packaging method and encapsulating structure of image sensing chip | |
| JP2023083481A (en) | Semiconductor manufacturing device, method for manufacturing semiconductor device using the same, and semiconductor device | |
| CN103560125A (en) | Three-dimensional flexible substrate electromagnetic shielding packaged structure and manufacturing method | |
| CN103426869B (en) | Package on package and manufacture method thereof | |
| CN112563247B (en) | Electromagnetic shielding packaging structure and electromagnetic shielding packaging method | |
| CN105938824A (en) | Semiconductor package assembly | |
| CN108496250A (en) | The manufacture of multi-chip module | |
| KR20020084702A (en) | Mounting substrate and structure having semiconductor element mounted on substrate | |
| CN107958844A (en) | Packaging structure and manufacturing method thereof | |
| CN105845585A (en) | Chip packaging method and chip packaging structure | |
| CN104517936B (en) | Encapsulating structure | |
| KR20110098679A (en) | Integrated circuit packaging system with exposed conductor and method of manufacture thereof | |
| CN103824784B (en) | With connecting the method that sheet realizes the semiconductor packages connected | |
| CN104733415A (en) | Semiconductor Package And Fabrication Method Thereof | |
| KR20120080320A (en) | Semiconductor package for stack and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |