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KR20120080320A - Semiconductor package for stack and method for manufacturing the same - Google Patents

Semiconductor package for stack and method for manufacturing the same Download PDF

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Publication number
KR20120080320A
KR20120080320A KR1020110001696A KR20110001696A KR20120080320A KR 20120080320 A KR20120080320 A KR 20120080320A KR 1020110001696 A KR1020110001696 A KR 1020110001696A KR 20110001696 A KR20110001696 A KR 20110001696A KR 20120080320 A KR20120080320 A KR 20120080320A
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South Korea
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substrate
conductive
semiconductor
stacked
mold via
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KR1020110001696A
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Korean (ko)
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KR101185457B1 (en
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김진성
김광호
박동주
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앰코 테크놀로지 코리아 주식회사
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Priority to KR1020110001696A priority Critical patent/KR101185457B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE: A stacked type semiconductor package and a manufacturing method thereof are provided to increase capacity of a memory chip by molding both sides of a substrate with a molding compound resin after wire-bonding a semiconductor chip with the substrate. CONSTITUTION: A first semiconductor chip(12a) is laminated on a chip adhesion area divided at one side of a substrate(10). A first conductive wire(16a) is connected between the first semiconductor ship and a conductive pattern exposed to one side of the substrate. A second semiconductor chip(12b) is laminated on a chip adhesion area divided at the other side of the substrate. A second conductive wire(16b) is connected between the second semiconductor chip and a conductive pattern exposed to the other side of the substrate. A first molding compound resin(18a) protects the first semiconductor chip and the first conductive wire.

Description

적층형 반도체 패키지 및 그 제조 방법{Semiconductor package for stack and method for manufacturing the same}Stacked semiconductor package and method for manufacturing the same {Semiconductor package for stack and method for manufacturing the same}

본 발명은 적층형 반도체 패키지 및 그 제조 방법에 관한 것으로서, 더욱 상세하게는 기판의 양면에 반도체 칩을 탑재하여 몰딩시킨 양면 몰딩 구조로 제작하여, 공정 비용 및 패키지의 두께를 줄일 수 있도록 한 적층형 반도체 패키지 및 그 제조 방법에 관한 것이다.
The present invention relates to a stacked semiconductor package and a method of manufacturing the same, and more particularly, to a stacked semiconductor package manufactured by forming a double-sided molding structure in which a semiconductor chip is mounted on both sides of a substrate and molding, thereby reducing process costs and package thickness. And a method for producing the same.

여러개의 반도체 칩을 적층하여 데이터 저장 용량을 향상시키는 동시에 데이터 처리 속도를 향상시킬 수 있는 다양한 구조의 메모리 반도체 패키지가 출시되고 있으며, 그 일례를 첨부한 도 5 내지 도 7을 참조로 설명하면 다음과 같다.A memory semiconductor package having various structures capable of stacking a plurality of semiconductor chips to improve data storage capacity and at the same time improving data processing speed has been released. Referring to FIGS. same.

인쇄회로기판(10, 이하 기판이라 칭함)의 상면 중앙쪽에 구획된 칩 부착영역에 여러개의 반도체 칩(12)이 교번으로 적층 부착된다.A plurality of semiconductor chips 12 are alternately stacked and attached to the chip attaching region partitioned at the center of the upper surface of the printed circuit board 10 (hereinafter referred to as a substrate).

또한, 각 반도체 칩(12)이 순차적으로 적층 부착될 때, 도전성 와이어(16)를 연결하는 와이어 본딩 공정이 진행되는 바, 도전성 와이어(16)의 일끝단은 각 반도체 칩(12)의 본딩패드에 1차 본딩(볼 본딩)되고, 타끝단은 기판의 상면에 노출되어 있는 전도성패턴에 2차 본딩(스티치 본딩)된다.In addition, when the semiconductor chips 12 are sequentially stacked and attached, a wire bonding process of connecting the conductive wires 16 is performed, and one end of the conductive wires 16 is a bonding pad of each semiconductor chip 12. Primary bonding (ball bonding) is carried out, and the other end is secondary bonding (stitch bonding) to the conductive pattern exposed on the upper surface of the substrate.

이어서, 각 반도체 칩(12)과 도전성 와이어(16)를 포함하는 기판(10)의 상면을 몰딩 컴파운드 수지(18)로 몰딩하는 공정이 진행되어, 각 반도체 칩(12)과 도전성 와이어(16)들이 몰딩 컴파운드 수지(18)에 의하여 감싸여지며 보호되는 상태가 된다.Subsequently, a process of molding the upper surface of the substrate 10 including the semiconductor chips 12 and the conductive wires 16 with the molding compound resin 18 proceeds to proceed the respective semiconductor chips 12 and the conductive wires 16. Are surrounded by the molding compound resin 18 and are in a protected state.

다음으로, 상기 몰딩 컴파운드 수지의 상면에서 기판의 전도성패턴이 노출될 때까지 레이저 가공 공정에 의한 관통 몰드 비아(TMV: Through Mold Via)가 형성되고, 이 관통 몰드 비아(20)내에는 전도성 충진재가 충진된다.Next, a through mold via (TMV) is formed by a laser processing process on the upper surface of the molding compound resin until the conductive pattern of the substrate is exposed, and the conductive filler is formed in the through mold via 20. It is filled.

최종적으로, 상기 기판(10)의 저면을 통해 노출되어 있는 볼랜드(22)에 입출력단자 역할을 하는 솔더볼(24)을 융착시킴으로써, 첨부한 도 4에서 보는 바와 같이 적층을 위한 반도체 패키지로 완성된다.Finally, the solder balls 24 serving as input / output terminals are fused to the ball lands 22 exposed through the bottom surface of the substrate 10, thereby completing the semiconductor package for stacking as shown in FIG. 4.

이렇게 완성된 반도체 패키지를 첨부한 도 5에서 보듯이, 메모리 칩의 용량을 증대시키기 위해 상하로 적층시킬 수 있으며, 상부 패키지의 솔더볼(24)을 하부 패키지의 관통 몰드 비아(20)와 연결되도록 함으로써, 상부 패키지 및 하부 패키지가 전기적 신호 교환 가능하게 적층된다.As shown in FIG. 5 to which the completed semiconductor package is attached, the semiconductor package may be stacked up and down to increase the capacity of the memory chip, and the solder balls 24 of the upper package may be connected to the through mold vias 20 of the lower package. The upper package and the lower package are stacked to be in electrical signal exchange.

또한, 첨부한 도 6에서 보듯이, 메모리 칩의 용량을 보다 증대시키기 위하여 4개 이상의 반도체 패키지를 동일한 방식으로 적층시킬 수 있다.In addition, as shown in FIG. 6, four or more semiconductor packages may be stacked in the same manner in order to further increase the capacity of the memory chip.

그러나, 종래의 반도체 패키지는 각 반도체 패키지마다 한 개의 기판이 필수적으로 포함됨에 따라, 그 적층 두께가 과도하게 증가하는 단점이 있고, 그에 따라 제조 비용이 많이 드는 단점이 있었다.
However, in the conventional semiconductor package, since one substrate is essentially included in each semiconductor package, the stack thickness thereof is excessively increased, and thus, the manufacturing cost is high.

본 발명은 상기와 같은 점을 감안하여 안출한 것으로서, 단일 기판의 양면에 여러개의 반도체 칩을 적층 부착하고, 각 칩을 기판과 와이어 본딩한 후, 기판의 양면을 모두 몰딩 컴파운드 수지로 몰딩함으로써, 반도체 칩의 실장 갯수를 늘려 메모리 칩의 용량을 크게 증대시킬 수 있고, 기존 적층된 패키지 대비 그 두께를 현격하게 줄일 수 있도록 한 적층형 반도체 패키지 및 그 제조 방법을 제공하는데 그 목적이 있다.
The present invention has been made in view of the above, by stacking a plurality of semiconductor chips on both sides of a single substrate, wire bonding each chip with the substrate, and then molding both sides of the substrate with a molding compound resin, It is an object of the present invention to provide a stacked semiconductor package and a method of manufacturing the same, which can greatly increase the capacity of the memory chip by increasing the mounting number of the semiconductor chip and significantly reduce the thickness of the conventional stacked package.

상기한 목적을 달성하기 위한 본 발명의 일 구현예는: 기판의 일면에 구획된 칩부착 영역에 적층 부착되는 다수개의 제1반도체 칩들과; 각 제1반도체 칩들과 기판의 일면에 노출된 전도성패턴 간에 연결되는 제1 도전성 와이어와; 기판의 타면에 구획된 칩부착 영역에 적층 부착되는 다수개의 제2반도체 칩들과; 각 제2반도체 칩들과 기판의 타면에 노출된 전도성패턴 간에 연결되는 제2도전성 와이어와; 기판의 일면에 몰딩되어, 제1반도체 칩 및 제1와이어들을 감싸는 제1몰딩 컴파운드 수지와; 기판의 일면에 형성된 전도성패턴과 도전 가능하도록 제1몰딩 컴파운드 수지에 형성되는 제1관통 몰드 비아와; 기판의 타면에 몰딩되어, 제2반도체 칩과 제2와이어들을 감싸는 제2몰딩 컴파운드 수지와; 기판의 타면에 형성된 전도성패턴과 도전 가능하도록 제2몰딩 컴파운드 수지에 형성되는 제2관통 몰드 비아; 를 포함하여 구성된 것을 특징으로 하는 적층형 반도체 패키지를 제공한다.One embodiment of the present invention for achieving the above object comprises: a plurality of first semiconductor chips stacked on the chip attachment region partitioned on one surface of the substrate; A first conductive wire connected between each of the first semiconductor chips and a conductive pattern exposed on one surface of the substrate; A plurality of second semiconductor chips stacked on and attached to the chip attaching region partitioned on the other surface of the substrate; A second conductive wire connected between each of the second semiconductor chips and a conductive pattern exposed on the other surface of the substrate; A first molding compound resin molded on one surface of the substrate and surrounding the first semiconductor chip and the first wires; A first through mold via formed in the first molding compound resin to be conductive with the conductive pattern formed on one surface of the substrate; A second molding compound resin molded on the other surface of the substrate and surrounding the second semiconductor chip and the second wires; A second through mold via formed in the second molding compound resin to be conductive with a conductive pattern formed on the other surface of the substrate; It provides a stacked semiconductor package, characterized in that configured to include.

상기한 목적을 달성하기 위한 본 발명의 다른 구현예는: 기판의 일면에 구획된 칩부착 영역에 적층 부착되는 다수개의 제1반도체 칩들과; 각 제1반도체 칩들과 기판의 일면에 노출된 전도성패턴 간에 연결되는 제1도전성 와이어와; 기판의 타면에 구획된 칩부착 영역에 적층 부착되는 다수개의 제2반도체 칩들과; 각 제2반도체 칩들과 기판의 타면에 노출된 전도성패턴 간에 연결되는 제2도전성 와이어와; 기판의 일면에 몰딩되어, 제1반도체 칩 및 제1도전성 와이어들을 감싸는 제1몰딩 컴파운드 수지와; 기판의 일면에 형성된 전도성패턴과 도전 가능하도록 제1몰딩 컴파운드 수지에 형성되는 제1관통 몰드 비아와; 기판의 타면에 몰딩되어, 제2반도체 칩과 제2도전성 와이어들을 감싸는 제2몰딩 컴파운드 수지와; 기판의 타면에 형성된 전도성패턴과 도전 가능하도록 제2몰딩 컴파운드 수지에 형성되는 제2관통 몰드 비아; 를 포함하여 구성된 것을 특징으로 하는 적층형 반도체 패키지 제조 방법을 제공한다.
Another embodiment of the present invention for achieving the above object comprises: a plurality of first semiconductor chips stacked on the chip attachment region partitioned on one surface of the substrate; A first conductive wire connected between each of the first semiconductor chips and a conductive pattern exposed on one surface of the substrate; A plurality of second semiconductor chips stacked on and attached to the chip attaching region partitioned on the other surface of the substrate; A second conductive wire connected between each of the second semiconductor chips and a conductive pattern exposed on the other surface of the substrate; A first molding compound resin molded on one surface of the substrate and surrounding the first semiconductor chip and the first conductive wires; A first through mold via formed in the first molding compound resin to be conductive with the conductive pattern formed on one surface of the substrate; A second molding compound resin molded on the other surface of the substrate and surrounding the second semiconductor chip and the second conductive wires; A second through mold via formed in the second molding compound resin to be conductive with a conductive pattern formed on the other surface of the substrate; It provides a laminated semiconductor package manufacturing method characterized in that it comprises a.

상기한 과제 해결 수단을 통하여, 본 발명은 다음과 같은 효과를 제공한다.Through the above-mentioned means for solving the problems, the present invention provides the following effects.

본 발명에 따르면, 하나의 기판의 일면에 여러개의 반도체 칩을 적층 부착하는 동시에 각 칩과 기판을 와이어로 본딩하여 몰딩하고, 기판의 타면에도 여러개의 반도체 칩을 적층 부착하는 동시에 각 칩과 기판을 와이어로 본딩하여 몰딩함으로써, 반도체 칩의 실장 갯수를 늘려 메모리 칩의 용량을 크게 증대시킬 수 있을 뿐만 아니라, 기존 적층된 패키지 대비 그 두께를 현격하게 줄일 수 있으므로, 경박단소화를 실현할 수 있다.According to the present invention, a plurality of semiconductor chips are laminated and attached to one surface of one substrate, and each chip and the substrate are bonded and molded by wires, and the plurality of semiconductor chips are laminated and attached to the other surface of the substrate, respectively. By bonding with wires and molding, not only can the mounting number of semiconductor chips be increased, but also the capacity of the memory chips can be greatly increased, and the thickness of the semiconductor chips can be significantly reduced compared to the existing stacked packages, thereby making it possible to realize light and small size reduction.

특히, 기존에 두 개의 기판을 이용하여 적층된 패키지 대비, 하나의 기판만을 이용하여 동수의 칩을 적층할 수 있으므로, 고가의 기판 사용을 감소시켜 제조 원가를 절감할 수 있다.
In particular, since the same number of chips can be stacked using only one substrate, compared to a package stacked using two substrates, it is possible to reduce manufacturing cost by reducing the use of expensive substrates.

도 1은 본 발명에 따른 적층형 반도체 패키지를 나타내는 단면도,
도 2는 도 2의 반도체 패키지를 상하로 적층시킨 상태를 나타내는 단면도,
도 3은 본 발명의 패키지와 기존의 패키지 간의 높이 차를 비교한 단면도,
도 4는 본 발명에 따른 적층형 반도체 패키지의 다른 예를 나타낸 단면도,
도 5는 종래의 반도체 패키지를 나타내는 단면도,
도 6은 종래의 반도체 패키지를 상하로 적층시킨 상태를 나타내는 단면도,
도 7은 종래의 반도체 패키지를 4개 적층시킨 것을 보여주는 단면도.1 is a cross-sectional view showing a stacked semiconductor package according to the present invention;
2 is a cross-sectional view illustrating a state in which the semiconductor package of FIG. 2 is stacked up and down;
3 is a cross-sectional view comparing the height difference between the package of the present invention and the existing package,
4 is a cross-sectional view showing another example of a stacked semiconductor package according to the present invention;
5 is a cross-sectional view showing a conventional semiconductor package;
6 is a cross-sectional view showing a state in which a conventional semiconductor package is stacked up and down;
7 is a cross-sectional view showing a stack of four conventional semiconductor packages.

이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명은 하나의 기판의 일면에 여러개의 반도체 칩을 적층 부착하는 동시에 기판의 타면에도 여러개의 반도체 칩을 적층 부착한 후, 양면 몰딩을 실시함으로써, 반도체 칩의 실장 갯수를 늘려 메모리 칩의 용량을 크게 증대시킬 수 있을 뿐만 아니라, 기존 적층된 패키지 대비 그 두께를 현격하게 줄일 수 있도록 한 점에 주안점이 있다.According to the present invention, a plurality of semiconductor chips are laminated on one surface of one substrate, and a plurality of semiconductor chips are laminated on the other surface of the substrate, and then double-sided molding is performed to increase the number of mounting of the semiconductor chips to increase the capacity of the memory chip. Not only can it be greatly increased, but the point is to significantly reduce the thickness compared to the existing laminated package.

도 1에서 보듯이, 먼저 기판(10)의 일면에 구획된 칩부착 영역에 다수개의 제1반도체 칩(12a)들이 교번으로 적층되며 부착된다.As shown in FIG. 1, first, a plurality of first semiconductor chips 12a are alternately stacked and attached to a chip attaching region partitioned on one surface of a substrate 10.

즉, 다수개의 제1반도체 칩(12a)들을 적층 부착할 때, 각 제1반도체 칩(12a)의 본딩패드에 도전성 와이어의 일끝단이 1차로 본딩되면서 위쪽으로 루프 하이트(loop hight)를 형성할 때, 그 공간을 확보할 수 있도록 각 제1반도체 칩(12a)의 테두리 부분이 서로 엇갈리게 배열되도록 한다.That is, when the plurality of first semiconductor chips 12a are stacked and attached, one end of the conductive wire may be primarily bonded to the bonding pads of the first semiconductor chips 12a to form a loop height. At this time, the edge portions of each of the first semiconductor chips 12a are arranged to be staggered with each other so as to secure the space.

이어서, 각 제1반도체 칩(12a)들의 본딩패드와 기판(10)의 일면에 노출된 전도성패턴 간을 제1도전성 와이어(16a)로 연결하는 와이어 본딩 공정이 진행된다.Subsequently, a wire bonding process of connecting the bonding pads of the first semiconductor chips 12a and the conductive patterns exposed on one surface of the substrate 10 with the first conductive wire 16a is performed.

보다 상세하게는, 상기와 같이 와이어 본딩 공간이 확보된 각 제1반도체 칩(12a)의 본딩패드에 제1도전성 와이어(16a)의 일끝단이 1차 본딩(볼 본딩)되는 동시에 기판(10)의 전도성패턴에 제1도전성 와이어(16a)의 타끝단이 2차 본딩(스티치 본딩)되어진다.More specifically, one end of the first conductive wire 16a is first bonded (ball bonded) to the bonding pad of each of the first semiconductor chips 12a in which the wire bonding space is secured as described above. The other end of the first conductive wire 16a is subjected to secondary bonding (stitch bonding) on the conductive pattern of.

다음으로, 상기 제1반도체 칩(12a)들과 제1도전성 와이어(16a) 등을 외부로부터 보호하기 위하여 기판(10)의 일면을 제1몰딩 컴파운드 수지(18a)로 몰딩하여,제1반도체 칩(12a)과 제1도전성 와이어(16a)가 감싸여지는 상태가 되도록 한다.Next, in order to protect the first semiconductor chips 12a and the first conductive wire 16a from the outside, one surface of the substrate 10 is molded with a first molding compound resin 18a to form a first semiconductor chip. 12a and the first conductive wire 16a are wrapped.

이어서, 상기 제1몰딩 컴파운드 수지(18a)의 상면에서 그 테두리 부분에 레이저 가공을 이용하여 홈을 파내되, 기판(10)의 상면 테두리 부분에 노출된 전도성패턴이 노출될 때까지 파낸 다음, 그 내부에 전도성 충진재를 충진시켜서 제1관통 몰드 비아(20a)를 형성하게 된다.Subsequently, a groove is excavated from the upper surface of the first molding compound resin 18a by using laser processing, and then the trench is excavated until the conductive pattern exposed on the upper edge of the substrate 10 is exposed. Filling the conductive filler therein to form a first through-mold via 20a.

이렇게 기판(10)의 일면에 제1반도체 칩(12a)들을 적층 부착하고, 제1도전성 와이어(16a)를 연결하며, 또한 제1몰딩 컴파운드 수지(18a)를 몰딩하고, 제1관통 몰드 비아(20a)를 형성한 다음, 기판(10)을 뒤집어서 기판(10)의 타면에 제2반도체 칩(12b)들을 적층 부착하고, 제2도전성 와이어(16b)를 연결하며, 또한 제2몰딩 컴파운드 수지(18b)를 몰딩하고, 제2관통 몰드 비아(20b)를 형성하는 공정이 동일하게 순차 진행된다.The first semiconductor chips 12a are laminated and attached to one surface of the substrate 10, the first conductive wires 16a are connected to each other, the first molding compound resin 18a is molded, and the first through mold via ( 20 a), the substrate 10 is turned upside down, and the second semiconductor chips 12 b are laminated and attached to the other surface of the substrate 10, the second conductive wires 16 b are connected to each other, and the second molding compound resin ( The process of molding 18b) and forming the second through mold via 20b proceeds in the same manner.

즉, 기판(10)의 타면에 구획된 칩부착 영역에 다수개의 제2반도체 칩(12b)들을 교번 배열로 적층 부착하는 단계와, 각 제2반도체 칩(12b)의 본딩패드와 기판(10)의 타면에 형성된 전도성패턴 간을 제2도전성 와이어(16b)로 연결하는 단계와, 제2반도체 칩(12b)과 제2도전성 와이어(16b)들을 감싸도록 기판(10)의 타면을 제2몰딩 컴파운드 수지(18b)로 몰딩하는 단계와, 기판(10)의 타면 테두리에 형성된 전도성패턴과 도전되도록 제2몰딩 컴파운드 수지(18b)에 제2관통 몰드 비아(20b)를 형성하는 단계가 순차적으로 진행됨으로써, 도 1에 도시된 바와 같은 본 발명의 반도체 패키지가 완성된다.That is, stacking and attaching a plurality of second semiconductor chips 12b in an alternating arrangement to a chip attaching region partitioned on the other surface of the substrate 10, and bonding pads and substrates 10 of the respective second semiconductor chips 12b to each other. Connecting the conductive patterns formed on the other surface of the second conductive wire 16b to the second conductive wire 16b, and covering the second surface of the substrate 10 with the second molding compound to surround the second semiconductor chip 12b and the second conductive wire 16b. Molding with the resin 18b and forming the second through mold via 20b in the second molding compound resin 18b in order to be conductive with the conductive pattern formed at the edge of the other surface of the substrate 10. The semiconductor package of the present invention as shown in FIG. 1 is completed.

본 발명에 따르면, 상기와 같은 제조된 본 발명의 반도체 패키지를 상하로 2개 또는 그 이상 적층시킬 수 있다.According to the present invention, two or more of the semiconductor packages of the present invention manufactured as described above can be stacked up and down.

도 2에 보듯이, 하나의 반도체 패키지에 형성된 제1관통 몰드 비아(20a)와, 적층 대상의 다른 반도체 패키지에 형성된 제2관통 몰드 비아(20b)를 전도성 솔더와 같은 도전수단(26)을 매개로 연결시키며 적층시키거나, 또는 하나의 반도체 패키지에 형성된 제2관통 몰드 비아(20b)와, 적층 대상의 다른 반도체 패키지에 형성된 제1관통 몰드 비아(20b)를 전도성 솔더와 같은 도전수단(26)을 매개로 연결시키며 적층시킴으로써, 2개 이상의 패키지가 상하로 적층될 수 있다.As shown in FIG. 2, the first through mold via 20a formed in one semiconductor package and the second through mold via 20b formed in another semiconductor package to be stacked are mediated through conductive means 26 such as conductive solder. A second through-mold via 20b formed in one semiconductor package or a first through-mold via 20b formed in another semiconductor package to be stacked, and a conductive means 26 such as conductive solder. By stacking by connecting through two, two or more packages can be stacked up and down.

본 발명에 따른 반도체 패키지에 적용되는 각 반도체 칩들은 반도체를 이용하여 정보를 저장하는 솔리드 스테이트 드라이브(Solid-state Drive)에 사용되는 메모리 칩으로 채택된 것으로서, 상기와 같이 기판(10)을 중심으로 그 양면에 여러개의 칩들을 적층 부착하는 동시에 패키지 자체를 더 적층함에 따라 메모리 칩의 용량을 크게 증대시킬 수 있다.Each of the semiconductor chips applied to the semiconductor package according to the present invention is adopted as a memory chip used in a solid-state drive that stores information using a semiconductor. By stacking multiple chips on both sides and stacking the package itself, the capacity of the memory chip can be greatly increased.

특히, 첨부한 도 3에서 보는 바와 같이 기존의 반도체 패키지(적층 후)와 본 발명의 반도체 패키지(적층 전)를 비교해 보면, 2개 이상의 기판을 이용하여 여러개의 칩들을 각각 적층 부착시킨 기존의 반도체 패키지에 비하여, 하나의 기판을 이용하여 그 양면에 기존과 동일한 갯수의 칩들을 적층시킨 본 발명의 반도체 패키지 두께가 보다 얇게 제작되어 경박단소화를 실현할 수 있다.In particular, when comparing the semiconductor package (after lamination) and the semiconductor package (before lamination) of the present invention, as shown in the accompanying Figure 3, the conventional semiconductor is laminated with a plurality of chips using two or more substrates, respectively Compared to the package, the thickness of the semiconductor package of the present invention in which the same number of chips are stacked on both surfaces thereof by using one substrate is manufactured to be thinner, thereby realizing light and small size reduction.

또한, 본 발명의 반도체 패키지는 하나의 기판만을 사용함에 따라, 고가의 기판 사용을 줄일 수 있고, 그에 따라 제조 원가를 절감할 수 있다.In addition, since the semiconductor package of the present invention uses only one substrate, it is possible to reduce the use of expensive substrates, thereby reducing the manufacturing cost.

한편, 첨부한 도 4에 도시된 바와 같이 반도체 칩을 적층할 때, 와이어 본딩이 아닌 관통 실리콘 비아(28, TSV: Through Silicon Via)를 이용하여 전기적 신호 교환 가능하게 적층하거나, 플립칩(30, Flip Chip) 또는 컵(Cup)을 이용하여 적층하여, 상기와 같은 본 발명의 적층형 패키지를 구성할 수 있음은 물론이다.
Meanwhile, as shown in FIG. 4, when the semiconductor chips are stacked, the semiconductor chips may be stacked so as to be electrically exchanged using a through silicon via (TSV) 28 instead of wire bonding, or flip chips 30 may be used. By stacking using a Flip Chip) or a cup (Cup), it is a matter of course that the laminated package of the present invention can be configured as described above.

10 : 기판 12 : 반도체 칩
12a : 제1반도체 칩 12b : 제2반도체 칩
16 : 도전성 와이어 16a : 제1도전성 와이어
16b : 제2도전성 와이어 18 : 몰딩 컴파운드 수지
18a : 제1몰딩 컴파운드 수지 18b : 제2몰딩 컴파운드 수지
20 : 관통 몰드 비아 20a : 제1관통 몰드 비아
20b : 제2관통 몰드 비아 22 : 볼랜드
24 : 솔더볼 26 : 도전수단
28 : TSV 30 : 플립칩10 substrate 12 semiconductor chip
12a: first semiconductor chip 12b: second semiconductor chip
16 conductive wire 16a first conductive wire
16b: second conductive wire 18: molding compound resin
18a: first molding compound resin 18b: second molding compound resin
20: through mold via 20a: first through mold via
20b: second through mold via 22: Borland
24: solder ball 26: conductive means
28: TSV 30: flip chip

Claims (7)

기판(10)의 일면에 구획된 칩부착 영역에 적층 부착되는 다수개의 제1반도체 칩(12a)들과;
각 제1반도체 칩(12a)들과 기판(10)의 일면에 노출된 전도성패턴 간에 연결되는 제1도전성 와이어(16a)와;
기판(10)의 타면에 구획된 칩부착 영역에 적층 부착되는 다수개의 제2반도체 칩(12b)들과;
각 제2반도체 칩(12b)들과 기판(10)의 타면에 노출된 전도성패턴 간에 연결되는 제2도전성 와이어(16b)와;
기판(10)의 일면에 몰딩되어, 제1반도체 칩(12a) 및 제1도전성 와이어(16a)들을 감싸는 제1몰딩 컴파운드 수지(18a)와;
기판(10)의 일면에 형성된 전도성패턴과 도전 가능하도록 제1몰딩 컴파운드 수지(18a)에 형성되는 제1관통 몰드 비아(20a)와;
기판(10)의 타면에 몰딩되어, 제2반도체 칩(12b)과 제2도전성 와이어(16b)들을 감싸는 제2몰딩 컴파운드 수지(18b);
기판(10)의 타면에 형성된 전도성패턴과 도전 가능하도록 제2몰딩 컴파운드 수지(18b)에 형성되는 제2관통 몰드 비아(20b);
를 포함하여 구성된 것을 특징으로 하는 적층형 반도체 패키지.
A plurality of first semiconductor chips 12a stacked on and attached to the chip attaching region partitioned on one surface of the substrate 10;
A first conductive wire 16a connected between each of the first semiconductor chips 12a and a conductive pattern exposed on one surface of the substrate 10;
A plurality of second semiconductor chips 12b stacked on and attached to the chip attaching region partitioned on the other surface of the substrate 10;
A second conductive wire 16b connected between the respective second semiconductor chips 12b and the conductive pattern exposed on the other surface of the substrate 10;
A first molding compound resin 18a molded on one surface of the substrate 10 and surrounding the first semiconductor chip 12a and the first conductive wires 16a;
A first through mold via 20a formed in the first molding compound resin 18a to be conductive with a conductive pattern formed on one surface of the substrate 10;
A second molding compound resin 18b molded on the other surface of the substrate 10 and surrounding the second semiconductor chip 12b and the second conductive wire 16b;
A second through mold via 20b formed in the second molding compound resin 18b to be conductive with a conductive pattern formed on the other surface of the substrate 10;
Stacked semiconductor package, characterized in that configured to include.
청구항 1에 있어서,
상기 제1관통 몰드 비아(20a)를 적층 대상의 패키지에 형성된 제2관통 몰드 비아(20b)와 도전수단을 매개로 연결시키거나, 상기 제2관통 몰드 비아(20b)를 적층 대상의 패키지에 형성된 제1관통 몰드 비아(20b)와 도전수단(26)을 매개로 연결시켜서, 2개 이상의 패키지가 상하로 적층되도록 한 것을 특징으로 하는 적층형 반도체 패키지.
The method according to claim 1,
The first through-mold via 20a is connected to the second through-mold via 20b formed in the package to be stacked and the conductive means, or the second through-mold via 20b is formed in the package to be stacked. A laminated semiconductor package, characterized in that two or more packages are stacked up and down by connecting a first through-mold via (20b) and a conductive means (26).
청구항 2에 있어서,
상기 도전수단(26)은 전도성 솔더인 것을 특징으로 하는 적층형 반도체 패키지.
The method according to claim 2,
The conductive means 26 is a laminated semiconductor package, characterized in that the conductive solder.
청구항 1에 있어서,
상기 제1 및 제2반도체 칩(12a,12b)을 솔리드 스테이트 드라이브에 사용되는 메모리 칩 인 것을 특징으로 하는 적층형 반도체 패키지.
The method according to claim 1,
And the first and second semiconductor chips (12a, 12b) are memory chips used in a solid state drive.
기판(10)의 일면에 구획된 칩부착 영역에 다수개의 제1반도체 칩(12a)들을 차례로 적층 부착하는 단계와;
각 제1반도체 칩(12a)의 본딩패드와 기판(10)의 일면에 형성된 전도성패턴 간을 제1도전성 와이어(16a)로 연결하는 단계와;
제1반도체 칩(12a) 및 제1도전성 와이어(16a)들을 감싸도록 기판(10)의 일면을 제1몰딩 컴파운드 수지(18a)로 몰딩하는 단계와;
기판(10)의 일면에 형성된 전도성패턴과 도전되는 제1관통 몰드 비아(20a)를 제1몰딩 컴파운드 수지(18a)에 형성하는 단계와;
상기 기판(10)을 뒤집은 후, 기판(10)의 타면에 구획된 칩부착 영역에 다수개의 제2반도체 칩(12b)들을 차례로 적층 부착하는 단계와;
각 제2반도체 칩(12b)의 본딩패드와 기판(10)의 타면에 형성된 전도성패턴 간을 제2도전성 와이어(16b)로 연결하는 단계와;
제2반도체 칩(12b)과 제2도전성 와이어(16b)들을 감싸도록 기판(10)의 타면을 제2몰딩 컴파운드 수지(18b)로 몰딩하는 단계와;
기판(10)의 타면에 형성된 전도성패턴과 도전되는 제2관통 몰드 비아(20b)를 제2몰딩 컴파운드 수지(18b)에 형성하는 단계;
로 이루어지는 것을 특징으로 하는 적층형 반도체 패키지 제조 방법.
Stacking and attaching a plurality of first semiconductor chips 12a sequentially to a chip attaching region partitioned on one surface of the substrate 10;
Connecting the bonding pads of each of the first semiconductor chips 12a and the conductive patterns formed on one surface of the substrate 10 with the first conductive wires 16a;
Molding one surface of the substrate 10 with the first molding compound resin 18a to surround the first semiconductor chip 12a and the first conductive wire 16a;
Forming a first through mold via (20a) in the first molding compound resin (18a) that is conductive with the conductive pattern formed on one surface of the substrate (10);
Inverting and then laminating the plurality of second semiconductor chips (12b) on the chip attaching region partitioned on the other surface of the substrate (10);
Connecting the bonding pads of the second semiconductor chips 12b and the conductive patterns formed on the other surface of the substrate 10 with the second conductive wires 16b;
Molding the other surface of the substrate 10 with the second molding compound resin 18b to surround the second semiconductor chip 12b and the second conductive wire 16b;
Forming a second through mold via (20b) in the second molding compound resin (18b) that is conductive with the conductive pattern formed on the other surface of the substrate (10);
Method for manufacturing a laminated semiconductor package, characterized in that consisting of.
청구항 5에 있어서,
상기 제1관통 몰드 비아(20a)를 적층 대상의 패키지에 형성된 제2관통 몰드 비아(20b)와 도전수단을 매개로 연결시키거나, 상기 제2관통 몰드 비아(20b)를 적층 대상의 패키지에 형성된 제1관통 몰드 비아(20b)와 도전수단(26)을 매개로 연결시켜서, 2개 이상의 패키지를 상하로 적층시키는 단계를 더 포함하는 것을 특징으로 하는 적층형 반도체 패키지 제조 방법.
The method according to claim 5,
The first through-mold via 20a is connected to the second through-mold via 20b formed in the package to be stacked and the conductive means, or the second through-mold via 20b is formed in the package to be stacked. Stacking two or more packages up and down by connecting the first through mold via (20b) and the conductive means (26) as a medium.
청구항 5에 있어서,
상기 제1반도체 칩(12a)들과, 제2반도체 칩(12b)들은 적층 부착할 때, 그 테두리 부분이 서로 엇갈리게 배열되도록 한 것을 특징으로 하는 적층형 반도체 패키지 제조 방법.The method according to claim 5,
The first semiconductor chip (12a) and the second semiconductor chip (12b) when the stack is attached, the edge portion of the stacking semiconductor package manufacturing method characterized in that the arrangement is staggered with each other.
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