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CN109004029B - GaN-based MOS-HEMT device with metal oxide/silicon dioxide stacked gate and preparation method thereof - Google Patents

GaN-based MOS-HEMT device with metal oxide/silicon dioxide stacked gate and preparation method thereof Download PDF

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CN109004029B
CN109004029B CN201810783099.5A CN201810783099A CN109004029B CN 109004029 B CN109004029 B CN 109004029B CN 201810783099 A CN201810783099 A CN 201810783099A CN 109004029 B CN109004029 B CN 109004029B
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dielectric layer
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gate dielectric
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CN109004029A (en
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王洪
陈迪涛
周泉斌
耿魁伟
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South China University of Technology SCUT
Zhongshan Institute of Modern Industrial Technology of South China University of Technology
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South China University of Technology SCUT
Zhongshan Institute of Modern Industrial Technology of South China University of Technology
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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Abstract

The invention discloses a GaN-based MOS-HEMT device with a metal oxide/silicon dioxide stacked gate and a preparation method thereof; the device comprises an AlGaN/GaN heterojunction epitaxial layer, a first gate dielectric layer, a second gate dielectric layer, a gate electrode and a source electrode and a drain electrode; the first gate dielectric layer is SiO covered on the AlGaN/GaN heterojunction epitaxial layer 2 The thickness of the thin film and the first gate dielectric layer is 5-15nm; the second gate dielectric layer is a metal oxide film covered on the first gate dielectric layer, and the thickness of the second gate dielectric layer is 5-15nm; the invention adopts metal oxide/SiO 2 The damage of magnetron sputtering deposition high dielectric constant oxide medium to epitaxy is reduced, so that the GaN-based HEMT device is suitable for preparation; at the same time make up for SiO 2 The defect of low dielectric constant improves the overall gate control capability of the device and effectively reduces the gate leakage.

Description

GaN-based MOS-HEMT device with metal oxide/silicon dioxide stacked gate and preparation method thereof
Technical Field
The invention relates to a MOS-HEMT device, in particular to a GaN-based MOS-HEMT device with a metal oxide/silicon dioxide stacked gate and a preparation method thereof, and the GaN-based MOS-HEMT device can be used in the fields of power electronics, microwave communication and the like, and belongs to the technical field of semiconductors.
Background
With the development of modern weaponry and aerospace, nuclear energy, communication technology, automotive electronics, and switching power supplies, higher demands are being placed on semiconductor performance. GaN and GaN-based materials, as a representative of third generation wide bandgap semiconductor materials, have a large bandgap (3.4 eV) and a high electron saturation rate (2×10) 7 cm/s), high breakdown field strength,high heat conductivity, corrosion resistance and the like, and is considered as an excellent material for high-voltage high-frequency high-power electronic devices. In addition, gaN can form a modulation doped AlGaN/GaN heterojunction structure with AlGaN, and the structure can form a two-dimensional electron gas with high electron concentration and high electron mobility at room temperature, so that an AlGaN/GaN High Electron Mobility Transistor (HEMT) is one of the most important device types in the gallium nitride field.
Due to the defects of AlGaN/GaN crystal epitaxial surface defects, metal/semiconductor Schottky contact quality and the like, the HEMT device with the traditional Schottky gate structure has the defects of serious gate leakage, small gate working voltage swing and the like, and the performance advantages of the GaN-based HEMT device are seriously limited. To cope with this problem, a method of forming a MOS structure by interposing an oxide dielectric layer between a gate electrode and an AlGaN barrier layer is currently generally employed.
The preparation method of the gate dielectric layer mainly comprises PECVD (plasma enhanced chemical vapor deposition), LPCVD (low pressure chemical vapor deposition), ALD (atomic layer deposition), PVD (physical deposition) and other methods, and the methods have advantages and disadvantages. ALD deposited thin films are high in quality, but are mostly used for experimental experiments, are not compatible with the traditional semiconductor process, and are slow in deposition speed and difficult in mass production; PECVD/LPCVD deposited silicon nitride and silicon dioxide have inferior gate control capability as compared with high dielectric constant dielectric structures due to low dielectric constants of the materials themselves; PVD is capable of depositing high dielectric constant dielectrics, but has physical damage to the epitaxy, resulting in increased epitaxial surface defects and degraded device current. Based on the above situation, how to realize the rapid and low-cost preparation of the high-dielectric-constant gate dielectric on the premise of being compatible with the traditional silicon MOS process is a problem to be solved urgently for GaN-based MOS-HEMT devices.
Disclosure of Invention
The invention aims to overcome the defects of the gate dielectric preparation technology of the existing GaN-based MOS-HEMT device, and provides the GaN-based MOS-HEMT device with the metal oxide/silicon dioxide stacked gate and the preparation method thereof from the angles of a gate dielectric structure and a preparation process, so that the gate leakage current of the device can be effectively reduced, the gate control capability can be improved, and the GaN-based MOS-HEMT device is suitable for large-scale production.
In order to achieve the above purpose, the present invention provides the following technical solutions:
the GaN-based MOS-HEMT device with the metal oxide/silicon dioxide stacked gate comprises an AlGaN/GaN heterojunction epitaxial layer, a first gate dielectric layer, a second gate dielectric layer, a gate electrode and a source electrode and a drain electrode; the AlGaN/GaN heterojunction epitaxial layer comprises a substrate, a nitride nucleation layer, a nitride buffer layer, a GaN channel layer and an AlGaN barrier layer from bottom to top;
the first gate dielectric layer is SiO covered on the AlGaN/GaN heterojunction epitaxial layer 2 The thickness of the thin film and the first gate dielectric layer is 5-15nm;
the second gate dielectric layer is a metal oxide film covered on the first gate dielectric layer, and the metal oxide is Al 2 O 3 、Ga 2 O 3 、HfO 2 Or TiO x The thickness of the second gate dielectric layer is 5-15nm;
the first gate dielectric layer, the second gate dielectric layer and the AlGaN/GaN heterojunction epitaxial layer form an MOS structure;
the source electrode and the drain electrode are arranged on the AlGaN potential barrier layer at intervals; and a gate electrode is arranged between the source electrode and the drain electrode and is arranged on the second gate dielectric layer.
To further achieve the object of the present invention, it is preferable that the gate electrode and the source-drain electrode have a thickness of 100 to 300nm.
Preferably, the cross sections of the gate electrode and the source and drain electrodes are circular.
Preferably, the cross section of the gate electrode is rectangular, the length of the gate electrode is 50-2000 μm, and the width of the gate electrode is 2-10 μm.
Preferably, the thicknesses of the substrate, the nitride nucleation layer, the nitride buffer layer, the GaN channel layer and the AlGaN barrier layer are respectively 0.5-2mm, 0.2-1 μm, 500-2500nm, 100-500nm and 10-30nm.
Preferably, the cross section of the substrate is circular, and the diameter is 4inch-10inch.
Preferably, said SiO 2 The film is deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) or low-pressure chemical gasPhase deposition (LPCVD deposition).
Preferably, the metal oxide film is formed by magnetron sputtering deposition.
The method for manufacturing the GaN-based MOS-HEMT device with the metal oxide/silicon dioxide stacked gate comprises the following steps:
1) And (3) epitaxial growth: sequentially epitaxially growing a nitride nucleation layer, a nitride buffer layer, a GaN channel layer and an AlGaN barrier layer on a substrate through metal organic vapor deposition to form an AlGaN/GaN heterojunction epitaxial layer;
2) Device isolation: defining an active region, and performing coverage protection on the active region by using photoresist; removing the AlGaN/GaN heterojunction epitaxial layer outside the active area by utilizing inductively coupled plasma etching ICP, wherein the etching depth is larger than the thicknesses of the AlGaN barrier layer and the GaN channel layer;
3) Source-drain electrode preparation: defining the metal positions and patterns of the source and drain electrodes on the active area which is isolated in the step 2) through a negative photoresist photoetching process, and depositing a source and drain electrode film through electron beam evaporation or magnetron sputtering; annealing in nitrogen atmosphere at a temperature above 800 ℃ to enable the source electrode and the drain electrode to form ohmic contact with the AlGaN barrier layer;
4) Depositing a first gate dielectric layer: deposition of SiO on AlGaN/GaN heterojunction epitaxial layers 2 The thin film is used for forming a first gate dielectric layer to cover, and the thickness of the first gate dielectric layer is 5-15nm;
5) And (3) depositing a second gate dielectric layer: depositing a metal oxide film on the first gate dielectric layer by magnetron sputtering;
6) Medium removal: removing the first dielectric layer and the second dielectric layer of the source drain electrode region to expose the source drain electrode metal; firstly protecting a medium except a source electrode and a drain electrode by photoresist, and then removing the medium;
7) Preparing a gate electrode: a gate electrode is prepared between the source and drain electrode metals by electron beam evaporation or magnetron sputtering.
The first metal layer is made of high work function material, such as nickel metal, and the second metal layer may be gold Au, titanium nitride TiN or other metal with high conductivity and stable chemical property.
Preferably, the source-drain electrode film in the step 3) is composed of a Ti/Al metal system multi-layer metal, and source-drain electrode metal lines are formed through a stripping process; the Ti/Al metal system is Ti/Al/Ni/Au or Ti/Al/Ni/TiN;
the method for removing the medium in the step 6) is wet etching or dry etching; wherein the solution adopted by wet etching is hydrofluoric acid or phosphoric acid, etc.; the dry etching is inductively coupled plasma etching or reactive ion etching;
the gate electrode in the step 7) is composed of two layers of metals, wherein the first layer of metal is nickel metal, and the second layer of metal is Au or TiN.
The invention forms a source electrode and a drain electrode in an active region on a GaN epitaxial wafer; then forming a first gate dielectric layer SiO by using plasma enhanced chemical vapor deposition 2 Forming a second gate dielectric layer with high dielectric constant by using magnetron sputtering; removing the first dielectric layer and the second dielectric layer above the source drain electrode metal by dry etching; a gate electrode is formed between the source and drain electrodes.
The first gate dielectric layer is SiO deposited by plasma enhanced chemical vapor deposition PECVD or low pressure chemical vapor deposition LPCVD 2 Film of SiO 2 The film has good compactness, small movable charge density in the dielectric layer, small leakage current, high breakdown field strength and high-quality interface with AlGaN; the method is used for reducing the gate leakage current and reducing the damage of the active region by the next magnetron sputtering process. The second gate dielectric layer is a metal oxide film with higher dielectric constant deposited by magnetron sputtering, and the metal oxide with higher dielectric constant can be Al 2 O 3 、Ga 2 O 3 、HfO 2 、TiO x One of them. The thin film has good compactness, high breakdown field strength, high relative dielectric constant and SiO 2 Has a high quality interface; meanwhile, the surface roughness of the two layers of media is smaller; to further reduce leakage current while maintaining gate control capability.
Compared with the prior art, the invention has the following advantages and beneficial effects:
1) First layer SiO of the invention 2 Protection of active region, decreaseDamage to epitaxy by a subsequent magnetron sputtering process; the second layer of high-dielectric-constant medium further improves the leakage characteristic of the medium layer and compensates the first layer of SiO 2 The defect of low relative dielectric constant improves the control capability of the grid electrode to the channel, and further improves the dynamic electric characteristics of the device.
2) The MOS structure prepared by the lamination process can be used in large-scale production, so that the gate leakage of a device is reduced, and the breakdown characteristic and dynamic electric characteristic of the device are improved.
3) The invention adopts metal oxide/SiO 2 The damage of magnetron sputtering deposition high dielectric constant oxide medium to epitaxy is reduced, so that the GaN-based HEMT device is suitable for preparation; the overall grid control capability of the device is improved, and the grid leakage is effectively reduced.
4) The process used by the method is compatible with the SiMOS process, and the method is simple in process and strong in operability.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a GaN-based MOS-HEMT device with a metal oxide/silicon dioxide stack gate according to the present invention.
Fig. 2-8 are schematic diagrams illustrating a process for forming a GaN-based MOS-HEMT device with a metal oxide/silicon dioxide stack according to the present invention.
Fig. 9 is a gate-source IV curve of a GaN-based MOS-HEMT device with a metal oxide/silicon dioxide stack gate of embodiment 1;
fig. 10 is an off-state breakdown curve of a GaN-based MOS-HEMT device with a metal oxide/silicon dioxide stack of embodiment 1;
fig. 11 is a transfer curve of a GaN-based MOS-HEMT device with a metal oxide/silicon dioxide stack of embodiment 1.
The figure shows: an AlGaN/GaN heterojunction epitaxial layer 1, an AlGaN barrier layer 01, a GaN channel layer 02, a nitride buffer layer 03, a nitride nucleation layer 04, a substrate 05, a source-drain electrode 2, a first gate dielectric layer 3, a second gate dielectric layer 4 and a gate electrode 5.
Detailed Description
The following description of the embodiments of the invention is provided with reference to the accompanying drawings and examples, but the embodiments and protection of the invention are not limited thereto, and it should be noted that the following detailed description of the process or process parameters will be presented to those skilled in the art with reference to the prior art.
As shown in fig. 8, the GaN-based MOS-HEMT device with metal oxide/silicon dioxide stacked gate includes an AlGaN/GaN heterojunction epitaxial layer 1, a first gate dielectric layer 3, a second gate dielectric layer 4, a gate electrode 5, and a source-drain electrode 2. The AlGaN/GaN heterojunction epitaxial layer 1 comprises a substrate 05, a nitride nucleation layer 04, a nitride buffer layer 03, a GaN channel layer 02 and an AlGaN barrier layer 01 from bottom to top; the substrate 05 is preferably circular, and the diameter is preferably 4inch-10inch; the thicknesses of the substrate 05, the nitride nucleation layer 04, the nitride buffer layer 03, the GaN channel layer 02 and the AlGaN barrier layer 01 are respectively 0.5-2mm, 0.2-1 mu m, 500-2500nm, 100-500nm and 10-30nm.
The first gate dielectric layer 3 is covered on the AlGaN/GaN heterojunction epitaxial layer 1, and the thickness is 5-15nm; the second gate dielectric layer 4 covers the first gate dielectric layer 3; the thickness of the second gate dielectric layer 4 is 5-15nm, and the first gate dielectric layer 3, the second gate dielectric layer 4 and the AlGaN/GaN heterojunction epitaxial layer 1 form a MOS structure; the source and drain electrodes comprise source electrodes and drain electrodes which are arranged on the 01 plane of the AlGaN barrier layer at intervals; a gate electrode 5 is arranged between the source electrode and the drain electrode, and the gate electrode 5 is arranged on the second gate dielectric layer 4. The thickness of both the gate electrode 5 and the source-drain electrode 2 is preferably 100-300nm.
Example 1
Referring to fig. 2-8, as shown in fig. 1, corresponding to each flow description, the method for manufacturing the GaN-based MOS-HEMT device with the metal oxide/silicon dioxide stack gate includes the following steps:
step S1: alGaN/GaN heterojunction epitaxial layer 1 is prepared. The nitride nucleation layer 04, the nitride buffer layer 03, the GaN channel layer 02, and the AlGaN barrier layer 01 are sequentially grown on the Si or SiC substrate 05 by metal organic vapor deposition (MOCVD), as shown in fig. 2. Then willAlGaN/GaN heterojunction epitaxial layer 1 is immersed in H 2 SO 4 :H 2 O 2 =6: 1 (mass ratio) for 10 minutes to remove the surface oxide layer, and then acetone and isopropanol are adopted to remove the organic matters on the AlGaN/GaN heterojunction epitaxial layer 1.
Step S2: device isolation is achieved. The active region is defined by a positive photoresist lithography process, and is rectangular with a width of 53 μm and a length of 100 μm. And (5) performing coverage protection on the active region by using photoresist. And removing the heterojunction of the GaN channel layer and the AlGaN barrier layer outside the active region by utilizing Inductively Coupled Plasma (ICP), wherein the etching depth is larger than or equal to the sum of the thicknesses of the AlGaN barrier layer and the GaN channel layer, and the isolation between devices is realized as shown in figure 3.
Step S3: source-drain electrode 2. The source and drain electrode metal is defined as a rectangle with a length of 100 μm and a width of 10 μm on the active region where isolation is realized in step S2 by a negative photoresist lithography process, and is 2 μm away from the edge of the active region. The source and drain electrode thin film is deposited by electron beam evaporation, the Ti/Al/Ni/Au is sequentially arranged from bottom to top by adopting multiple layers of metals, the thicknesses of the Ti/Al/Ni/Au are 20/100/10/100nm respectively, and the source and drain electrode is formed by a stripping process, as shown in figure 4. And (3) placing the sample in a nitrogen atmosphere, and annealing at 850 ℃ for 1min to enable the source electrode and the drain electrode to form ohmic contact with the AlGaN barrier layer.
Step S4: a first gate dielectric layer 3 is deposited. SiO is deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) on the faces of the nitride buffer layer, alGaN barrier layer and source drain electrode 2 A first gate dielectric layer 3 is formed as shown in fig. 5. The thickness is 15nm, and the deposition conditions are as follows: cavity pressure is 850mTorr, high purity N 2 O flow rate is 1000sccm, high purity N 2 400sccm SiH at 5% by volume 4 And N 2 The flow rate of the mixed gas is 100sccm, the reaction temperature is 300 ℃, and the radio frequency power is 50W. The coupon is then transferred to a magnetron sputtering chamber.
Step S4: a second gate dielectric layer 4 is deposited. A second layer of dielectric 4 is formed on the face of the first gate dielectric layer 3 by magnetron sputtering as shown in fig. 6. The layer of Al 2 O 3 The preparation conditions of (2) are as follows: alumina ceramic target with purity of 99.99% is used as target, substrate temperature is 300 ℃, sputtering gasThe bulk is Ar, the sputtering air pressure is 6mtorr, the radio frequency sputtering power is 160W, and the deposition thickness is 15nm.
Step S5: the source-drain electrode 2 is exposed. And covering the photoresist on the non-source drain electrode region by a photoetching process to protect, and using an inductively coupled plasma etching ICP process. CHF with trifluoromethane 3 And O 2 The method is a process gas, and the specific conditions are as follows: CHF and CHF 3 Flow rate is 50sccm, O 2 The flow rate was 10sccm, RF power 60W, ICP power 600W. SiO is made of 2 Dielectric layer 3 and Al 2 O 3 And etching and removing the dielectric layer 4 to expose the source and drain electrode metal. As shown in fig. 7.
Step S6: a gate electrode 5 is prepared. As shown in fig. 8, the line pattern and position of the gate electrode, which is rectangular with a length of 100 μm and a width of 3 μm, are defined by a negative photoresist lithography process, and are located between the source and drain electrodes. And sequentially depositing nickel and gold by using an electron beam evaporation process, wherein the thickness of the deposited layers of the nickel and the gold is 50nm and 150nm respectively, and reserving the gate electrode 5 above the second gate dielectric layer 4 by using a stripping process.
The device is a stacked gate dielectric MOS high electron mobility transistor based on AlGaN/GaN heterojunction, and a first gate dielectric layer SiO is formed by adopting plasma enhanced chemical vapor deposition PEDCVD 2 Then forming a second gate dielectric layer Al by magnetron sputtering 2 O 3 And realizing a stacked gate dielectric MOS structure. First gate dielectric layer SiO 2 The active region is protected, so that the damage of the subsequent magnetron sputtering process to epitaxy can be effectively reduced; the second layer of high-k dielectric further improves the leakage characteristic of the dielectric layer and compensates the SiO of the first gate dielectric layer 2 The defect of low relative dielectric constant improves the control capability of the grid electrode to the channel, and further improves the dynamic electric characteristics of the device. The MOS structure prepared by the laminated gate dielectric process is suitable for large-scale production, reduces the gate leakage of devices and improves the breakdown characteristic and dynamic electric characteristic of the devices.
DC characteristic test of the sample of example 1 with Agilent B1505, junctionThe results are shown in FIG. 9, FIG. 10, and FIG. 11, in which SiO 2 /Al 2 O 3 The sample of example 1, siN, is a sample of SiN media prepared using conventional plasma enhanced chemical vapor deposition PECVD. As shown in FIG. 9, example 1 samples the gate leakage Ig when a voltage of-5V is applied<10 ‐7 A/mm is reduced by two orders of magnitude compared with the SiN medium sample prepared by the existing plasma enhanced chemical vapor deposition PECVD. As shown in fig. 10, the example 1 sample breakdown voltage reached 530V, which is increased by approximately 330V compared to 200V for the SiN dielectric sample. As shown in FIG. 11, the sample transconductance peak of example 1 reaches 65mS/mm, which is increased by 12mS/mm compared to the SiN medium sample prepared by plasma enhanced chemical vapor deposition PECVD.
Example 2
Referring to fig. 2-8, as shown in fig. 1, corresponding to each flow description, the method for manufacturing the GaN-based MOS-HEMT device with the metal oxide/silicon dioxide stack gate includes the following steps:
step S1: alGaN/GaN heterojunction epitaxial layer 1 is prepared. The nitride nucleation layer 04, the nitride buffer layer 03, the GaN channel layer 02, and the AlGaN barrier layer 01 are sequentially grown on the Si or SiC substrate 05 by metal organic vapor deposition (MOCVD), as shown in fig. 2. Then soaking the AlGaN/GaN heterojunction epitaxial layer 1 in H 2 SO 4 :H 2 O 2 =6: 1 (mass ratio) for 10 minutes to remove the surface oxide layer, and then acetone and isopropanol are adopted to remove the organic matters on the AlGaN/GaN heterojunction epitaxial layer 1.
Step S2: device isolation is achieved. The active region was defined by a positive photoresist lithography process, and the active region was rectangular with a width of 53 μm and a length of 100 μm, and was 2 μm from the boundary of the active region. And (5) performing coverage protection on the active region by using photoresist. And removing the heterojunction of the GaN channel layer and the AlGaN barrier layer outside the active region by utilizing inductively coupled plasma etching ICP, wherein the etching depth is larger than or equal to the sum of the thicknesses of the AlGaN barrier layer and the GaN channel layer, and the isolation between devices is realized as shown in figure 3.
Step S3: source-drain electrode 2. The source and drain electrode metal is defined as a rectangle with a length of 100 μm and a width of 10 μm on the active region where isolation is realized in step S2 by a negative photoresist lithography process, and is 2 μm away from the edge of the active region. The source and drain electrode thin film is deposited by electron beam evaporation, the Ti/Al/Ni/Au is sequentially arranged from bottom to top by adopting multiple layers of metals, the thicknesses of the Ti/Al/Ni/Au are 20/100/10/100nm respectively, and the source and drain electrode is formed by a stripping process, as shown in figure 4. And (3) placing the sample in a nitrogen atmosphere, and annealing at 850 ℃ for 1min to enable the source electrode and the drain electrode to form ohmic contact with the AlGaN barrier layer.
Step S4: a first gate dielectric layer 3 is deposited. SiO is deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) on the faces of the nitride buffer layer, alGaN barrier layer and source drain electrode 2 A first gate dielectric layer 3 is formed as shown in fig. 5. The thickness is 10nm, and the deposition conditions are as follows: cavity pressure is 850mTorr, high purity N 2 O flow rate is 1000sccm, high purity N 2 400sccm SiH at 5% by volume 4 And N 2 The flow rate of the mixed gas is 50sccm, the reaction temperature is 350 ℃, and the radio frequency power is 30W. The coupon is then transferred to a magnetron sputtering chamber.
Step S4: a second gate dielectric layer 4 is deposited. A second layer of dielectric 4 is formed on the face of the first gate dielectric layer 3 by magnetron sputtering as shown in fig. 6. The layer of Al 2 O 3 The preparation conditions of (2) are as follows: an alumina ceramic target with purity of 99.99% is used as a target, the substrate temperature is 300 ℃, sputtering gas is Ar, and reaction gas O with flow of 5sccm is introduced 2 The sputtering pressure was 6mtorr, the RF sputtering power was 160W, and the deposition thickness was 15nm.
Step S5: the source/drain electrode is exposed. And covering the photoresist on the non-source drain electrode region by a photoetching process to protect, and using an inductively coupled plasma etching ICP process. CHF with trifluoromethane 3 And O 2 The method is a process gas, and the specific conditions are as follows: CHF and CHF 3 Flow rate is 50sccm, O 2 The flow rate was 10sccm, RF power 60W, ICP power 600W. SiO is made of 2 Dielectric layer 3 and Al 2 O 3 And etching and removing the dielectric layer 4 to expose the source and drain electrode metal. As shown in fig. 7.
Step S6: a gate electrode 5 is prepared. As shown in FIG. 8, the pattern and position of the gate line is defined by a negative photoresist lithography process, wherein the gate line has a rectangular shape with a length of 100 μm and a width of 3 μm and is located between the source and drain electrodes. Sequentially depositing nickel and gold by using an electron beam evaporation process, wherein the thickness of the deposited layers of the nickel and the gold is 50nm and 150nm respectively, and realizing Al by using a stripping process 2 O 3 A gate electrode 5 remains over the dielectric 4.
The device is a stacked gate dielectric MOS high electron mobility transistor based on AlGaN/GaN heterojunction, and a first gate dielectric layer SiO is formed by adopting plasma enhanced chemical vapor deposition PEDCVD 2 . Wherein SiO is realized at a lower silane flow rate and a higher deposition temperature 2 The thin film has smaller thickness and higher compactness. Then forming a second gate dielectric layer Al by magnetron sputtering 2 O 3 Realizing a stacked gate dielectric MOS structure, preferably introducing oxygen to participate in the reaction in the sputtering film forming process, improving Al 2 O 3 Insulation of the film. First gate dielectric layer SiO 2 The active region is protected, so that the damage of the subsequent magnetron sputtering process to epitaxy can be effectively reduced; the second layer of high-k dielectric further improves the leakage characteristic of the dielectric layer and compensates the SiO of the first gate dielectric layer 2 The defect of low relative dielectric constant improves the control capability of the grid electrode to the channel, and further improves the dynamic electric characteristics of the device. The MOS structure prepared by the laminated gate dielectric process is suitable for large-scale production, reduces the gate leakage of devices and improves the breakdown characteristic and dynamic electric characteristic of the devices.
Example 2 sample Gate leakage Ig when applied with a voltage of-5V<10 ‐8 A/mm is reduced by two orders of magnitude compared with the SiN medium sample prepared by the existing plasma enhanced chemical vapor deposition PECVD. Example 2 the sample breakdown voltage reached 560V, which is increased by nearly 360V compared to 200V for a SiN dielectric sample prepared by plasma enhanced chemical vapor deposition PECVD. Example 2 the sample transconductance peak reaches 71mS/mm, which is 18mS/mm greater than the SiN dielectric sample prepared by plasma enhanced chemical vapor deposition PECVD.
Example 3
Referring to fig. 2-8, as shown in fig. 1, corresponding to each flow description, the method for manufacturing the GaN-based MOS-HEMT device with the metal oxide/silicon dioxide stack gate includes the following steps:
step S1: alGaN/GaN heterojunction epitaxial layer 1 is prepared. The nitride nucleation layer 04, the nitride buffer layer 03, the GaN channel layer 02, and the AlGaN barrier layer 01 are sequentially grown on the Si or SiC substrate 05 by metal organic vapor deposition (MOCVD), as shown in fig. 2. Then soaking the AlGaN/GaN heterojunction epitaxial layer 1 in H 2 SO 4 :H 2 O 2 =6: 1 (mass ratio) for 10 minutes to remove the surface oxide layer, and then acetone and isopropanol are adopted to remove the organic matters on the AlGaN/GaN heterojunction epitaxial layer 1.
Step S2: device isolation is achieved. The active region is defined by a positive photoresist lithography process, and is rectangular with a width of 53 μm and a length of 100 μm. And (5) performing coverage protection on the active region by using photoresist. And removing the heterojunction of the GaN channel layer and the AlGaN barrier layer outside the active region by utilizing inductively coupled plasma etching ICP, wherein the etching depth is larger than or equal to the sum of the thicknesses of the AlGaN barrier layer and the GaN channel layer, and the isolation between devices is realized as shown in figure 3.
Step S3: and (5) preparing a source-drain electrode. The source and drain electrode metal is defined as a rectangle with a length of 100 μm and a width of 10 μm on the active region where isolation is realized in step S2 by a negative photoresist lithography process, and is 2 μm away from the edge of the active region. The source and drain electrode thin film is deposited by electron beam evaporation, the Ti/Al/Ni/Au is sequentially arranged from bottom to top by adopting multiple layers of metals, the thicknesses of the Ti/Al/Ni/Au are 20/100/10/100nm respectively, and the source and drain electrode is formed by a stripping process, as shown in figure 4. And (3) placing the sample in a nitrogen atmosphere, and annealing at 850 ℃ for 1min to enable the source electrode and the drain electrode to form ohmic contact with the AlGaN barrier layer.
Step S4: a first gate dielectric layer 3 is deposited. SiO is deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) on the faces of the nitride buffer layer, alGaN barrier layer and source drain electrode 2 A first gate dielectric layer 3 is formed as shown in fig. 5. The thickness is 15nm, and the deposition conditions are as follows: cavity pressure is 850mTorr, high purity N 2 O flow rate is 1000sccm, high purity N 2 400sccm SiH at 5% by volume 4 And N 2 The flow rate of the mixed gas is 100sccm, the reaction temperature is 300 ℃, and the radio frequency power is 50W. Then transferring the sample wafer to magnetic control sputteringAnd the injection cavity.
Step S4: a second gate dielectric layer 4 is deposited. A second layer of dielectric 4 is formed on the face of the first gate dielectric layer 3 by magnetron sputtering as shown in fig. 6. The medium of the layer selects gallium oxide Ga with the relative dielectric constant reaching more than 10 2 O 3 The preparation conditions are as follows: gallium oxide ceramic targets with purity of 99.99% are used as target targets, the substrate temperature is 350 ℃, sputtering gas is Ar, sputtering air pressure is 3.5mtorr, radio frequency sputtering power is 140W, and deposition thickness is 15nm.
Step S5: the source-drain electrode 2 is exposed. And covering the photoresist on the non-source drain electrode region by a photoetching process to protect, and using an inductively coupled plasma etching ICP process. CHF with trifluoromethane 3 And O 2 The method is a process gas, and the specific conditions are as follows: CHF and CHF 3 Flow rate is 50sccm, O 2 The flow rate was 10sccm, RF power 60W, ICP power 600W. SiO is made of 2 Dielectric layer 3 and Al 2 O 3 And etching and removing the dielectric layer 4 to expose the source and drain electrode metal. As shown in fig. 7.
Step S6: a gate electrode 5 is prepared. As shown in fig. 8, the gate line pattern and the position are defined by a negative photoresist lithography process, wherein the gate line has a rectangular shape with a length of 100 μm and a width of 3 μm, and is located between the source and drain electrodes. Sequentially depositing nickel and gold by using an electron beam evaporation process, wherein the thickness of the deposited layers of the nickel and the gold is 50nm and 150nm respectively, and realizing Al by using a stripping process 2 O 3 A gate electrode 5 remains over the dielectric 4.
The device is a stacked gate dielectric MOS high electron mobility transistor based on AlGaN/GaN heterojunction, and a first gate dielectric layer SiO is formed by adopting plasma enhanced chemical vapor deposition PEDCVD 2 Then forming a second gate dielectric layer Al by magnetron sputtering 2 O 3 And realizing a stacked gate dielectric MOS structure. First gate dielectric layer SiO 2 The active region is protected, so that the damage of the subsequent magnetron sputtering process to epitaxy can be effectively reduced; the second layer of high-k dielectric further improves the leakage characteristic of the dielectric layer and compensates the SiO of the first gate dielectric layer 2 The defect of low relative dielectric constant improves the control capability of the grid electrode to the channel, and further improves the dynamic electric characteristics of the device. Plasma enhanced chemicalThe MOS structure prepared by the laminated gate dielectric process is suitable for large-scale production, reduces gate leakage of devices and improves breakdown characteristics and dynamic electric characteristics of the devices.
Example 3 sample Gate leakage Ig when applied with a voltage of-5V<10 ‐6 A/mm is reduced by an order of magnitude compared with the SiN medium sample prepared by the existing plasma enhanced chemical vapor deposition PECVD. Example 3 the sample breakdown voltage reached 360V, which is increased by nearly 160V compared to 200V for the SiN dielectric sample. Example 3 the sample transconductance peak reaches 77mS/mm, which is 24mS/mm greater than the SiN dielectric sample prepared by plasma enhanced chemical vapor deposition PECVD.
Those skilled in the art will appreciate that in other embodiments, the deposition conditions and manner of the first layer medium may be adjusted as desired, such as plasma enhanced chemical vapor deposition PECVD deposition of SiO 2 Pressure, power, gas flow, or Low Pressure Chemical Vapor Deposition (LPCVD) for SiO deposition 2 Corresponding effects can also be achieved. The deposition conditions for preparing Al2O3 by magnetron sputtering can be adjusted in the same way.
The above-described embodiments are only preferred examples of the present invention and do not constitute any limitation of the present invention, and it will be apparent to those skilled in the art that various modifications and changes in form and details can be made according to the method of the present invention without departing from the principle and scope of the invention, but these modifications and changes based on the present invention remain within the scope of the appended claims.

Claims (10)

1. The GaN-based MOS-HEMT device with the metal oxide/silicon dioxide stacked gate is characterized by comprising an AlGaN/GaN heterojunction epitaxial layer, a first gate dielectric layer, a second gate dielectric layer, a gate electrode and a source electrode and a drain electrode; the AlGaN/GaN heterojunction epitaxial layer comprises a substrate, a nitride nucleation layer, a nitride buffer layer, a GaN channel layer and an AlGaN barrier layer from bottom to top;
the first gate dielectricThe quality layer is SiO covered on the AlGaN/GaN heterojunction epitaxial layer 2 The thickness of the thin film and the first gate dielectric layer is 5-15nm;
the second gate dielectric layer is a metal oxide film covered on the first gate dielectric layer, and the metal oxide is Al 2 O 3 、Ga 2 O 3 、HfO 2 Or TiO x The thickness of the second gate dielectric layer is 5-15nm;
the first gate dielectric layer, the second gate dielectric layer and the AlGaN/GaN heterojunction epitaxial layer form an MOS structure;
the source electrode and the drain electrode are arranged on the AlGaN potential barrier layer at intervals; a gate electrode is arranged between the source electrode and the drain electrode and is arranged on the second gate dielectric layer;
the preparation method of the GaN-based MOS-HEMT device with the metal oxide/silicon dioxide stacked gate comprises the following steps:
1) And (3) epitaxial growth: sequentially epitaxially growing a nitride nucleation layer, a nitride buffer layer, a GaN channel layer and an AlGaN barrier layer on a substrate through metal organic vapor deposition to form an AlGaN/GaN heterojunction epitaxial layer;
2) Device isolation: defining an active region, and performing coverage protection on the active region by using photoresist; removing the AlGaN/GaN heterojunction epitaxial layer outside the active area by utilizing inductively coupled plasma etching ICP, wherein the etching depth is larger than the thicknesses of the AlGaN barrier layer and the GaN channel layer;
3) Source-drain electrode preparation: defining the metal positions and patterns of the source and drain electrodes on the active area which is isolated in the step 2) through a negative photoresist photoetching process, and depositing a source and drain electrode film through electron beam evaporation or magnetron sputtering; annealing in nitrogen atmosphere at a temperature above 800 ℃ to enable the source electrode and the drain electrode to form ohmic contact with the AlGaN barrier layer;
4) Depositing a first gate dielectric layer: deposition of SiO on AlGaN/GaN heterojunction epitaxial layers 2 The thin film is used for forming a first gate dielectric layer to cover, and the thickness of the first gate dielectric layer is 5-15nm;
5) And (3) depositing a second gate dielectric layer: depositing a metal oxide film on the first gate dielectric layer by magnetron sputtering;
6) Medium removal: removing the first dielectric layer and the second dielectric layer of the source drain electrode region to expose the source drain electrode metal; firstly protecting a medium except a source electrode and a drain electrode by photoresist, and then removing the medium;
7) Preparing a gate electrode: a gate electrode is prepared between the source and drain electrode metals by electron beam evaporation or magnetron sputtering.
2. The GaN-based MOS-HEMT device of claim 1 wherein the gate electrode and the source-drain electrode are both 100-300nm thick.
3. The GaN-based MOS-HEMT device of claim 1 wherein the gate electrode and the source-drain electrode are circular in cross-section.
4. The GaN-based MOS-HEMT device of claim 1 wherein the gate electrode is rectangular in cross section, 50-2000 μm long and 2-10 μm wide.
5. The GaN-based MOS-HEMT device of claim 1 wherein the substrate, nitride nucleation layer, nitride buffer layer, gaN channel layer and AlGaN barrier layer have thicknesses of 0.5-2mm, 0.2-1 μm, 500-2500nm, 100-500nm and 10-30nm, respectively.
6. The GaN-based MOS-HEMT device of claim 1 wherein the substrate is a circular sheet having a diameter of 4inch-10inch.
7. The GaN-based MOS-HEMT device of claim 1 wherein said SiO 2 The film is deposited by plasma enhanced chemical vapor deposition (P)ECVD) or low pressure chemical vapor deposition (LPCVD deposition).
8. The GaN-based MOS-HEMT device of claim 1 wherein the metal oxide film is formed by magnetron sputter deposition.
9. The method with metal oxide/silicon dioxide stacked gate GaN-based MOS-HEMT device of any of claims 1-8 characterized by comprising the steps of:
1) And (3) epitaxial growth: sequentially epitaxially growing a nitride nucleation layer, a nitride buffer layer, a GaN channel layer and an AlGaN barrier layer on a substrate through metal organic vapor deposition to form an AlGaN/GaN heterojunction epitaxial layer;
2) Device isolation: defining an active region, and performing coverage protection on the active region by using photoresist; removing the AlGaN/GaN heterojunction epitaxial layer outside the active area by utilizing inductively coupled plasma etching ICP, wherein the etching depth is larger than the thicknesses of the AlGaN barrier layer and the GaN channel layer;
3) Source-drain electrode preparation: defining the metal positions and patterns of the source and drain electrodes on the active area which is isolated in the step 2) through a negative photoresist photoetching process, and depositing a source and drain electrode film through electron beam evaporation or magnetron sputtering; annealing in nitrogen atmosphere at a temperature above 800 ℃ to enable the source electrode and the drain electrode to form ohmic contact with the AlGaN barrier layer;
4) Depositing a first gate dielectric layer: deposition of SiO on AlGaN/GaN heterojunction epitaxial layers 2 The thin film is used for forming a first gate dielectric layer to cover, and the thickness of the first gate dielectric layer is 5-15nm;
5) And (3) depositing a second gate dielectric layer: depositing a metal oxide film on the first gate dielectric layer by magnetron sputtering;
6) Medium removal: removing the first dielectric layer and the second dielectric layer of the source drain electrode region to expose the source drain electrode metal; firstly protecting a medium except a source electrode and a drain electrode by photoresist, and then removing the medium;
7) Preparing a gate electrode: preparing a gate electrode between source and drain electrode metals by electron beam evaporation or magnetron sputtering; the gate electrode is composed of two layers of metals, wherein the first layer of metal is nickel metal, and the second layer of metal is Au or TiN.
10. The method of claim 9, wherein the source-drain electrode film in step 3) is composed of a Ti/Al metal system multi-layer metal, and source-drain electrode metal lines are formed by a lift-off process; the Ti/Al metal system is Ti/Al/Ni/Au or Ti/Al/Ni/TiN;
the method for removing the medium in the step 6) is wet etching or dry etching; wherein the solution adopted by wet etching is hydrofluoric acid or phosphoric acid, etc.; the dry etching is inductively coupled plasma etching or reactive ion etching.
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