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CN116387246A - p-GaN enhanced MIS-HEMT device and preparation method thereof - Google Patents

p-GaN enhanced MIS-HEMT device and preparation method thereof Download PDF

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CN116387246A
CN116387246A CN202310306201.3A CN202310306201A CN116387246A CN 116387246 A CN116387246 A CN 116387246A CN 202310306201 A CN202310306201 A CN 202310306201A CN 116387246 A CN116387246 A CN 116387246A
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layer
gan
dielectric layer
electrode
hemt device
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王洪
丁凡
谢子敬
黄华茂
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South China University of Technology SCUT
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Abstract

The invention discloses a p-GaN enhanced MIS-HEMT device and a preparation method thereof. The devices being other than metal oxide/SiO 2 Lamination of layersAs a surface passivation layer to inhibit current collapse, promote the breakdown characteristic of the device and grow a layer of NiO by a thermal oxidation deposition mode x As a contact passivation layer and gate dielectric for the device. NiO x As a natural P-type oxide, the energy gap is large (about 4.0 ev), and the natural P-type oxide is used as a gate dielectric of a P-GaN HEMT device, so that the influence of the gate dielectric on the threshold voltage drift of the device can be reduced while the electric leakage of a gate can be effectively inhibited, and the overall performance of the device is improved.

Description

p-GaN enhanced MIS-HEMT device and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a p-GaN enhanced MIS-HEMT device and a preparation method thereof.
Background
The GaN high electron mobility transistor (High Electron Mobility Transistor, HEMT) has the advantages of high power, ultrahigh frequency and the like, and has wide application prospects in the fields of high-voltage switches, wireless 5G communication and the like. Conventional GaN HEMT devices are depletion mode, and in view of operational safety and manufacturing costs, HEMT devices are often required to be enhancement mode in high power applications. The use of a p-type GaN cap layer to deplete the two-dimensional electron gas under the channel is currently the most common solution in several main solutions for preparing enhancement-mode GaN HEMT devices. However, the conventional schottky gate p-GaN HEMT device still has many problems, mainly including small gate voltage swing, large gate leakage current and low threshold voltage of the device, and on the other hand, the problems of defect state density increase and two-dimensional electron gas concentration reduction caused by p-GaN etching above a barrier layer outside a gate region need to be overcome.
Conventional AlGaN/GaN HEMT devices generally employ Plasma Enhanced Chemical Vapor Deposition (PECVD) to grow a layer of SiO 2 The stack of/SiNx or both dielectric layers is used as passivation layer to reduce a large number of defects and dangling bonds on the barrier layer surface, however PECVD deposition of the dielectric cannot significantly reduce interface state density, alGaN/GaN and SiO 2 The interface trap states between/SiNx are capable of trapping or releasing electrons, causing reliability problems such as device current collapse (Geng K, chen D, zhou Q, et al, electronics,2018,416.).
Metal oxide deposition with high-k characteristics deposited by magnetron sputtering has small damage to SiO 2 /Si 3 N 4 Compared with the prior art, the method can effectively reduce the interface trap state density and inhibit the current collapse phenomenon of the GaN HEMT device. Metal oxide/SiO 2 The lamination used as the surface passivation layer is applied to the p-GaN gate enhanced HEMT device, so that the interface state density can be effectively reduced, the current collapse can be inhibited, and the enhancement is achievedIncreasing device reliability, however, when used directly as a contact passivation layer or gate dielectric, can cause problems with negative threshold voltage drift in HEMT devices (Lin Y C, lin T W, wu C H, et al,2016, ieee, 115-118.) which is detrimental to enhancement device applications. Therefore, a more effective dielectric lamination structure needs to be designed, the trap state quantity of a contact interface between a dielectric and a semiconductor material is reduced, the influence of the dielectric on the threshold voltage drift of the device is reduced while the current collapse is inhibited, the electric leakage of a grid electrode is reduced, and the integral grid control capability of the device is improved.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention aims to provide a p-GaN enhanced MIS-HEMT device and a preparation method thereof, wherein the device adopts metal oxide/SiO 2 The lamination is used as a surface passivation layer to inhibit current collapse, so that not only the breakdown characteristic of the device is improved, but also a layer of NiO is grown in a thermal oxidation deposition mode x As a contact passivation layer and gate dielectric for the device. NiO x As a natural P-type oxide, the energy gap is large (about 4.0 ev), and the natural P-type oxide is used as a gate dielectric of a P-GaN HEMT device, so that the influence of the gate dielectric on the threshold voltage drift of the device can be reduced while the electric leakage of a gate can be effectively inhibited, and the overall performance of the device is improved.
The object of the invention is achieved by at least one of the following technical solutions.
The p-GaN enhanced MIS-HEMT device comprises a substrate layer, a nucleation layer, a buffer layer, a channel layer and a barrier layer which are sequentially laminated from bottom to top;
the upper surface of the barrier layer is sequentially provided with a source electrode, a p-GaN layer and a drain electrode which are spaced from each other from one end to the other end, the p-GaN layer is provided with a gate electrode, and a first dielectric layer is arranged between the p-GaN layer and the gate electrode;
the first dielectric layer covers all upper surfaces except the contact surfaces of the barrier layer with the source electrode, the p-GaN layer and the drain electrode and all surfaces of the p-GaN layer except the contact surfaces with the barrier layer;
the second dielectric layer covers all upper surfaces of the first dielectric layer except the contact surface with the p-GaN layer;
and the third dielectric layer covers all the upper surfaces of the second dielectric layer.
Further, the first dielectric layer is NiO grown by thermal oxidation of a Ni metal film x The upper surface of the first dielectric layer is connected with a gate electrode and is used as a gate dielectric and a bottom passivation layer, the thickness of the first dielectric layer from bottom to top is 8-20 nm, and the thickness of the Ni metal film is 2-5 nm;
the second dielectric layer is a metal oxide film, and the metal oxide is HfO 2 、Al 2 O 3 Or Ga 2 O 3 At least one of the second dielectric layers has a thickness of 5-20 nm;
the third dielectric layer is SiO covered on the second dielectric layer 2 The thickness of the thin film, the third dielectric layer from bottom to top is 50-200 nm.
Further, the material of the substrate layer is any one of silicon, sapphire, silicon carbide, gallium nitride and a diamond self-supporting substrate; the material of the nucleation layer is AlN superlattice; the material of the buffer layer is GaN or AlGaN; the material of the channel layer is GaN or GaAs; the material of the barrier layer is either AlGaN, inAlN, alN or InGaN.
Further, the thicknesses of the substrate layer, the nucleation layer, the buffer layer, the channel layer, the barrier layer and the p-GaN layer are respectively 0.5-2 mm, 0.2-1 μm, 0.5-2.5 μm, 100-300 nm, 10-30 nm and 70-120 nm.
The preparation method of the p-GaN enhanced MIS-HEMT device comprises the following steps:
s1, epitaxial growth: sequentially epitaxially growing a nucleation layer, a buffer layer, a channel layer, a barrier layer and a p-GaN layer on the substrate layer by metal organic chemical vapor deposition;
s2, mesa isolation etching: obtaining a patterned device mesa through a photoetching process, and performing mesa isolation by adopting an ICP/RIE etching technology, wherein the etching depth exceeds the sum of thicknesses of the barrier layer and the channel layer;
s3, p-GaN etching outside the gate region: the patterned p-GaN grid region is obtained through a photoetching process, the p-GaN layers except the grid region are completely removed by adopting an ICP/RIE etching technology, and only the p-GaN layer below the grid is reserved;
s4, preparing a source-drain electrode: the patterned areas of the source electrode and the drain electrode are obtained through a photoetching process, and source-drain ohmic contact electrodes are prepared on the upper surface of the barrier layer;
s5, preparing a first dielectric layer: depositing a first dielectric layer on the surface of the wafer;
s6, through holes of the first dielectric layer: patterning the source-drain electrode through hole pattern by a photoetching process, and forming a source-drain electrode through hole by adopting an ICP/RIE etching technology;
s7, preparing a gate electrode: obtaining a patterned grid electrode and a bonding pad region through a photoetching process, depositing a grid electrode and bonding pad metal lamination, and then carrying out metal stripping;
s8, preparing a second medium layer: depositing a second dielectric layer metal oxide film on the surface of the wafer;
s9, preparing a third medium layer: depositing a third dielectric layer SiO on the surface of the wafer 2 A film;
s10, electrode through holes: and (3) obtaining a patterned electrode pad through hole pattern through a photoetching process, forming an electrode pad through hole by adopting an ICP/RIE etching technology, and exposing the source electrode, the gate electrode and the drain electrode.
Further, in mesa isolation, p-GaN etching outside the gate region and electrode via etching in step S2, step S3, step S6 and step S10, the gases are chlorine, fluorine, ar, N 2 Or O 2 At least one of them.
Further, in step S4, the source-drain ohmic contact electrode metal system is Ti/Al/Ni/Au or Ti/Al/Ti/Au lamination; and (3) after the metal electrode is stripped, carrying out high-temperature thermal annealing for 15-60 s at the temperature of more than 800 ℃ in a nitrogen atmosphere to form the ohmic alloy.
Further, in step S5, the first dielectric layer is prepared, the Ni metal film is grown by electron beam evaporation or magnetron sputtering, and is oxidized at high temperature by a thermal oxidation furnace or a rapid thermal annealing furnace, the thermal oxidation temperature is 350-450 ℃, the oxygen flow is 50-100 sccm, and the thermal oxidation treatment time is 15-30 min.
Further, in step S7, the gate electrode and the pad metal are Ni/Au or Ni/TiN stack.
Further, in step S8, the second dielectric layer metal oxide film is formed by magnetron sputtering deposition, the sputtering power is 100-150W, the pressure in the cavity is 5-10 mTorr, the sputtering temperature is 80-300 ℃, and the sputtering rate is 0.1-0.5 nm/min.
Further, in step S9, a third dielectric layer SiO 2 The film is formed by Plasma Enhanced Chemical Vapor Deposition (PECVD) or Low Pressure Chemical Vapor Deposition (LPCVD), and the deposition temperature is 300-450 ℃.
Compared with the prior art, the p-GaN enhanced MIS-HEMT device provided by the invention has the following beneficial effects and technical advantages:
(1) By metal oxide/SiO 2 Lamination as surface passivation layer, and conventional SiO 2 The passivation phase can effectively reduce interface state density, inhibit current collapse, improve saturation current density and breakdown characteristic of the device, and protect the active region of the device.
(2) NiO is adopted x As a gate medium of the P-GaN gate enhanced MIS-HEMT, the natural P-type oxide characteristic can reduce the influence of surface passivation on the threshold voltage drift of the device; the grid control capability of the device is improved, and the grid leakage is effectively reduced.
(3) NiO is adopted x The whole p-GaN grid electrode is wrapped by the grid medium and the bottom passivation layer, so that a peak electric field introduced by the p-GaN side wall is optimized, and the breakdown characteristic of the device is further improved.
(4) NiO is generated by thermal oxidation in a thermal oxidation furnace or a rapid thermal annealing furnace mode x The process has the advantages of simple preparation flow and small deposition damage, and is compatible with the existing process for preparing HEMT devices.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a p-GaN enhancement-mode MIS-HEMT device according to an embodiment of the present invention;
fig. 2, fig. 3, fig. 4, fig. 5, fig. 6, fig. 7, and fig. 8 are schematic diagrams illustrating a p-GaN enhancement type MIS-HEMT device according to an embodiment of the present invention;
fig. 9, 10 and 11 are the presentThe p-GaN enhanced MIS-HEMT device provided by the embodiment of the invention and the device containing HfO 2 /SiO 2 P-GaN gate MS-HEMT device of dielectric passivation layer and traditional SiO 2 The p-GaN gate MS-HEMT device with the medium being passivated is subjected to a current collapse schematic diagram under the two conditions of drain bias stress 200V and drain-free bias (Ref);
fig. 12 shows a p-GaN enhancement-mode MIS-HEMT device and a HfO-containing device according to an embodiment of the present invention 2 /SiO 2 P-GaN gate MS-HEMT device of dielectric passivation layer and traditional SiO 2 The transfer characteristic diagram of the p-GaN gate MS-HEMT device with the medium being passivated;
fig. 13 shows a p-GaN enhanced MIS-HEMT device and a device with HfO according to an embodiment of the present invention 2 /SiO 2 P-GaN gate MS-HEMT device of dielectric passivation layer and traditional SiO 2 A dielectric is used as a passivation p-GaN gate MS-HEMT device gate leakage current schematic diagram;
fig. 14 shows a p-GaN enhancement type MIS-HEMT device and a device with HfO according to an embodiment of the present invention 2 /SiO 2 The breakdown voltage of the p-GaN MS-HEMT device of the dielectric passivation layer and the conventional p-GaN gate MS-HEMT device without the dielectric layer is shown in the schematic diagram.
Detailed Description
The invention will be further described in detail with reference to the drawings and examples, but the invention can be embodied or practiced in other different specific forms and with the proviso that the scope of protection is to be construed as long as the variations and modifications are within the spirit and scope of the appended claims.
Examples:
in one embodiment, as shown in fig. 1, the p-GaN enhancement-mode MIS-HEMT device is prepared by a method comprising the steps of:
s1, epitaxial growth: an AlN nucleation layer 02, an AlGaN buffer layer 03, a GaN channel layer 04, an AlGaN barrier layer 05 and a p-GaN layer 06 are sequentially epitaxially grown on a silicon-based substrate layer (01) by Metal Organic Chemical Vapor Deposition (MOCVD), as shown in FIG. 2; then placing the epitaxy on H 2 SO 4 :H 2 O 2 =3: 1 (mass ratio) soaking in the solution for 10 minutes, removingRemoving the surface oxide layer, and ultrasonically cleaning by adopting acetone and isopropanol for 10 minutes to remove organic matters on the epitaxy;
s2, mesa isolation etching: the patterned device active region is obtained through a photoetching process, an ICP/RIE etching technology is adopted for carrying out mesa isolation, and the etching depth exceeds the sum of the thicknesses of the AlGaN barrier layer 05 and the GaN channel layer 04;
s3, p-GaN etching outside the gate region: the patterned p-GaN grid region is obtained through a photoetching process, the p-GaN layer 06 except the grid region is completely removed by adopting an ICP/RIE etching technology, only the p-GaN layer 06 below the grid is reserved, and the etching gas adopts Cl 2 /Ar/O 2 The flow rates are respectively 40/10/5sccm, the ICP/RF power is respectively 200/50W, the pressure in the cavity is 1mTorr, the p-GaN etching rate is 4-5nm/min, and the etching is finished as shown in FIG. 3;
s4, preparing a source-drain electrode: ti/Al/Ni/Au is sequentially deposited on the upper surface of the AlGaN barrier layer 05 by electron beam evaporation, and patterned regions of a source electrode 07 and a drain electrode 09 are obtained by photoetching and stripping processes, as shown in FIG. 4, wherein the thickness of a first metal layer Ti is 20nm, the thickness of a second metal layer Al is 100nm, the thickness of a third metal layer Ni is 10nm, the thickness of a fourth metal layer Au is 100nm, and the thickness of a metal electrode is N after stripping 2 Thermal annealing at 830 ℃ for 30s under atmosphere;
s5, preparing a first dielectric layer: depositing a layer of Ni metal film with the thickness of 5nm on the surface of a wafer, and performing thermal oxidation treatment on the metal film in a rapid annealing furnace for 20 minutes, wherein the temperature in the chamber is 400 ℃, the oxygen flow is 50sccm, so as to form a first dielectric layer NiO x 10；
S6, through holes of the first dielectric layer: the patterned source-drain electrode through hole pattern is obtained through a photoetching process, the source-drain electrode through hole is formed by adopting an ICP/RIE etching technology, and the etching gas adopts Cl 2 /BCl 3 The flow rates are respectively 60/10sccm, the ICP/RF power is respectively 300/50W, the pressure in the cavity is 5mTorr, and the etching is finished as shown in FIG. 5;
s7, preparing a gate electrode: sequentially depositing Ni/Au metal lamination from bottom to top as a gate electrode and a metal bonding pad through electron beam evaporation, and obtaining a patterned gate electrode 08 and bonding pad through photoetching and stripping processes, as shown in fig. 6, wherein the thickness of a first metal layer Ni is 50nm, and the thickness of a second metal layer Au is 200nm;
s8, preparing a second medium layer: depositing a second dielectric layer HfO with the thickness of 15nm on the surface of the wafer by magnetron sputtering 2 11, as shown in FIG. 7, the sputtering power was 150W, the chamber pressure was 6mTorr, the substrate temperature was 100deg.C, and the sputtering rate was 0.3nm/min. And carrying out thermal annealing at 400 ℃ in N2 atmosphere after dielectric deposition to repair dielectric damage.
S9, preparing a third medium layer: deposition of a third dielectric layer SiO by PECVD 2 12, the deposition temperature is 300 ℃, and the deposition thickness is 200nm;
s10, electrode through holes: the patterned electrode pad via hole pattern is obtained by a photolithography process, an electrode via hole is formed by an ICP/RIE etching technique, the source electrode 07, the gate electrode 08 and the drain electrode 09 are exposed, and the etching gas adopts CHF 3 /O 2 The flow rates were 50/10sccm, ICP/RF power was 400/60W, chamber pressure was 5mTorr, and after etching was completed, FIG. 8 shows.
In one embodiment, fig. 9 and 10 and 11 are respectively a p-GaN enhanced MIS-HEMT device, and a HfO-containing device in contrast thereto 2 /SiO 2 P-GaN gate enhanced MS-HEMT device of dielectric passivation layer and traditional SiO 2 The p-GaN gate enhanced MS-HEMT device with the medium being passivated is a current collapse schematic diagram under the two conditions of drain bias stress 200V and no drain bias (Ref), wherein a solid line (Ref) corresponds to an output curve under the condition of no drain bias, and a dotted line corresponds to the output curve under the condition of drain bias stress 200V and lasting stress time 10 s. As can be seen from the graph, the current collapse amounts of the p-GaN enhanced MIS-HEMT device corresponding to the embodiment are 8.3%, 10.7% and 24.4%, respectively, compared with the conventional SiO 2 The dielectric is passivated, and the current collapse of the device with the high-k metal oxide dielectric layer is reduced by 66% and 56% respectively.
In one embodiment, FIG. 12 is a p-GaN enhanced MIS-HEMT device, and a comparison thereof, a device containing HfO 2 /SiO 2 P-GaN gate enhanced MS-HEMT device of dielectric passivation layer and traditional SiO 2 And a transfer characteristic curve diagram of the p-GaN gate enhanced MS-HEMT device passivated by the medium. Wherein the traditional SiO 2 The p-GaN gate enhanced MS-HEMT device with passivation medium has threshold voltage of +0.83V and contains HfO 2 /SiO 2 The threshold voltage of the P-GaN gate enhanced MS-HEMT device of the dielectric passivation layer is +0.1V, and the threshold voltage of the P-GaN enhanced MIS-HEMT device provided by the embodiment is +1.17V, and NiO with P-type characteristics is formed x The problem of negative drift of the threshold voltage of the device can be effectively solved by using the p-GaN gate enhanced HEMT device as the gate dielectric.
In one embodiment, FIG. 13 is a p-GaN enhanced MIS-HEMT device, and a comparison thereof, a device containing HfO 2 /SiO 2 P-GaN gate enhanced MS-HEMT device of dielectric passivation layer and traditional SiO 2 Grid leakage of the p-GaN grid enhanced MS-HEMT device with the medium being passivated is shown. when-2V grid voltage is applied, the grid leakage of the p-GaN enhanced MIS-HEMT device provided by the embodiment is less than 10 -9 A/mm, ratio is not NiO x The gate leakage of the two sets of controls of the gate dielectric is reduced by an order of magnitude.
In one embodiment, FIG. 14 is a p-GaN enhanced MIS-HEMT device, and a comparison thereof, a device containing HfO 2 /SiO 2 The breakdown characteristic diagrams of the p-GaN gate enhanced MS-HEMT device of the dielectric passivation layer and the conventional p-GaN gate enhanced MS-HEMT device without the dielectric layer are shown. The embodiment provides a device breakdown voltage up to 722V, which is increased by approximately 110V over a conventional device structure without any dielectric layer, compared to a device structure without NiOx gate dielectric but with HfO 2 /SiO 2 The device of the medium is 28V higher.
The above examples are provided to assist the reader in understanding the structure and preparation method of the present invention, and the embodiments of the present invention are not limited to the above examples. Those skilled in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations are still within the scope of the present disclosure.

Claims (10)

  1. The p-GaN enhanced MIS-HEMT device is characterized by comprising a substrate layer (01), a nucleation layer (02), a buffer layer (03), a channel layer (04) and a barrier layer (05) which are sequentially stacked from bottom to top;
    the upper surface of the barrier layer (05) is sequentially provided with a source electrode (07), a p-GaN layer (06) and a drain electrode (09) which are spaced from each other from one end to the other end, a gate electrode (08) is arranged on the p-GaN layer (06), and a first dielectric layer (10) is arranged between the p-GaN layer (06) and the gate electrode (08);
    the first dielectric layer (10) covers all upper surfaces of the barrier layer (05) except the contact surfaces with the source electrode (07), the p-GaN layer (06) and the drain electrode (09) and all surfaces of the p-GaN layer (06) except the contact surfaces with the barrier layer (05);
    the second dielectric layer (11) covers all upper surfaces of the first dielectric layer (10) except the contact surface with the p-GaN layer (06);
    the third dielectric layer (12) covers all upper surfaces of the second dielectric layer (11).
    The p-GaN enhancement mode MIS-HEMT device of claim 1 wherein said first dielectric layer (10) is Ni metal thin film thermally oxidized grown NiO x The upper surface of the first dielectric layer (10) is connected with a gate electrode (08) and is used as a gate dielectric and a bottom passivation layer, the thickness of the first dielectric layer (10) from bottom to top is 8-20 nm, and the thickness of the Ni metal film is 2-5 nm;
    the second dielectric layer (11) is a metal oxide film, and the metal oxide is HfO 2 、Al 2 O 3 Or Ga 2 O 3 The thickness of the second dielectric layer (11) is 5-20 nm;
    the third dielectric layer (12) is SiO covered on the second dielectric layer (11) 2 The thickness of the film, the third dielectric layer (12) from bottom to top is 50-200 nm.
  2. 2. The p-GaN enhancement-mode MIS-HEMT device of claim 1, wherein the material of the substrate layer (01) is any one of silicon, sapphire, silicon carbide, gallium nitride, diamond self-supporting substrate; the material of the nucleation layer (02) is AlN superlattice; the material of the buffer layer (03) is GaN or AlGaN; the material of the channel layer (04) is GaN or GaAs; the material of the barrier layer (05) is either AlGaN, inAlN, alN or InGaN.
  3. 3. The p-GaN enhancement-type MIS-HEMT device of claim 1, wherein the substrate layer (01), nucleation layer (02), buffer layer (03), channel layer (04), barrier layer (05) and p-GaN layer (06) have thicknesses of 0.5-2 mm, 0.2-1 μm, 0.5-2.5 μm, 100-300 nm, 10-30 nm and 70-120 nm, respectively.
  4. The preparation method of the 4.p-GaN enhanced MIS-HEMT device is characterized by comprising the following steps of:
    s1, epitaxial growth: epitaxially growing a nucleation layer (02), a buffer layer (03), a channel layer (04), a barrier layer (05) and a p-GaN layer (06) on the substrate layer (01) in sequence by Metal Organic Chemical Vapor Deposition (MOCVD);
    s2, mesa isolation etching: obtaining a patterned device mesa through a photoetching process, performing mesa isolation by adopting an ICP/RIE etching technology, wherein the etching depth exceeds the sum of thicknesses of the barrier layer (05) and the channel layer (04);
    s3, p-GaN etching outside the gate region: the patterned p-GaN grid region is obtained through a photoetching process, the p-GaN layers (06) except the grid region are completely removed by adopting an ICP/RIE etching technology, and only the p-GaN layers (06) below the grid are reserved;
    s4, preparing a source-drain electrode: the patterned areas of the source electrode (07) and the drain electrode (09) are obtained through a photoetching process, and source-drain ohmic contact electrodes are prepared on the upper surface of the barrier layer (05);
    s5, preparing a first dielectric layer: depositing a first dielectric layer (10) on the surface of the wafer;
    s6, through holes of the first dielectric layer: patterning the source-drain electrode through hole pattern by a photoetching process, and forming a source-drain electrode through hole by adopting an ICP/RIE etching technology;
    s7, preparing a gate electrode: obtaining a patterned grid electrode and a bonding pad region through a photoetching process, depositing a grid electrode (08) and a bonding pad metal lamination, and then carrying out metal stripping;
    s8, preparing a second medium layer: depositing a second dielectric layer (11) metal oxide film on the surface of the wafer;
    s9, preparing a third medium layer: depositing a third dielectric layer (12) of SiO on the wafer surface 2 A film;
    s10, electrode through holes: the patterned electrode pad through hole pattern is obtained through a photoetching process, and an ICP/RIE etching technology is adopted to form the electrode pad through hole, so that the source electrode (07), the gate electrode (08) and the drain electrode (09) are exposed.
  5. 5. The method for fabricating a p-GaN enhanced MIS-HEMT device of claim 4, wherein in mesa isolation, gate out-of-gate p-GaN etching and electrode via etching in steps S2, S3, S6 and S10, the gas is chlorine, fluorine, ar, N 2 Or O 2 At least one of them.
  6. 6. The method for fabricating a p-GaN enhanced MIS-HEMT device of claim 4, wherein in step S4, the source-drain ohmic contact electrode metal system is a Ti/Al/Ni/Au or Ti/Al/Ti/Au stack; and (3) after the metal electrode is stripped, carrying out high-temperature thermal annealing for 15-60 s at the temperature of more than 800 ℃ in a nitrogen atmosphere to form the ohmic alloy.
  7. 7. The method for fabricating a p-GaN enhanced MIS-HEMT device according to claim 4, wherein in step S5, the first dielectric layer is fabricated, the Ni metal film is grown by electron beam evaporation or magnetron sputtering, and is oxidized at high temperature by a thermal oxidation furnace or a rapid thermal annealing furnace, the thermal oxidation temperature is 350-450 ℃, the oxygen flow is 50-100 sccm, and the thermal oxidation treatment time is 15-30 min.
  8. 8. The method of manufacturing a p-GaN enhancement-mode MIS-HEMT device of claim 4, wherein in step S7, the gate electrode and the pad metal are Ni/Au or Ni/TiN stacks.
  9. 9. The method of manufacturing a p-GaN enhancement type MIS-HEMT device according to claim 4, wherein in step S8, the second dielectric layer metal oxide film is formed by magnetron sputtering deposition, the sputtering power is 100-150W, the intra-cavity pressure is 5-10 mTorr, the sputtering temperature is 80-300 ℃, and the sputtering rate is 0.1-0.5 nm/min.
  10. 10. The method for fabricating a p-GaN enhanced MIS-HEMT device of claim 4, wherein in step S9, a third dielectric layer, siO 2 The film is formed by Plasma Enhanced Chemical Vapor Deposition (PECVD) or Low Pressure Chemical Vapor Deposition (LPCVD), and the deposition temperature is 300-450 ℃.
CN202310306201.3A 2023-03-24 2023-03-24 p-GaN enhanced MIS-HEMT device and preparation method thereof Pending CN116387246A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118198123A (en) * 2024-05-20 2024-06-14 江苏能华微电子科技发展有限公司 Enhanced GaN power device and preparation method thereof
CN118412273A (en) * 2024-07-03 2024-07-30 成都航天博目电子科技有限公司 Gate preparation method of GaN HEMT device, gate and GaN HEMT device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118198123A (en) * 2024-05-20 2024-06-14 江苏能华微电子科技发展有限公司 Enhanced GaN power device and preparation method thereof
CN118198123B (en) * 2024-05-20 2024-10-01 江苏能华微电子科技发展有限公司 Enhanced GaN power device and preparation method thereof
CN118412273A (en) * 2024-07-03 2024-07-30 成都航天博目电子科技有限公司 Gate preparation method of GaN HEMT device, gate and GaN HEMT device

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