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CN106653751B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN106653751B
CN106653751B CN201510742087.4A CN201510742087A CN106653751B CN 106653751 B CN106653751 B CN 106653751B CN 201510742087 A CN201510742087 A CN 201510742087A CN 106653751 B CN106653751 B CN 106653751B
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Prior art keywords
layer
semiconductor devices
gate structure
semiconductor
semiconductor substrate
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CN201510742087.4A
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CN106653751A (zh
Inventor
徐长春
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201510742087.4A priority Critical patent/CN106653751B/zh
Priority to EP16196138.8A priority patent/EP3166150A1/en
Priority to US15/343,433 priority patent/US9985132B2/en
Publication of CN106653751A publication Critical patent/CN106653751A/zh
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Publication of CN106653751B publication Critical patent/CN106653751B/zh
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    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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Abstract

一种半导体器件及其制造方法，所述方法包括：提供半导体衬底；在半导体衬底上形成栅极结构；在栅极结构两侧的半导体衬底上形成外延衬底层；在栅极结构的侧壁上形成硬掩膜侧壁层；以硬掩膜侧壁层为掩膜，刻蚀外延衬底层和半导体衬底，在栅极结构两侧形成沟槽；在沟槽内形成应力层。本发明将外延衬底层作为PMOS器件衬底的一部分，使PMOS器件衬底被抬高且可以通过调节外延衬底层的厚度以控制衬底被抬高的高度，从而在保证对PMOS沟道区施加压应力以提高空穴迁移率的同时，减少形成沟槽的刻蚀工艺对靠近栅极底部的氧化层的损耗，从而避免了栅极结构和源、漏区之间的短路问题，进而提高半导体器件的性能。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体领域，尤其涉及一种半导体器件及其制造方法。
背景技术
在半导体制造中，随着超大规模集成电路的发展趋势，集成电路特征尺寸持续减小，晶体管的尺寸也越来越小、操作速度越来越快，因此，半导体制造工艺对晶体管性能的要求也越来越高。载流子的迁移率是影响晶体管性能的主要因素之一，有效提高载流子迁移率成为了晶体管器件制造工艺的重点之一。
在互补金属氧化物半导体场效应晶体管(CMOS)器件的制造技术中，普遍将P型金属氧化物半导体场效应晶体管(PMOS)和N型金属氧化物半导体场效应晶体管(NMOS)分开处理，例如，在PMOS器件的制造方法中，外延生长锗硅(EPI SiGe)技术通过在PMOS器件的源漏(S/D)区形成锗硅(SiGe)应力层，能对沟道区施加适当的压应力以提高空穴的迁移率而成为PMOS器件应力工程的主要技术之一。而在NMOS器件中则形成能提供拉应力的应力层以提高电子迁移率。
但是，现有技术形成的PMOS器件的性能提高有限，工艺制程窗口小，产品良率受限。
发明内容
本发明解决的问题是提供一种半导体器件及其制造方法，提高半导体器件的性能和产品良率。
为解决上述问题，本发明提供一种半导体器件的制造方法。包括如下步骤：提供半导体衬底；在所述半导体衬底上形成栅极结构；在所述栅极结构两侧的半导体衬底上形成外延衬底层；在所述外延衬底层、栅极结构和半导体衬底上保形覆盖一层硬掩膜层；刻蚀所述硬掩膜层，在所述栅极结构的侧壁上形成硬掩膜侧壁层；以所述硬掩膜侧壁层为掩膜，刻蚀所述外延衬底层和半导体衬底，在所述栅极结构两侧形成沟槽；在所述沟槽内形成应力层。
可选的，所述半导体器件为PMOS，所述沟槽的形状为Sigma形状。
可选的，所述外延衬底层的材料为硅。
可选的，形成所述外延衬底层的方法为化学气相沉积外延生长法。
可选的，形成所述外延衬底层的化学气相沉积外延生长法中，工艺温度为500℃至950℃，工艺时间为10s至11000s，反应室气压为5Torr至1000Torr，外延形成所述外延衬底层的预处理气体为氢气，外延形成所述外延衬底层的反应气体为氯化氢、二氯二氢硅、硅烷中的一种气体或多种构成的混合气体。
可选的，所述外延衬底层的厚度为至
可选的，所述硬掩膜层的材料为氮化硅。
可选的，所述硬掩膜层的厚度为至
可选的，所述应力层的材料为锗硅材料或含硼的锗硅材料。
可选的，形成所述应力层的方法为化学气相沉积外延生长法。
可选的，形成所述应力层的化学气相沉积外延生长法中，工艺温度为500℃至950℃，工艺时间为10s至11000s反应室气压为5Torr至1000Torr，外延形成所述应力层的预处理气体为氢气，外延形成所述应力层的反应气体为氯化氢、二氯二氢硅、硅烷或乙硼烷中的一种气体或多种构成的混合气体。
可选的，所述应力层的厚度为至
可选的，在所述栅极结构两侧形成沟槽的步骤包括：以所述硬掩膜侧壁层为掩膜，采用第一刻蚀工艺，依次刻蚀所述外延衬底层和半导体衬底，在所述栅极结构两侧的外延衬底层和半导体衬底内形成初始开口；
采用第二刻蚀工艺刻蚀所述初始开口，在所述栅极结构两侧的外延衬底层和半导体衬底内形成沟槽。
可选的，所述第一刻蚀工艺为等离子体干法刻蚀工艺，所述第二刻蚀工艺为各向异性的湿法刻蚀工艺。
本发明还提供一种半导体器件结构，包括：半导体衬底；位于半导体衬底上的栅极结构；位于所述栅极结构两侧的半导体衬底上的外延衬底层，所述外延衬底层的厚度小于所述栅极结构的高度；位于所述栅极结构侧壁上的硬掩膜侧壁层，所述硬掩膜侧壁层位于所述外延衬底层上方；位于所述外延衬底层和半导体衬底中的应力层。
可选的，所述半导体器件还包括位于所述半导体衬底内的隔离结构，所述应力层位于所述隔离结构与所述栅极结构之间。
可选的，所述外延衬底层的材料为硅，所述应力层的材料为锗硅或锗硅硼。
可选的，所述外延衬底层的厚度为至
可选的，所述应力层的厚度为至
可选的，所述硬掩膜侧壁层的材料为氮化硅。
与现有技术相比，本发明的技术方案具有以下优点：本发明在栅极结构两侧的半导体衬底上形成外延衬底层，所述外延衬底层作为PMOS器件的衬底的一部分，使PMOS器件的衬底被抬高，且可以通过调节所述外延衬底层的厚度以控制PMOS器件衬底被抬高的高度，在所述栅极结构的侧壁上形成硬掩膜侧壁层，以所述硬掩膜侧壁层为掩膜刻蚀所述外延衬底层和半导体衬底，在所述栅极结构两侧形成Sigam形状的沟槽，在形成所述沟槽的工艺过程中，所述硬掩膜侧壁层底部的外延衬底层被保留，从而使形成的沟槽顶部的开口尺寸变小，相应的，靠近所述外延衬底层的沟槽侧壁与所述衬底表面的夹角变小，从而减少了形成所述Sigam形状的沟槽的刻蚀工艺对靠近栅极底部的氧化层的损耗，避免了栅极结构和两侧源、漏区之间的短路问题，因此，在向所述沟槽内形成应力层后，可以进一步提高所述应力层对PMOS结构沟道区施加压应力的效果，进而提高半导体器件的性能。
附图说明
图1至图4是现有技术半导体器件的制造方法各步骤对应结构示意图；
图5至图17是本发明半导体器件的制造方法一实施例中各步骤对应结构示意图。
具体实施方式
参考图1至图4，在现有技术半导体制造过程中，半导体器件的形成工艺包括以下步骤：
提供包括NMOS区域Ⅰ和PMOS区域Ⅱ的半导体衬底100(如图1所示)，在所述NMOS区域Ⅰ和PMOS区域Ⅱ的半导体衬底100表面分别形成有栅极结构110(如图1所示)，在所述半导体衬底100和栅极结构110上保形覆盖一层介质层120(如图1所示)；在所述半导体衬底100上形成图形化的第一掩膜层130(如图2所示)，所述图形化的掩膜层130覆盖所述NMOS区域Ⅰ，以所述图形化的掩膜层130为掩膜，通过刻蚀工艺在所述PMOS区域Ⅱ栅极结构110两侧的半导体衬底100内形成沟槽140(如图2所示)，在所述PMOS区域Ⅱ的栅极结构110侧壁表面形成侧墙121，所述沟槽140的形状为Sigma形状；在所述沟槽140内填充应力层150(如图3所示)；在所述半导体衬底100上形成图形化的第二掩膜层160(如图4所示)，所述图形化的第二掩膜层140覆盖所述PMOS区域Ⅱ，以所述图形化的第二掩膜层160为掩膜，刻蚀所述NMOS区域Ⅰ半导体衬底100表面和栅极结构110顶部的介质层120，在所述NMOS区域Ⅰ的栅极结构110侧壁表面形成侧墙121；后续再通过离子注入工艺以形成半导体器件。
现有技术通过刻蚀所述PMOS区域Ⅱ的介质层120(如图1所示)和半导体衬底100以形成Sigma形状的沟槽140(如图2所示)，所述Sigma形状的沟槽140顶部的开口尺寸较大，相应的，靠近所述半导体衬底100的沟槽140侧壁与所述半导体衬底100表面的夹角较大，因此在对所述半导体衬底100进行刻蚀以形成所述Sigma形状的沟槽140时，容易对靠近所述栅极结构110底部的氧化层的造成损耗，从而导致所述栅极结构110和源、漏区(未图示)之间的短路，进而降低了半导体器件的性能。
为了解决所述技术问题，本发明提供一种半导体器件的制造方法，包括：提供半导体衬底；在所述半导体衬底上形成栅极结构；在所述栅极结构两侧的半导体衬底上形成外延衬底层；在所述外延衬底层、栅极结构和半导体衬底上保形覆盖一层硬掩膜层；刻蚀所述硬掩膜层，在所述栅极结构的侧壁上形成硬掩膜侧壁层；以所述硬掩膜侧壁层为掩膜，刻蚀所述外延衬底层和半导体衬底，在所述栅极结构两侧形成沟槽；在所述沟槽内形成应力层。
在形成所述沟槽之前，本发明先在栅极结构两侧的半导体衬底上形成外延衬底层，所述外延衬底层作为PMOS器件的衬底的一部分，使PMOS器件的衬底被抬高，且可以通过调节所述外延衬底层的厚度以控制PMOS器件衬底被抬高的高度，在所述栅极结构的侧壁上形成硬掩膜侧壁层，以所述硬掩膜侧壁层为掩膜刻蚀所述外延衬底层和半导体衬底，在所述栅极结构两侧形成Sigam形状的沟槽，在形成所述沟槽的工艺过程中，所述硬掩膜侧壁层底部的外延衬底层被保留，从而使形成的沟槽顶部的开口尺寸变小，相应的，靠近所述外延衬底层的沟槽侧壁与所述衬底表面的夹角变小，从而减少了形成所述Sigam形状的沟槽的刻蚀工艺对靠近栅极底部的氧化层的损耗，避免了栅极结构和两侧源、漏区之间的短路问题，因此，在向所述沟槽内形成应力层后，可以进一步提高所述应力层对PMOS结构沟道区施加压应力的效果，进而提高半导体器件的性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图5至图17是本发明半导体器件的制造方法一实施例中各步骤对应结构示意图。
参考图5，提供半导体衬底200。
具体地，所述半导体衬底200包括：用于形成NMOS的第一区域Ⅰ和用于形成PMOS的第二区域Ⅱ。
本实施例中，所述第一区域I和第二区域II为相邻的区域。
所述半导体衬底200的材料为硅、锗、锗化硅、碳化硅、砷化镓或镓化铟，所述半导体衬底200还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底。本实施例中，所述半导体衬底200为硅衬底。
需要说明的是，所述半导体衬底200中还形成有隔离结构210，所述隔离结构210可以是浅沟槽隔离结构，但不限于浅沟槽隔离结构。所述隔离结构210用于实现器件之间的相互隔离。
具体地，所述隔离结构210的形成步骤包括：刻蚀所述半导体衬底200，在所述半导体衬底200内形成隔离沟槽(未图示)；向所述隔离沟槽内填充满隔离材料；平坦化所述隔离材料形成所述隔离结构210。
所述隔离材料可以为氧化硅材料，向所述隔离沟槽内填充氧化硅材料的工艺可以为化学气相沉积法或物理气相沉积法，例如流体化学气相沉积(FCVD，Flow ChemicalVapor Deposition)工艺、等离子体增强化学气相沉积工艺或高纵宽比化学气相沉积工艺(HARP)。
本实施例中，采用高纵宽比化学气相沉积工艺(HARP)向所述隔离沟槽内填充满氧化硅材料，使形成的隔离结构210均匀致密，无空洞缺陷，具有良好的隔离作用；所述平坦化工艺为化学机械研磨工艺；所述刻蚀工艺为各向异性的干法刻蚀工艺。
继续参考图5，在所述半导体衬底200上形成栅极结构。
具体地，所述半导体衬底200包括用于形成NMOS器件的第一区域Ⅰ和用于形成PMOS器件的第二区域Ⅱ，相应的，形成栅极结构的步骤包括：在所述第一区域Ⅰ半导体衬底200表面形成第一栅极结构221，在所述第二区域II半导体衬底200表面形成第二栅极结构220。
结合参考图5和图6，需要说明的是，在所述半导体衬底200上形成栅极结构之后，还包括：在所述半导体衬底200、第一栅极结构221和第二栅极结构220上保形覆盖一层第一介质层(未图示)；刻蚀去除第二区域II半导体衬底200表面和第二栅极结构220顶部的第一介质层，形成覆盖所述第二栅极220结构侧壁表面的第一侧墙(未图示)。
所述第一介质层可以为单层结构，也可以为叠层结构。当所述第一介质层为单层结构时，所述第一介质层为氧化硅膜；当所述第一介质层为叠层结构时，所述第一介质层为氧化硅膜和氮化硅膜构成的双层结构，或所述第一介质层为氧化硅膜、氮化硅膜和氧化硅膜构成的三层结构。本实施例中，所述第一介质层包括氧化硅膜230(如图5所示)和氮化硅膜240(如图5所示)，所述氧化硅膜230的厚度为至所述氮化硅膜240的厚度为至相应的，所述第一侧墙为氧化硅层231和氮化硅层241构成的叠层结构。
具体地，形成所述第一侧墙的步骤包括：在所述半导体衬底200、第一栅极结构221和第二栅极结构220上保形覆盖第一介质层之后，在所述半导体衬底200表面形成图形化的第一掩膜层300，所述图形化的第一掩膜层300覆盖所述第一区域Ⅰ并暴露所述第二区域II；以所述图形化的第一掩膜层300为掩膜，沿暴露的第二区域II刻蚀去除所述第二区域II半导体衬底200表面和第二栅极结构220顶部的第一介质层，在所述第二栅极220结构侧壁表面形成由氧化硅层231和氮化硅层241构成的第一侧墙。
本实施例中，所述图形化的第一掩膜层300的材料为光刻胶，形成所述第一侧墙之后，采用湿法去胶或灰化工艺去除所述图形化的第一掩膜层300。
参考图7，在所述第二栅极结构220两侧的半导体衬底200上形成外延衬底层250。
后续通过刻蚀所述第二栅极结构220两侧外延衬底层250和半导体衬底200，在所述外延衬底层250和半导体衬底200内形成沟槽；所述半导体衬底200的第二区域Ⅱ用于形成PMOS器件，在所述第二栅极结构220两侧的外延衬底层250和半导体衬底200内形成的沟槽的形状为Sigma形状。
具体地，刻蚀去除所述第二区域II半导体衬底200表面和第二栅极结构220顶部的第一介质层，暴露出所述第二栅极结构220两侧的第二区域II半导体衬底200表面之后，在所述第二栅极结构220两侧露出的第二区域II半导体衬底200表面形成外延衬底层250。
本实施例中，所述外延衬底层250表面高出所述隔离结构210表面。但所述外延衬底层250的厚度不能过厚，也不能过薄。当所述外延衬底层250的厚度过厚时，后续难以在所述外延衬底层250和半导体衬底200内形成PMOS器件相对应Sigma形状的沟槽(未图示)，而所述Sigma形状的沟槽在后续工艺中用于形成应力层且所述应力层作为半导体器件的源、漏区，因此过厚的外延衬底层250容易对半导体器件源、漏区的形成质量产生不良影响，此外，在形成所述Sigma形状的沟槽的刻蚀工艺过程中，容易对所述第二栅极结构220底部的氧化层造成损耗，从而容易引起所述第二栅极结构220和后续形成的源、漏区(未图示)之间的短路问题，进而影响半导体器件的性能和良率；当所述外延衬底层250的厚度过薄时，后续形成的Sigma形状的沟槽位于所述半导体衬底200内的深度过深，而所述Sigma形状的沟槽在后续工艺中用于形成应力层且所述应力层作为半导体器件的源、漏区，从而也会影响半导体器件的性能和良率。为此，本实施例中，所述外延衬底层250的厚度为至
具体地，所述外延衬底层250的材料可以为硅、锗、锗化硅、碳化硅、砷化镓或镓化铟。本实施例中，所述外延衬底层250的材料为硅。
本实施例中，形成所述外延衬底层250所采用的化学气相沉积外延生长法的工艺参数包括：工艺温度为500℃至950℃，工艺时间为10s至11000s，反应室气压为5Torr至1000Torr，外延形成所述外延衬底层250的预处理气体为氢气，外延形成所述外延衬底层250的反应气体为氯化氢、二氯二氢硅、硅烷中的一种气体或多种构成的混合气体。
当工艺温度过高或过低时，基于设定的工艺时间及反应室气压条件，难以形成工艺所需的膜层材料，且难以保证形成的外延衬底层250的厚度值可以满足目标厚度值，因此，所述工艺温度需控制在500℃至950℃。相应的，为了形成满足目标厚度值的外延衬底层250且使所述外延衬底层250的材料为工艺所需的膜层材料，工艺时间需控制在10s至11000s，反应室气压需控制在5Torr至1000Torr。
参考图8，在所述外延衬底层250、第二栅极结构220和半导体衬底200上保形覆盖一硬掩膜层260。
通过调节所述硬掩膜层260的厚度，可以控制后续形成的Sigma形状的沟槽(未图示)的深度和横截面面积大小。
具体地，在所述第一区域Ⅰ的第一介质层(未图示)、外延衬底层250、形成有第一侧墙(未图示)的第二栅极结构220和半导体衬底200上保形覆盖一硬掩膜层260。
当所述硬掩膜层260的厚度过厚时，会导致后续通过刻蚀工艺在所述外延衬底层250和半导体衬底200内形成的Sigma形状的沟槽(未图示)的开口过小，同时影响所述沟槽横截面面积大小，而所述Sigma形状的沟槽在后续工艺中用于形成应力层且所述应力层作为半导体器件的源、漏区，因此过厚的外延衬底层250容易对半导体器件源、漏区的形成质量产生不良影响，从而影响半导体器件的性能和良率；当所述硬掩膜层260的厚度过薄时，会导致后续在所述外延衬底层250和半导体衬底200内形成的Sigma形状的沟槽顶部的开口尺寸较大，相应的，靠近所述半导体衬底200的沟槽侧壁与所述半导体衬底200表面的夹角较大，在对所述半导体衬底200进行刻蚀以形成所述Sigma形状的沟槽时，容易对靠近所述第二栅极结构220底部的氧化层造成损耗，从而导致所述第二栅极结构220和后续形成的源、漏区(未图示)之间的短路，进而降低了半导体器件的性能。为此，本实施例中，所述硬掩膜层260的厚度为至
具体地，通过化学气相沉积工艺形成硬掩膜层260。其中，所述硬掩膜层260可以包括氧化物层、氮化物层、氮氧化物层和无定形碳中的一种或多种。其中，氧化物层可以包括硼磷硅玻璃(BPSG)、磷硅玻璃(PSG)、正硅酸乙酯(TEOS)、未掺杂硅玻璃(USG)、旋涂玻璃(SOG)、高密度等离子体(HDP)或旋涂电介质(SOD)，氮化物层可包括氮化硅(Si3N4)层，氮氧化物层可包括氮氧化硅(SiON)层。本实施例中，所述硬掩膜层260为氮化硅层。
参考图9，刻蚀所述硬掩膜层260，在所述第二栅极结构220的侧壁上形成硬掩膜侧壁层261。
所述硬掩膜侧壁层261作为后续在所述外延衬底层250和半导体衬底200内形成沟槽的刻蚀掩膜层。
具体地，在所述半导体衬底200表面形成图形化的第二掩膜层310，所述图形化的第二掩膜层310覆盖所述第一区域Ⅰ并暴露出所述第二区域II；以所述图形化的第二掩膜层310为掩膜，通过等离子体干法刻蚀工艺，沿暴露的第二区域II刻蚀所述硬掩膜层260，在所述第二栅极结构220的侧壁上形成硬掩膜侧壁层261。
需要说明的是，由于所述硬掩膜层260保形覆盖于所述第二栅极结构220和外延衬底层250上，经过刻蚀工艺后，所述第二栅极结构220顶部和外延衬底层250部分表面的硬掩膜层260被刻蚀去除，形成位于所述第二栅极结构220侧壁上的硬掩膜侧壁层261。
本实施例中，所述图形化的第二掩膜层310的材料为光刻胶，形成所述硬掩膜侧壁层261之后，保留所述图形化的第二掩膜层310。
结合参考图9和图10，以所述硬掩膜侧壁层261为掩膜，刻蚀所述外延衬底层250和半导体衬底200，在所述第二栅极结构220两侧形成沟槽280(如图10所示)
具体地，在所述第二栅极结构220两侧形成沟槽280的步骤包括：以所述图形化的第二掩膜层310和所述硬掩膜侧壁层261为掩膜，采用第一刻蚀工艺，依次刻蚀所述第二区域II的外延衬底层250和半导体衬底200，在所述第二栅极结构220两侧的外延衬底层250和半导体衬底200内形成初始开口270(如图9所示)；采用第二刻蚀工艺刻蚀所述初始开口270，在所述第二栅极结构220两侧的外延衬底层250和半导体衬底200内形成沟槽280(如图10所示)；去除所述图形化的第二掩膜层310。
需要说明的是，所述第二区域Ⅱ用于形成PMOS器件，因此，所述沟槽280的形状为Sigma形状。
本实施例中，所述第一刻蚀工艺为等离子体干法刻蚀工艺。所述第一刻蚀工艺的工艺参数包括：刻蚀气体为CF4、CH3F、HBr、NF3、Cl2、O2和N2中的一种或多种气体，载气为Ar和He中的一种或多种气体，反应室气压为2mtorr至100mtorr，偏置电压为50V至250V，工艺温度为30℃至100℃，工艺时间为3s至20s。
需要说明的是，形成所述初始开口270之后，靠近所述隔离结构210一侧的外延衬底层250被去除，由于所述硬掩膜侧壁层261覆盖部分外延衬底层250表面，因此所述硬掩膜侧壁层261下方的部分外延衬底层250被保留。在其他实施例中，被保留的外延衬底层250还可以包括靠近所述隔离结构210一侧的部分外延衬底层250，以及位于所述硬掩膜侧壁层261下方的部分外延衬底层250。
本实施例中，所述第二刻蚀工艺为各向异性的湿法刻蚀工艺。所述湿法刻蚀工艺所采用的刻蚀液体包括四甲基氢氧化氨溶液，工艺温度为20℃至120℃，工艺时间为20s至500s。
需要说明的是，所述初始开口270的形状为所述沟槽280形状的过渡形状。通过湿法刻蚀工艺的各向异性，对硅材料具有很高的刻蚀选择比，湿法刻蚀所述初始开口270(如图9所示)后，在所述第二栅极结构220两侧的外延衬底层250和半导体衬底200内形成Sigma形状的沟槽280。所述沟槽280的深度大于所述初始开口270的深度，所述沟槽280的横截面面积大于所述初始开口270的横截面面积。形成所述沟槽280之后，采用湿法去胶或灰化工艺去除所述图形化的第二掩膜层310。
还需要说明的是，通过湿法刻蚀工艺形成所述沟槽280的过程中，所述第二栅极结构220两侧的部分外延衬底层250及隔离结构210被去除。
参考图11，在所述沟槽280(如图10所示)内形成应力层400。
具体地，形成所述沟槽280后，在所述沟槽280内填充应力材料以形成应力层400。
所述应力层400的材料为锗硅材料或含硼的锗硅材料；由于所述外延衬底层250的表面高出所述隔离结构210表面，相应的，所述应力层400的表面高出所述隔离结构210表面。
本实施例中，所述应力层400的材料为锗硅，形成所述应力层400的工艺为化学气相沉积外延生长法。其中，所述化学气相沉积外延生长法的工艺参数包括：工艺温度为500℃至950℃，工艺时间为10s至11000s，反应室气压为5Torr至1000Torr，外延形成所述应力层400的预处理气体为氢气，外延形成所述应力层400的反应气体为氯化氢、二氯二氢硅、硅烷中的一种气体或多种构成的混合气体。
当工艺温度过高或过低时，基于设定的工艺时间及反应室气压条件，难以形成工艺所需的膜层材料，且难以保证形成的应力层400的厚度值可以满足目标厚度值，因此，所述工艺温度需控制在500℃至950℃。相应的，为了形成满足目标厚度值的应力层400且使所述应力层400的材料为工艺所需的膜层材料，工艺时间需控制在10s至11000s，反应室气压需控制在5Torr至1000Torr。
通过所述应力层400对所述PMOS区域的沟道区施加适当的应力，从而提高空穴的迁移率，进而提升半导体器件的性能。
此外，在形成所述应力层400之前，先在第二栅极结构220两侧的半导体衬底200上形成外延衬底层250，所述外延衬底层250作为PMOS器件的衬底的一部分，使PMOS器件的衬底被抬高，且可以通过调节所述外延衬底层的厚度以控制PMOS器件衬底被抬高的高度，在所述第二栅极结构220的侧壁上形成硬掩膜侧壁层261，以所述硬掩膜侧壁层261为掩膜刻蚀所述外延衬底层250和半导体衬底200，在所述第二栅极结构220两侧的外延衬底层250和半导体衬底200内形成Sigma形状的沟槽280时，所述硬掩膜侧壁层261底部的外延衬底层250被保留，从而使形成的Sigma形状的沟槽280顶部的开口尺寸变小，相应的，靠近所述外延衬底层250的沟槽280侧壁与所述衬底200表面的夹角变小，从而减少了形成所述Sigam形状的沟槽280的刻蚀工艺对靠近第二栅极结构220底部的氧化层的损耗，在保证所述应力层400对所述PMOS区域的沟道区施加压应力以提高空穴迁移率的同时，避免了所述第二栅极结构220和两侧源、漏区(未图示)之间的短路问题，进而提高半导体器件的性能。
参考图12，刻蚀去除所述第一区域Ⅰ的第一介质层(未图示)表面的硬掩膜层260(如图11所示)，然后刻蚀去除所述第一区域Ⅰ半导体衬底200表面和第一栅极结构221顶部的第一介质层，形成覆盖所述第一栅极结构221侧壁表面的第一侧墙(未图示)。
本实施例中，所述第一介质层包括氧化硅膜230(如图11所示)和氮化硅膜240(如图11所示)，相应的，所述覆盖所述第一栅极结构221侧壁表面的第一侧墙为氧化硅层231和氮化硅层241构成的叠层结构。
具体地，形成覆盖所述第一栅极结构221侧壁表面的第一侧墙的步骤包括：在所述半导体衬底200表面形成图形化的第三掩膜层320，所述图形化的第三掩膜层320覆盖所述第二区域II并暴露出所述第一区域Ⅰ；以所述图形化的第三掩膜层320为掩膜，采用等离子体干法刻蚀工艺，沿暴露的第一区域Ⅰ刻蚀去除所述硬掩膜层260；以所述图形化的第三掩膜层320为掩膜，，刻蚀去除所述第一区域Ⅰ半导体衬底200表面以及所述第一栅极结构221顶部表面的第一介质层，在所述第一栅极结构221的侧壁表面形成第一侧墙。
本实施例中，所述图形化的第三掩膜层320的材料为光刻胶，在所述第一栅极结构221的侧壁表面形成所述第一侧墙之后，采用湿法去胶或灰化工艺去除所述图形化的第三掩膜层320。
参考图13，形成覆盖所述第一栅极结构221侧壁表面的第一侧墙之后，在所述第一栅极结构221两侧的半导体衬底200中形成第一浅掺杂离子区(未图示)。
具体地，在所述半导体衬底200表面形成图形化的第四掩膜层330，所述图形化的第四掩膜层330覆盖所述第二区域II并暴露出所述第一区域Ⅰ；以所述图形化的第四掩膜层330为掩膜，对所述第一区域Ⅰ进行浅掺杂离子注入工艺，在所述第一栅极结构221两侧的半导体衬底200中形成第一浅掺杂离子区。形成第一浅掺杂离子区之后，采用湿法去胶或灰化工艺去除所述图形化的第四掩膜层330。
本实施例中，所述第一区域Ⅰ用于形成NMOS，即所述第一浅掺杂离子区的主掺杂离子为N型离子，所述N型离子为磷离子、砷离子或锑离子，所述注入的离子能量为0.2Kev至10Kev，注入的离子剂量为2E14至3E15原子每平方厘米。
参考图14，在所述第二栅极结构220两侧的半导体衬底200中形成第二浅掺杂离子区(未图示)。
具体地，在所述半导体衬底200表面形成图形化的第五掩膜层340，所述图形化的第五掩膜层340覆盖所述第一区域Ⅰ并暴露出所述第二区域II；以所述图形化的第五掩膜层340为掩膜，对所述第二区域II进行浅掺杂离子注入工艺，在所述第二栅极结构220两侧的半导体衬底200中形成第二浅掺杂离子区。形成第二浅掺杂离子区之后，采用湿法去胶或灰化工艺去除所述图形化的第五掩膜层340。
需要说明的是，所述外延衬底层250和半导体衬底200内形成有所述应力层400，所述第二浅掺杂离子区位于所述应力层400和半导体衬底200内。
本实施例中，所述第二区域II用于形成PMOS，即所述第二浅掺杂离子区的主掺杂离子为P型离子，所述P型离子为硼离子、镓离子或铟离子，所述注入的离子能量为4Kev至50Kev，注入的离子剂量为6E12至6E13原子每平方厘米。
参考图15，在所述第一区域Ⅰ和第二区域II形成覆盖所述第一侧墙(未图示)表面的第二侧墙271。
具体地，形成所述第二侧墙271的步骤包括：在所述第一侧墙、应力层400、硬掩膜侧壁层261、第一栅极结构221、第二栅极结构220和半导体衬底200上保形覆盖一层第二介质层(未图示)；采用无掩膜刻蚀工艺，刻蚀去除所述半导体衬底200表面、第一栅极结构221顶部表面、第二栅极结构220顶部表面以及部分所述应力层顶部表面的第二介质层，在所述第一侧墙表面形成第二侧墙271。
需要说明的是，所述第二区域II的第一侧墙表面形成有硬掩膜侧壁层261，所述第二侧墙271形成于所述硬掩膜侧壁层261的侧壁表面。
本实施例中，所述无掩膜刻蚀工艺为等离子干法刻蚀工艺。
需要说明的是，所述第二介质层可以为单层结构，也可以为叠层结构。当所述第二介质层为单层结构时，所述第二介质层为氧化硅膜，相应的，所述第二侧墙271为氧化硅层；当所述第二介质层为叠层结构时，所述第二介质层为氧化硅膜和氮化硅膜构成的双层结构，或所述第二介质层为氧化硅膜、氮化硅膜和氧化硅膜构成的三层结构。相应的，所述第二侧墙271可以为氧化硅层，或氧化硅层和氮化硅层构成的双层结构，或氧化硅层、氮化硅层和氧化硅层构成的三层结构。
参考图16，在所述第一区域Ⅰ和第二区域II形成覆盖所述第一侧墙(未图示)表面的第二侧墙271之后，在所述第一栅极结构221两侧的半导体衬底200中形成第一源、漏区(未图示)。
具体地，在所述半导体衬底200表面形成图形化的第六掩膜层350，所述图形化的第六掩膜层350覆盖所述第二区域II并暴露出所述第一区域Ⅰ；以所述图形化的第六掩膜层350为掩膜，对所述第一区域Ⅰ进行重掺杂离子注入工艺，在所述第一栅极结构221两侧的半导体衬底200中形成第一源、漏区。形成所述第一源、漏区之后，采用湿法去胶或灰化工艺去除所述图形化的第六掩膜层350。
本实施例中，所述第一区域Ⅰ用于形成NMOS，即所述第一源、漏区的主掺杂离子为N型离子，所述N型离子为磷离子、砷离子或锑离子，所述注入的离子能量为1Kev至10Kev，注入的离子剂量为1E14至5E15原子每平方厘米。
参考图17，在所述第二栅极结构220两侧的半导体衬底200中形成第二源、漏区(未图示)。
具体地，在所述半导体衬底200表面形成图形化的第七掩膜层360，所述图形化的第七掩膜层360覆盖所述第一区域Ⅰ并暴露出所述第二区域II；以所述图形化的第七掩膜层360为掩膜，对所述第二区域II进行重掺杂离子注入工艺，在所述第二栅极结构220两侧的半导体衬底200中形成第二源、漏区。形成所述第二源、漏区之后，采用湿法去胶或灰化工艺去除所述图形化的第七掩膜层360。
本实施例中，所述第二区域II用于形成PMOS，即所述第二源、漏区的主掺杂离子为P型离子，所述P型离子为硼离子、镓离子或铟离子，所述注入的离子能量为1Kev至10Kev，注入的离子剂量为6E12至6E13原子每平方厘米。
需要说明的是，所述外延衬底层250和半导体衬底200内形成有所述应力层400，所述第二源、漏区位于所述应力层400和半导体衬底200内。
此外，参考图15，本发明还提供一种半导体器件，包括：
半导体衬底200；
位于所述半导体衬底200上的栅极结构；
位于所述栅极结构两侧的半导体衬底200上的外延衬底层250，所述外延衬底层250厚度小于所述栅极结构的高度；
位于所述栅极结构侧壁上的硬掩膜侧壁层261，所述硬掩膜侧壁层261位于所述外延衬底层250上方；
位于所述外延衬底层250和半导体衬底200中的应力层400。
具体地，所述半导体衬底200包括：用于形成NMOS的第一区域Ⅰ和用于形成PMOS的第二区域Ⅱ。
本实施例中，所述第一区域I和第二区域II为相邻的区域。
本实施例中，所述栅极结构包括：位于所述第一区域I半导体衬底200上的第一栅极结构221和位于所述第二区域Ⅱ半导体衬底200上的第二栅极结构220；所述外延衬底层250位于所述第二栅极结构220两侧的半导体衬底200上；所述硬掩膜侧壁层261位于所述第二栅极结构220侧壁上。
本实施例中，所述半导体器件结构还包括位于所述半导体衬底200内的隔离结构210，所述隔离结构210可以是浅沟槽隔离结构，但不限于浅沟槽隔离结构。所述隔离结构210用于实现器件之间的相互隔离。其中，在所述第二区域II内，所述应力层400位于所述隔离结构210与所述第二栅极结构220之间。
本实施例中，所述外延衬底层250的材料为硅，所述硬掩膜侧壁层261的材料为氮化硅，所述应力层400的材料为锗硅或锗硅硼。其中，所述外延衬底层250的厚度为至所述应力层400的厚度为至
所述外延衬底层250作为PMOS器件衬底的一部分，使PMOS器件衬底被抬高，且可以通过调节所述外延衬底层250的厚度以控制PMOS器件衬底被抬高的高度，从而在保证对PMOS沟道区施加适当的压应力以提高空穴迁移率的同时，使靠近所述第二栅极220底部的氧化硅层231的质量不受影响，从而避免所述第二栅极结构220和第二栅极结构220两侧的半导体衬底200内的源、漏区(未图示)之间的短路问题，进而提高半导体器件的性能。
本发明半导体器件结构可以由半导体器件结构的制造方法形成，但是本发明对此不作限制，还可以采用其他制造方法形成。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

1.一种半导体器件的制造方法，其特征在于，包括：
提供半导体衬底；
在所述半导体衬底表面上形成栅极结构；
在所述栅极结构两侧的半导体衬底表面上形成外延衬底层，以抬高所述半导体衬底的高度；
在所述外延衬底层、栅极结构和半导体衬底上保形覆盖一层硬掩膜层；
刻蚀所述硬掩膜层，在所述栅极结构的侧壁上形成硬掩膜侧壁层；
以所述硬掩膜侧壁层为掩膜，刻蚀所述外延衬底层和半导体衬底，在所述栅极结构两侧形成沟槽；
在所述沟槽内形成应力层。
2.如权利要求1所述的半导体器件的制造方法，其特征在于，所述半导体器件为PMOS，所述沟槽的形状为Sigma形状。
3.如权利要求1所述的半导体器件的制造方法，其特征在于，所述外延衬底层的材料为硅。
4.如权利要求1所述的半导体器件的制造方法，其特征在于，形成所述外延衬底层的方法为化学气相沉积外延生长法。
5.如权利要求4所述的半导体器件的制造方法，其特征在于，形成所述外延衬底层的化学气相沉积外延生长法中，工艺温度为500℃至950℃，工艺时间为10s至11000s，反应室气压为5Torr至1000Torr，外延形成所述外延衬底层的预处理气体为氢气，外延形成所述外延衬底层的反应气体为氯化氢、二氯二氢硅、硅烷中的一种气体或多种构成的混合气体。
6.如权利要求1所述的半导体器件的制造方法，其特征在于，所述外延衬底层的厚度为至
7.如权利要求1所述的半导体器件的制造方法，其特征在于，所述硬掩膜层的材料为氮化硅。
8.如权利要求1所述的半导体器件的制造方法，其特征在于，所述硬掩膜层的厚度为至
9.如权利要求1所述的半导体器件的制造方法，其特征在于，所述应力层的材料为锗硅材料或含硼的锗硅材料。
10.如权利要求1所述的半导体器件的制造方法，其特征在于，形成所述应力层的方法为化学气相沉积外延生长法。
11.如权利要求10所述的半导体器件的制造方法，其特征在于，形成所述应力层的化学气相沉积外延生长法中，工艺温度为500℃至950℃，工艺时间为10s至11000s反应室气压为5Torr至1000Torr，外延形成所述应力层的预处理气体为氢气，外延形成所述应力层的反应气体为氯化氢、二氯二氢硅、硅烷或乙硼烷中的一种气体或多种构成的混合气体。
12.如权利要求1所述的半导体器件的制造方法，其特征在于，所述应力层的厚度为至
13.如权利要求1所述的半导体器件的制造方法，其特征在于，在所述栅极结构两侧形成沟槽的步骤包括：以所述硬掩膜侧壁层为掩膜，采用第一刻蚀工艺，依次刻蚀所述外延衬底层和半导体衬底，在所述栅极结构两侧的外延衬底层和半导体衬底内形成初始开口；
采用第二刻蚀工艺刻蚀所述初始开口，在所述栅极结构两侧的外延衬底层和半导体衬底内形成沟槽。
14.如权利要求13所述的半导体器件的制造方法，其特征在于，所述第一刻蚀工艺为等离子体干法刻蚀工艺，所述第二刻蚀工艺为各向异性的湿法刻蚀工艺。
15.一种半导体器件，其特征在于，包括：
半导体衬底；
位于半导体衬底表面上的栅极结构；
位于所述栅极结构两侧的半导体衬底表面上的外延衬底层，所述外延衬底层的厚度小于所述栅极结构的高度；所述外延衬底层表面的高度高于所述半导体衬底表面的高度；
位于所述栅极结构侧壁上的硬掩膜侧壁层，所述硬掩膜侧壁层位于所述外延衬底层上方；
位于所述外延衬底层和半导体衬底中的应力层。
16.如权利要求15所述的半导体器件，其特征在于，所述半导体器件还包括位于所述半导体衬底内的隔离结构，所述应力层位于所述隔离结构与所述栅极结构之间。
17.如权利要求15所述的半导体器件，其特征在于，所述外延衬底层的材料为硅，所述应力层的材料为锗硅或锗硅硼。
18.如权利要求15所述的半导体器件，其特征在于，所述外延衬底层的厚度为至
19.如权利要求15所述的半导体器件，其特征在于，所述应力层的厚度为 至
20.如权利要求15所述的半导体器件，其特征在于，所述硬掩膜侧壁层的材料为氮化硅。
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