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CN105742193B - 晶圆与晶圆接合的工艺及结构 - Google Patents

晶圆与晶圆接合的工艺及结构 Download PDF

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Publication number
CN105742193B
CN105742193B CN201510971451.4A CN201510971451A CN105742193B CN 105742193 B CN105742193 B CN 105742193B CN 201510971451 A CN201510971451 A CN 201510971451A CN 105742193 B CN105742193 B CN 105742193B
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China
Prior art keywords
joint connections
opening
substrate
wafer
joint
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CN105742193A (zh
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余振华
陈明发
蔡文景
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例提供了一种接合结构及其形成方法。在接合结构的第一表面上形成导电层，接合结构包括接合至第二衬底的第一衬底，接合结构的第一表面是第一衬底的暴露的表面。在导电层上形成具有第一开口和第二开口的图案化的掩模，第一开口和第二开口暴露导电层的一部分。在第一开口中形成第一接合连接件的第一部分，并且在第二开口中形成第二接合连接件的第一部分。图案化导电层以形成第一接合连接件的第二部分和第二接合连接件的第二部分。使用第一接合连接件和第二接合连接件将接合结构接合至第三衬底。

Description

晶圆与晶圆接合的工艺及结构
相关申请的交叉参考
本申请要求以下于2014年12月26日临时提交的标题为“Wafer to Wafer BondingProcess and Structures”的美国专利申请第62/096,972号的优先权，其全部内容通过引用结合于此作为参考。
技术领域
本发明总体涉及半导体领域，更具体地，涉及晶圆接合的方法及其结构。
背景技术
为了遵守摩尔定律，半导体制造者面对不断的挑战。他们不断努力地持续减小特征尺寸(诸如有源和无源器件的尺寸)、互连引线宽度和厚度以及功耗，同时增大器件密度、引线密度和工作频率。在一些应用中，这些更小的电子组件还需要比过去的封装件占用更少面积的更小封装。
最近在半导体封装中开发了三维集成电路(3DIC)，其中多个半导体管芯彼此堆叠，诸如叠层封装(PoP)和系统级封装(SiP)的封装技术。形成3DIC的一些方法涉及将两个或多个半导体晶圆与位于不同半导体晶圆上的有源电路(诸如逻辑电路、存储器电路、处理器电路等)接合在一起。常用的接合技术包括直接接合、化学激活接合、等离子体激活接合、阳极接合、共晶接合、玻璃浆料接合、粘合剂接合、热压接合、反应接合等。一旦两个半导体晶圆接合在一起，两个半导体晶圆之间的界面就可以在堆叠的半导体晶圆之间提供导电路径。
堆叠的半导体器件的一个优势在于，通过采用堆叠的半导体器件可以来实现高得多的密度。此外，堆叠半导体器件可实现更小的形状因数、高成本效益、改进的性能以及较低的功耗。
发明内容
根据本发明的一个方面，提供了一种方法，包括：在接合结构的第一表面上形成导电层，所述接合结构包括接合至第二衬底的第一衬底，所述接合结构的第一表面是所述第一衬底的暴露的表面；在所述导电层上形成图案化的掩模，所述图案化的掩模包括第一开口和第二开口，所述第一开口和所述第二开口暴露所述导电层的一部分；在所述第一开口中形成第一接合连接件的第一部分，并且在所述第二开口中形成第二接合连接件的第一部分；图案化所述导电层以形成所述第一接合连接件的第二部分和所述第二接合连接件的第二部分，其中，所述第一接合连接件的第一部分和所述第二接合连接件的第一部分用作掩模；以及使用所述第一接合连接件和所述第二接合连接件将所述接合结构接合至第三衬底，其中，所述第一接合连接件和所述第二接合连接件延伸穿过形成在所述第三衬底的正面上的第三开口并且接触由所述第三开口而暴露的导电部件。
优选地，所述第一衬底是MEMS晶圆，并且所述第二衬底是盖帽晶圆。
优选地，所述第三衬底是CMOS晶圆。
优选地，所述第一接合连接件形成接合环。
优选地，所述第二接合连接件被所述接合环包围。
优选地，在将所述接合结构接合至所述第三衬底之后，所述第一接合连接件的第一部分沿着所述第一接合连接件的相应的第二部分的侧壁延伸。
优选地，所述第一接合连接件的厚度与所述第二接合连接件的厚度基本相同。
根据本发明的另一方面，提供了一种方法，包括：在第一衬底的背面上形成第一突出部件和第二突出部件；在所述第一突出部件和所述第二突出部件上形成第一导电材料；在所述第一突出部件上形成第一接合连接件的第一部分；在所述第二突出部件上形成第二接合连接件的第一部分；图案化所述第一导电材料以形成所述第一接合连接件的第二部分和所述第二接合连接件的第二部分，其中，所述第一接合连接件的第一部分和所述第二接合连接件的第一部分用作掩模；以及使用所述第一接合连接件和所述第二接合连接件将第二衬底接合至所述第一衬底。
优选地，形成所述第一接合连接件的第一部分包括：
在所述第一导电材料上形成第一图案化的掩模，所述第一图案化的掩模中具有第一开口，所述第一开口暴露所述第一导电材料中设置在所述第一突出部件上的部分；在所述第一开口中形成第二导电材料，所述第二导电材料与所述第一导电材料不同；以及去除所述第一图案化的掩模。
优选地，形成所述第二接合连接件的第一部分包括：在所述第一导电材料上形成第二图案化的掩模，所述第二图案化的掩模中具有第二开口，所述第二开口暴露所述第一导电材料中设置在所述第二突出部件上的部分；在所述第二开口中形成所述第二导电材料；以及去除所述第二图案化的掩模。
优选地，所述第一接合连接件形成接合环。
优选地，所述第二接合连接件被所述接合环包围。
优选地，该方法还包括：在将所述第二衬底接合至所述第一衬底之前，在所述第二衬底的正面上形成第三开口和第四开口，所述第三开口暴露第一导电部件，并且所述第四开口暴露第二导电部件。
优选地，所述第一接合连接件延伸进入所述第三开口并且接触所述第一导电部件，并且所述第二接合连接件延伸进入所述第四开口并且接触所述第二导电部件。
根据本发明的又一方面，提供了一种方法，包括：图案化第一衬底的背面以形成第一突出部件和第二突出部件；在所述第一突出部件上形成第一接合连接件的第二部分，并且在所述第二突出部件上形成第二接合连接件的第二部分；在所述第一接合连接件的第二部分上形成所述第一接合连接件的第一部分，并且在所述第二接合连接件的第二部分上形成所述第二接合连接件的第一部分；以及使用所述第一接合连接件和所述第二接合连接件将第二衬底接合至所述第一衬底。
优选地，形成所述第一接合连接件的第二部分和形成所述第二接合连接件的第二部分包括：在所述第一突出部件和所述第二突出部件上溅射第一导电材料；以及图案化所述第一导电材料。
优选地，形成所述第一接合连接件的第一部分和形成所述第二接合连接件的第一部分包括：通过无电镀方法在所述第一导电材料上形成第二导电材料，所述第二导电材料与所述第一导电材料不同。
优选地，所述第一接合连接件的厚度与所述第二接合连接件的厚度基本相同。
优选地，所述第一接合连接件形成接合环。
优选地，所述第二接合连接件是接合焊盘，所述接合焊盘被所述接合环包围。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各个方面。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1A至图1E、图2A至图2C、图3A和图3B示出了根据一些实施例的制造接合结构的中间阶段的截面图。
图4是示出了根据一些实施例的形成接合结构的方法的流程图。
图5A至图5G、图6A和图6B示出了根据一些实施例的制造接合结构的中间阶段的截面图。
图7是示出了根据一些实施例的形成接合结构的方法的流程图。
图8A至图8E、图9A和图9B示出了根据一些实施例的制造接合结构的中间阶段的截面图。
图10是示出了根据一些实施例的形成接合结构的方法的流程图。
具体实施方式
以下公开内容提供了许多不同实施例或实例，用于实现所提供主题的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。另外，本发明可以在多个实例中重复参考标号和/或字符。这种重复是为了简化和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等空间关系术语以描述如图所示的一个元件或部件与另一元件或部件的关系。除图中所示的方位之外，空间关系术语意欲包括使用或操作过程中的器件的不同的方位。装置可以以其它方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可同样地作相应地解释。
将关于具体的背景(即，通过接合两个或多个晶圆而形成的接合结构)来描述实施例。在一些实施例中，晶圆可以是微机电系统(MEMS)晶圆、互补金属氧化物半导体(CMOS)晶圆等。
图1A至图1E、图2A至图2C、图3A和图3B示出了根据一些实施例的制造接合结构的中间阶段的截面图。具体地，图1A至图1E示出了制备第一接合结构100的中间阶段的截面图，该第一接合结构包括接合至第二晶圆103的第一晶圆101以用于随后的接合工艺。图2A至图2C示出了制备用于随后的接合工艺的第三晶圆200的中间阶段的截面图。图3A和图3B分别示出了根据一些实施例的第二接合结构301和303的截面图，其包括接合至第三晶圆200的第一接合结构100。
首先参考图1A，根据一些实施例，示出了包括接合至第二晶圆103的第一晶圆101的第一接合结构100。在示出的实施例中，可以使用MEMS工艺形成第一晶圆101，并且该第一晶圆可以称为MEMS晶圆101。第二晶圆103可以用作MEMS晶圆101的盖帽(cap)，并且该第二晶圆也可以称为盖帽晶圆103。
在一些实施例中，MEMS晶圆101可以包括衬底和衬底上的各种器件，由于这些器件对于理解下述各个实施例来说不是必要的，所以图1A中没有明确示出这些器件。衬底可以由硅形成，但是其还可以由其他III族、IV族和/或V族元素(诸如，硅、锗、镓、砷、以及它们的组合)形成。衬底也可呈绝缘体上硅(SOI)的形式。SOI衬底可以包括形成在绝缘层(如，埋氧层等)上方的半导体材料层(如，硅、锗等)，其中，绝缘层形成在硅衬底上。另外，可以使用的其他衬底，包括多层衬底、梯度衬底、混合取向衬底、它们的任意组合等。
各种器件可以包括MEMS器件(包括腔体、构件、谐振器、悬臂式元件、压力传感器、加速计、运动传感器、陀螺仪等)并且可以使用传统的MEMS技术来形成。各种器件还可以包括各种有源和无源CMOS器件，包括晶体管、电容器、电阻器、二极管、光电二极管和熔丝等。
在一些实施例中，盖帽晶圆103可以是或可以不是CMOS晶圆，其可以具有或可以不具有电路(未示出)。具体地，盖帽晶圆103可以包括衬底和各种有源和无源CMOS器件，包括晶体管、电容器、电阻器、二极管、光电二极管和熔丝等。在一些实施例中，盖帽晶圆103也可以包括介电层、用于电气布线的导线和通孔。盖帽晶圆103的衬底可以与MEMS晶圆101的衬底类似，因此本文不再重复描述。可选地，盖帽晶圆103可以由包括陶瓷材料、石英等的其他合适的材料形成。
在一些实施例中，在盖帽晶圆103中形成诸如腔体105的腔体。在将盖帽晶圆103接合至MEMS晶圆101之后，腔体105可以用作各个MEMS器件的密封腔体。在一些实施例中，可以使用合适的光刻和蚀刻方法形成腔体105。在图1A中，出于说明的目的，仅示出了单个腔体105。可以根据MEMS晶圆101的设计要求来改变腔体的数量。
还是参考图1A，在一些实施例中，盖帽晶圆103的第一表面103A接合至MEMS晶圆101的第一表面101A以形成第一接合结构100。盖帽晶圆103的腔体105可以与MEMS晶圆101的MEMS器件对准。可以使用诸如熔融接合(如，氧化物与氧化物接合、金属与金属接合、混合接合等)、阳极接合、共晶接合等或它们的组合的任何合适的技术来将MEMS晶圆101接合至盖帽晶圆103。在一些实施例中，可以将由多晶硅或其他合适的材料形成的薄层(未示出)用作接合界面来将MEMS晶圆101熔融接合至盖帽晶圆103。在一些实施例中，当接合工艺可以在低压环境中执行时，在形成第一接合结构100之后，密封的腔体105可以具有低压(高真空)。在其他的实施例中，密封的腔体105可以具有取决于MEMS晶圆101的设计要求的任何合适的压力。
在一些实施例中，可以在形成第一接合结构100之前或之后，减薄MEMS晶圆101，从而使得一个或多个导电部件(未示出)可以暴露在MEMS晶圆101的第二表面101B上。在一些实施例中，减薄工艺可以包括研磨工艺、化学机械抛光(CMP)工艺等。如下文更加详细的描述，将在MEMS晶圆101的第二表面101B上形成接合连接件。在一些实施例中，接合连接件可以不连接至MEMS晶圆101的第二表面101B上的一个或多个导电部件，而是可以用于将接合结构100机械接合至另一晶圆。在其他的实施例中，接合连接件可以连接至MEMS晶圆101的第二表面101B上的一个或多个导电部件，并且可以用于将接合结构100机械接合并且电连接至另一晶圆。
参考图1B，在MEMS晶圆101的第二表面101B上形成导电层107。如下文更加详细的描述，随后图案化导电层107以在MEMS晶圆101的第二表面101B(与第一表面101A相对)上形成接合连接件(例如，诸如图1E中示出的第一接合连接件115A/115B和第二接合连接件117A/117B)，以制备用于随后的接合工艺的MEMS晶圆101。在一些实施例中，接合连接件将用于使MEMS晶圆101接合至第三晶圆200(例如，见图3A和图3B)。导电层107可以包括以下材料的一层或多层：铜、钛、镍、金、锰等或它们的组合，并且可以通过ALD、PVD、蒸发、溅射等或它们的组合来形成。在一些实施例中，导电层107可以具有介于大约2μm和大约4μm之间的厚度T1。在一些实施例中，导电层107包括形成在钛层(具有介于大约和大约之间的厚度)上方的铜层(具有介于大约1.95μm和大约3.9μm之间的厚度)。
参考图1C，在导电层107的暴露的表面上形成图案化的掩模109。在一些实施例中，图案化的掩模109包括光刻胶材料或任何光可图案化的材料。在一些实施例中，沉积、照射(曝光)和显影图案化的掩模109的材料以去除材料的各部分并且形成第一开口111和第二开口113，由此形成图案化的掩模109。在示出的实施例中，第一开口111和第二开口113暴露导电层107的各部分并且限定随后形成的接合连接件(诸如图1E中示出的第一接合连接件115A/115B和第二接合连接件117A/117B)的图案。如下文更加详细的描述，将在第一开口111中形成接合环的第一部分，并且将在第二开口113中形成接合焊盘的第一部分。在示出的实施例中，示出了两个第一开口111。然而，在一些实施例中，自顶向下看，两个第一开口111可以是单个连续开口的部分，并且可以具有圆环形状、矩形环状等。在一些实施例中，第二开口113的顶视图形状可以是圆形、椭圆形、诸如三角形、矩形、六边形等的多边形等。在示出的实施例中，仅仅是出于说明的目的，提供了一定数量的第一开口111和第二开口113。在其他的实施例中，可以根据MEMS晶圆101和第三晶圆200的设计要求来改变第一开口111和第二开口113的数量。
参考图1D，在一些实施例中，分别在第一开口111和第二开口113中形成第一接合连接件115A/115B的第一部分115A和第二接合连接件117A/117B的第一部分117A。在一些实施例中，第一接合连接件115A/115B的第一部分115A和第二接合连接件117A/117B的第一部分117A包括合适的导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合，并且可以使用电化学镀工艺、无电镀工艺等来形成。在一些实施例中，第一接合连接件115A/115B的第一部分115A和第二接合连接件117A/117B的第一部分117A可以具有介于大约0.5μm和大约1μm之间的高度H1。在一些实施例中，第一接合连接件115A/115B的第一部分115A可以具有介于大约30μm和大约70μm之间的宽度W1，并且第二接合连接件117A/117B的第一部分117A可以具有介于大约10μm和大约50μm之间的宽度W2。随后，去除图案化的掩模109以暴露第一接合连接件115A/115B的第一部分115A和第二接合连接件117A/117B的第一部分117A的侧壁。在图案化的掩模109由光刻胶材料形成的一些实施例中，可以例如使用灰化工艺并且之后通过湿清洗工艺来去除图案化的掩模109。
参考图1E，图案化导电层107以形成第一接合连接件115A/115B的第二部分115B和第二接合连接件117A/117B的第二部分117B。在一些实施例中，使用一次或多次蚀刻工艺同时使用第一接合连接件115A/115B的第一部分115A和第二接合连接件117A/117B的第一部分117A作为蚀刻掩模来图案化导电层107。因此，在示出的实施例中，第一接合连接件115A/115B的第二部分115B具有宽度W1，并且第二接合连接件117A/117B的第二部分117B具有宽度W2。此外，第一接合连接件115A/115B的第二部分115B和第二接合连接件117A/117B的第二部分117B具有高度H2，该高度等于导电层107的厚度T1。在导电层107包括形成在钛层上方的铜层的一些实施例中，可以例如使用FeCl3、HCl和H2O的混合物(用于蚀刻铜)以及H2O2、HF和H2O的混合物(用于蚀刻钛)来蚀刻导电层107。
还是参考图1E，第一接合连接件115A/115B和第二接合连接件117A/117B的顶视图形状分别与第一开口111和第二开口113的顶视图形状类似，因此本文不再重复描述。在下文中，第一接合连接件115A/115B也可以称为接合环115A/115B，并且第二接合连接件117A/117B也可以称为接合焊盘117A/117B。如下文更加详细的描述，第一接合连接件115A/115B和第二接合连接件117A/117B将用于使第一接合结构100接合并且电连接至第三晶圆200(例如，见图3A和图3B)。如以上参考图1A至图1E所述，在不图案化MEMS晶圆101的第二表面101B的情况下形成第一接合连接件115A/115B和第二接合连接件117A/117B，这有利地使得以降低的成本形成具有厚度高度一致的接合连接件。
图2A至图2C示出了制备用于随后的接合工艺的第三晶圆200的中间阶段的截面图。首先参考图2A，示出了第三晶圆200的一部分。在一些实施例中，可以使用CMOS工艺形成第三晶圆200，并且该第三晶圆可以称为CMOS晶圆200。在一些实施例中，CMOS晶圆200包括衬底、衬底上的各种有源和无源器件以及衬底上方的各种金属化层，它们在图2A中以层201统一示出。在一些实施例中，CMOS晶圆200的衬底可以与MEMS晶圆101的衬底类似，因此本文不再重复描述。
在一些实施例中，各种有源和无源器件可以包括诸如晶体管的各种n型金属氧化物半导体(NMOS)和/或p型金属氧化物半导体(PMOS)器件、电容器、电阻器、二极管、光电二极管、熔丝等。
金属化层可以包括形成在衬底上方的层间介电层(ILD)/金属间介电层(IMD)。可以通过本领域内已知的任何合适的方法(诸如，旋涂、化学汽相沉积(CVD)、等离子体增强的CVD(PECVD)等)由例如低K介电材料(诸如，磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等)形成ILD/IMD层。
在一些实施例中，例如，可以使用镶嵌工艺、双镶嵌工艺等在ILD/IMD中形成互连结构。可以使用光刻技术来图案化ILD/IMD以形成沟槽和通孔。可以通过使用各种沉积和镀敷方法等在ILD/IMD中的沟槽和通孔中沉积合适的导电材料来形成互连结构。另外，互连结构可以包括一个或多个阻挡/粘合层以保护ILD/IMD免受扩散和金属污染(poisoning)。一个或多个阻挡/粘合层可以包括钛、氮化钛、钽、氮化钽或其他可选材料。可以使用物理汽相沉积(PVD)、ALD、溅射等来形成阻挡层。互连结构的导电材料可以包括铜、铜合金、银、金、钨、钽、铝等。在实施例中，用于形成互连结构的步骤可以包括：毯式形成该一个或多个阻挡/粘合层；沉积薄导电材料晶种层；以及例如通过镀法，利用导电材料填充ILD/IMD中的沟槽和通孔。然后，执行化学机械抛光(CMP)以去除互连结构的多余部分。在一些实施例中，互连结构可以在形成在衬底上的各种无源和有源器件之间提供电连接。
在一些实施例中，可以在金属化层上方形成接触焊盘(未示出)。接触焊盘的形成可以包括毯式沉积导电层并且图案化导电层以形成接触焊盘。接触焊盘可以包括导电材料，诸如铜、钨、铝、银、金等、它们的合金或它们的组合。可以在接触焊盘上方形成钝化层(未示出)，并且图案化该钝化层以暴露接触焊盘的各部分。在一些实施例中，钝化层可以包括介电材料，诸如氮化硅、碳化硅、氧化硅、氮氧化硅等或它们的组合，并且可以使用CVD、PVD、ALD等或它们的组合来形成。在其他的实施例中，钝化层可以包括聚合物，包括(但不限于)聚酰亚胺(PI)、苯并环丁烯(BCB)、聚苯并恶唑(PBO)等或它们的组合，并且可以例如使用旋涂方法等来形成。可以使用合适的光刻和蚀刻方法来图案化钝化层。
还是参考图2A，在接触焊盘上方形成一个或多个再分布层(RDL)203。在一些实施例中，RDL 203可以包括一个或多个介电层205和形成在一个或多个介电层205内的一个或多个导电部件207(例如，诸如导线和通孔)。在一些实施例中，一个或多个介电层205可以包括聚合物，包括(但不限于)聚酰亚胺(PI)、苯并环丁烯(BCB)、聚苯并恶唑(PBO)等或它们的组合，并且可以例如使用旋涂方法等来形成。一个或多个导电部件207可以包括晶种层(未示出)和形成在晶种层上方的导电材料。晶种层可以包括铜、钛、镍、金、锰等或它们的组合，并且可以通过ALD、PVD、溅射等或它们的组合来形成。导电材料包括铜、钨、铝、银、金等或它们的组合，并且可以通过电化学镀工艺、无电镀工艺、ALD、PVD等或它们的组合形成在晶种层上。
在一些实施例中，图案化一个或多个介电层205的最顶部的介电层(未单独示出)以形成第一开口209和第二开口211。在一些实施例中，可以使用合适的光刻方法来图案化一个或多个介电层205的最顶部的介电层。第一开口209和第二开口211暴露一个或多个导电部件207的部分。如下文更加详细的描述，通过将第一接合连接件115A/115B和第二接合连接件117A/117B分别插入第一开口209和第二开口211并且接触一个或多个导电部件207的暴露部分，使MEMS晶圆101与CMOS晶圆200相接合。因此，设计第一开口209和第二开口211的尺寸和形状以容纳第一接合连接件115A/115B和第二接合连接件117A/117B。在一些实施例中，第一开口209和第二开口211的宽度分别大于第一接合连接件115A/115B的宽度W1和第二接合连接件117A/117B的宽度W2。在一些实施例中，第一开口209和第二开口211的高度小于第一接合连接件115A/115B和第二接合连接件117A/117B的高度H1+H2。在其他的实施例中，第一开口209和第二开口211的高度小于第一接合连接件115A/115B的第二部分115B和第二接合连接件117A/117B的第二部分117B的高度H2。
参考图2B，在RDL 203上方以及在第一开口209和第二开口211内毯式形成晶种层213。在一些实施例中，晶种层213可以包括与以上关于图1B所述的导电层107类似的材料并且可以使用与该导电层107类似的方法来形成，因此本文不再重复描述。在一些实施例中，晶种层213可以包括形成在钛层(具有介于大约和大约之间的厚度)上方的铜层(具有介于大约0.5μm和大约2μm之间的厚度)。
参考图2C，去除晶种层213中设置在RDL 203的最顶面上的部分，从而仅保留位于第一开口209和第二开口211内的晶种层213并且形成用于第一接合连接件115A/115B和第二接合连接件117A/117B的凸块下金属层(UBM)213。在一些实施例中，可以例如使用研磨、CMP工艺等去除晶种层213中设置在RDL 203的最顶面上的部分。
图3A示出了根据一些实施例的第二接合结构301的截面图，该接合结构包括接合至图2A所示的CMOS晶圆200的第一接合结构100。在示出的实施例中，在未在第一开口209和第二开口211中形成UBM 213的情况下，将CMOS晶圆200接合至第一接合结构100。在一些实施例中，第一接合结构100的第一接合连接件115A/115B和第二接合连接件117A/117B分别相对于CMOS晶圆200的第一开口209和第二开口211对准。随后，第一接合结构100与CMOS晶圆200接触，从而使得第一接合连接件115A/115B和第二接合连接件117A/117B分别延伸至第一开口209和第二开口211，并且接触RDL 203的相应的暴露的导电部件207。
例如，在第一接合连接件115A/115B的第一部分115A和第二接合连接件117A/117B的第一部分117A由诸如锡(Sn)的焊料形成的一些实施例中，可以执行回流工艺以使焊料成型为期望的连接件形状。在示出的实施例中，在回流工艺之后，第一接合连接件115A/115B的第一部分115A填充第一开口209并且沿着第一接合连接件115A/115B的相应的第二部分115B的侧壁延伸。类似地，第二接合连接件117A/117B的第一部分117A填充第二开口211并且沿着第二接合连接件117A/117B的相应的第二部分117B的侧壁延伸。在示出的实施例中，第一接合连接件115B/115B的第二部分115B和第二接合连接件117A/117B的第二部分117B直接接触RDL203的对应的导电部件207。在其他的实施例中，第一接合连接件115A/115B的第一部分115A的材料可以介于第一接合连接件115A/115B的相应的第二部分115B和RDL203的相应的导电部件207之间。类似地，第二接合连接件117A/117B的第一部分117A的材料可以介于第二接合连接件117A/117B的相应的第二部分117B和RDL 203的相应的导电部件207之间。
还是参考图3A，在一些实施例中，第一接合连接件115A/115B和第二接合连接件117A/117B将第一接合结构100机械连接并且电连接至CMOS晶圆200。在第一接合连接件115A/115B形成接合环的一些实施例中，第一接合连接件115A/115B可以仅提供机械接合并且可以具有电惰性。在这种实施例中，接合环115A/115B可以气密密封MEMS晶圆101的MEMS器件以与外部环境隔离。在其他的实施例中，接合环115A/115B可以电连接至地。在又一些实施例中，接合环115A/115B可以电连接至MEMS晶圆101的MEMS器件并且电连接至CMOS晶圆200的各种有源和无源器件。
图3B示出了根据一些实施例的第二接合结构303的截面图，该接合结构包括接合至图2C所示的CMOS晶圆200的第一接合结构100。在示出的实施例中，在第一开口209和第二开口211中形成UBM 213(例如，见图2B和图2C)之后，将CMOS晶圆200接合至第一接合结构100。在一些实施例中，可以使用与第二接合结构301类似的方法形成第二接合结构303，因此本文不再重复描述。在示出的实施例中，UBM 213介于第一接合连接件115B/115B和RDL203的相应的导电部件207之间，以及介于第二接合连接件117A/117B和RDL 203的相应的导电部件207之间。
图4是示出了根据一些实施例的形成接合结构(诸如第二接合结构301或303)的方法400的流程图。方法400开始于步骤401，其中如以上关于图1A所述，第一晶圆(诸如MEMS晶圆101)接合至第二晶圆(诸如盖帽晶圆103)以形成第一接合结构(诸如第一接合结构100)。在步骤403中，如以上关于图1B所述，在第一晶圆的暴露的表面上形成导电层(诸如导电层107)。在步骤405中，如以上关于图1C所述，在导电层的暴露的表面上形成具有第一开口(诸如第一开口111)和第二开口(诸如第二开口113)的图案化的掩模(诸如图案化的掩模109)。在步骤407中，如以上关于图1D所述，分别在第一开口和第二开口中形成第一接合连接件和第二接合连接件的第一部分(诸如第一接合连接件115A/115B的第一部分115A和第二接合连接件117A/117B的第一部分117A)。在步骤409中，如以上关于图1E所述，图案化导电层以形成第一接合连接件和第二接合连接件的第二部分(诸如第一接合连接件115A/115B的第二部分115B和第二接合连接件117A/117B的第二部分117B)。在一些实施例中，第一接合连接件和第二接合连接件的第一部分可以用作导电层的蚀刻掩模。在步骤411中，如以上关于图3A和图3B所述，使用第一接合连接件和第二接合连接件将第一接合结构接合至第三晶圆(诸如CMOS晶圆200)，以形成第二接合结构(例如，诸如第二接合结构301或303)。
图5A至图5G、图6A和图6B示出了根据一些实施例的制造接合结构的中间阶段的截面图。特别地，图5A至图5G示出了制备第一接合结构500的中间阶段的截面图，该第一接合结构包括用于随后的接合工艺的接合至第二晶圆103的第一晶圆101。图6A和图6B分别示出了根据一些实施例的第二接合结构601和603的截面图，该第二接合结构包括接合至CMOS晶圆200的第一接合结构500。
首先参考图5A，根据一些实施例，示出了包括接合至第二晶圆103的第一晶圆101的第一接合结构500。在一些实施例中，第一接合结构500与以上关于图1A所述的第一接合结构100类似，并且类似的元件用类似标号标记，因此本文不再重复描述。
参考图5B，图案化MEMS晶圆101的第二表面101B以形成第一突出部件501和第二突出部件503。在一些实施例中，可以使用合适的光刻和蚀刻方法来图案化MEMS晶圆101的第二表面101B。在一些实施例中，第一突出部件501和第二突出部件503可以具有介于大约1.5μm和大约2.5μm之间的高度H3。在示出的实施例中，示出了两个第一突出部件501。然而，在一些实施例中，自顶向下看，两个第一突出部件501可以是单个连续突出部件的部分，并且可以具有圆环形状、矩形环状等。在一些实施例中，第二突出部件503的顶视图的形状可以是圆形、椭圆形、诸如三角形、矩形、六边形的多边形等。在示出的实施例中，仅仅出于说明的目的，提供了一定数量的第一突出部件501和第二突出部件503。在其他的实施例中，可以根据MEMS晶圆101的设计要求来改变第一突出部件501和第二突出部件503的数量。如下文更加详细的描述，第一接合连接件511A/511B和第二接合连接件517A/517B(例如，见图5G)将分别形成在第一突出部件501和第二突出部件503上，并且将用于使第一接合结构100接合至CMOS晶圆200。
参考图5C，在MEMS晶圆101的图案化的第二表面101B上共形地形成晶种层505。在一些实施例中，可以使用与以上关于图1B所述的导电层107类似的材料和方法来形成晶种层505，因此本文不再重复描述。在一些实施例中，可以使用电化学镀工艺等来形成晶种层505。在一些实施例中，晶种层505可以具有介于大约和大约之间的厚度T2。在一些实施例中，晶种层505可以包括形成在钛层(具有介于大约和大约之间的厚度)上方的铜层(具有介于大约和大约之间的厚度)。
还是参考图5C，在晶种层505的暴露的表面上形成其中具有第一开口509的第一图案化的掩模507。在一些实施例中，可以使用与以上关于图1C所述的图案化的掩模109类似的材料来形成第一图案化的掩模507，并且可以使用与该图案化的掩模类似的方法来图案化该第一图案化的掩模，因此本文不再重复描述。在示出的实施例中，第一开口509暴露晶种层505中设置在第一突出部件501上的部分。在一些实施例中，第一开口509的顶视图形状可以与以上关于图5B所述的第一突出部件501的顶视图形状类似，因此本文不再重复描述。
参考图5D，在第一开口509中形成第一接合连接件511A/511B(例如，见图5G)的第一部分511A。在一些实施例中，可以使用与以上关于图1D所述的第一接合连接件115A/115B的第一部分115A类似的材料和方法来形成第一接合连接件511A/511B的第一部分511A，因此本文不再重复描述。在示出的实施例中，可以使用电化学镀工艺等来形成第一接合连接件511A/511B的第一部分511A。随后，去除第一图案化的掩模507以暴露第一接合连接件511A/511B的第一部分511A的侧壁。在一些实施例中，可以使用与以上关于图1D所述的图案化的掩模109类似的方法来去除第一图案化的掩模507，因此本文不再重复描述。在一些实施例中，第一接合连接件511A/511B的第一部分511A可以具有介于大约0.2μm和大约1μm之间的高度H4和介于大约30μm和大约70μm之间的宽度W4。
参考图5E，在晶种层505的暴露的表面和第一接合连接件511A/511B的第一部分511A上形成其中具有第二开口515的第二图案化的掩模513。在一些实施例中，可以使用与以上关于图1C所述的图案化的掩模109类似的材料来形成第二图案化的掩模513，并且可以使用与该图案化的掩模类似的方法来图案化该第一图案化的掩模，因此本文不再重复描述。在示出的实施例中，第二开口515暴露晶种层505的设置在第二突出部件503上的部分。在一些实施例中，第二开口515的顶视图形状可以与以上关于图5B所述的第二突出部件503的顶视图形状类似，因此本文不再重复描述。
参考图5F，在第二开口515中形成第二接合连接件517A/517B(例如，见图5G)的第一部分517A。在一些实施例中，可以使用与以上关于图1D所述的第一接合连接件115A/115B的第一部分115A类似的材料和方法来形成第二接合连接件517A/517B的第一部分517A，因此本文不再重复描述。在示出的实施例中，可以使用电化学镀工艺等来形成第二接合连接件517A/517B的第一部分517A。随后，去除第二图案化的掩模513以暴露第一接合连接件511A/511B的第一部分511A和第二接合连接件517A/517B的第一部分517A的侧壁。在一些实施例中，可以使用与以上关于图1D所述的图案化的掩模109类似的方法来去除第二图案化的掩模513，因此本文不再重复描述。在一些实施例中，第二接合连接件517A/517B的第一部分517A可以具有介于大约0.2μm和大约1μm之间的高度H5和介于大约10μm和大约50μm之间的宽度W5。在示出的实施例中，第二接合连接件517A/517B的第一部分517A的高度H5基本等于第一接合连接件511A/511B的第一部分511A的高度H4。在其他的实施例中，第二接合连接件517A/517B的第一部分517A的高度H5与第一接合连接件511A/511B的第一部分511A的高度H4不同。
还是参考图5G，图案化晶种层505以形成第一接合连接件511A/511B的第二部分511B和第二接合连接件517A/517B的第二部分517B。在一些实施例中，可以使用与以上关于图1E所述的导电层107类似的方法来图案化晶种层505，因此本文不再重复描述。因此，在示出的实施例中，第一接合连接件511A/511B的第二部分511B具有宽度W4，并且第二接合连接件517A/517B的第二部分517B具有宽度W5。此外，第一接合连接件511A/511B的第二部分511B和第二接合连接件517A/517B的第二部分517B具有高度H6，该高度等于晶种层505的厚度T2。
还是参考图5G，第一接合连接件511A/511B和第二接合连接件517A/517B的顶视图的形状分别与第一开口509和第二开口515的顶视图形状类似，因此本文不再重复描述。在下文中，第一接合连接件511A/511B也可以称为接合环511A/511B，并且第二接合连接件517A/517B也可以称为接合焊盘517A/517B。如下文更加详细的描述，第一接合连接件511A/511B和第二接合连接件517A/517B将用于使第一接合结构500接合并且电连接至第三晶圆200(例如，见图6A和图6B)。如以上关于图5A至图5G所述，在不同的工艺步骤期间，分别使用第一图案化的掩模507和第二图案化的掩模513来形成第一接合连接件511A/511B和第二接合连接件517A/517B。由于在每一个工艺步骤期间填充具有类似形状和大小的开口(诸如第一开口509或第二开口515)，从而有利地形成厚度高度一致的接合连接件。
图6A示出了根据一些实施例的第二接合结构601的截面图，该第二接合结构包括接合至图2A所示的CMOS晶圆200的第一接合结构500。在示出的实施例中，在未在第一开口209和第二开口211内形成UBM 213的情况下，将CMOS晶圆200接合至第一接合结构500。在一些实施例中，第一接合结构500的第一接合连接件511A/511B和第二接合连接件517A/517B分别相对于CMOS晶圆200的第一开口209和第二开口211(见图2A)对准。随后，第一接合结构500与CMOS晶圆200相接触，从而使得第一接合连接件511A/511B和第二接合连接件517A/517B分别延伸至第一开口209和第二开口211内，并且接触RDL 203的相应暴露的导电部件207。
例如，在第一接合连接件511A/511B的第一部分511A和第二接合连接件517A/517B的第一部分517A由诸如锡(Sn)的焊料形成的一些实施例中，可以在低于焊料的回流温度的温度条件下执行接合工艺。在这种实施例中，第一接合连接件511A/511B的第一部分511A和第二接合连接件517A/517B的第一部分517A未改变形状，并且例如使用扩散焊接方法使第一接合连接件511A/511B的第一部分511A和第二接合连接件517A/517B的第一部分517A接合至RDL 203的相应的导电部件207。在其他的实施例中，可以使用如以上关于图3A所述的回流工艺来将第一接合连接件511A/511B和第二接合连接件517A/517B接合至RDL 203的相应的导电部件207，因此本文不再重复描述。在一些实施例中，第一接合连接件511A/511B和第二接合连接件517A/517B将第一接合结构500机械连接并且电连接至CMOS晶圆200。在第一接合连接件511A/511B形成接合环的一些实施例中，第一接合连接件511A/511B可以仅提供机械接合并且可以具有电惰性。在这种实施例中，接合环511A/511B可以气密密封MEMS晶圆101的MEMS器件以与外部环境隔离。在其他的实施例中，接合环511A/511B可以电连接至地。在又一些实施例中，接合环511A/511B可以电连接至MEMS晶圆101的MEMS器件并且电连接至CMOS晶圆200的各种有源和无源器件。
图6B示出了根据一些实施例的第二接合结构603的截面图，该第二接合结构包括接合至图2C所示的CMOS晶圆200的第一接合结构500。在示出的实施例中，在第一开口209和第二开口211中形成UBM 213(例如，见图2C)之后，将CMOS晶圆200接合至第一接合结构500。在一些实施例中，可以使用与以上关于图6A所述的第二接合结构601类似的方法来形成第二接合结构603，因此本文不再重复描述。在示出的实施例中，UBM 213介于第一接合连接件511A/511B和RDL 203的相应的导电部件207之间，以及介于第二接合连接件517A/517B和RDL 203的相应的导电部件207之间。
图7是示出了根据一些实施例的形成接合结构(诸如第二接合结构601或603)的方法700的流程图。方法700开始于步骤701，其中如以上关于图5A所述，第一晶圆(诸如MEMS晶圆101)接合至第二晶圆(诸如盖帽晶圆103)以形成第一接合结构(诸如第一接合结构500)。在步骤703中，如以上关于图5B所述，图案化第一晶圆的暴露的表面以形成第一突出部件和第二突出部件(诸如第一突出部件501和第二突出部件503)。在步骤705中，如以上关于图5C所述，在第一晶圆的图案化的表面上形成导电层(诸如晶种层505)。在步骤707中，如以上关于图5C所述，在导电层的暴露的表面上形成具有第一开口(诸如第一开口509)的第一图案化的掩模(诸如第一图案化的掩模507)。在步骤709中，如以上关于图5D所述，在第一开口中形成第一接合连接件的第一部分(诸如第一接合连接件511A/511B的第一部分511A)。在步骤711中，如以上关于图5E所述，在导电层的暴露的表面和第一接合连接件的第一部分上形成具有第二开口(诸如第二开口515)的第二图案化的掩模(诸如第二图案化的掩模513)。在步骤713中，如以上关于图5F所述，在第二开口中形成第二接合连接件的第一部分(诸如第二接合连接件517A/517B的第一部分517A)。在步骤715中，如以上关于图5G所述，图案化导电层以形成第一接合连接件和第二接合连接件的第二部分(诸如第一接合连接件511A/511B的第二部分511B和第二接合连接件517A/517B的第二部分517B)。在一些实施例中，第一接合连接件和第二接合连接件的第一部分可以用作导电层的蚀刻掩模。在步骤717中，如以上关于图6A和图6B所述，使用第一接合连接件和第二接合连接件将第一接合结构接合至第三晶圆(诸如CMOS晶圆200)，以形成第二接合结构(例如，诸如第二接合结构601或603)。
图8A至图8E、图9A和图9B示出了根据一些实施例的制造接合结构的中间阶段的截面图。具体地地，图8A至图8E示出了制备第一接合结构800的中间阶段的截面图，该第一接合结构包括用于随后的接合工艺的接合至第二晶圆103的第一晶圆101。图9A和图9B分别示出了根据一些实施例的第二接合结构901和903的截面图，其包括接合至CMOS晶圆200的第一接合结构800。
首先参考图8A，根据一些实施例，示出了包括接合至第二晶圆103的第一晶圆101的第一接合结构800。在一些实施例中，第一接合结构800与以上关于图1A所述的第一接合结构100类似，并且类似元件用类似标号来标记，因此本文不再重复描述。
图8B示出了在图案化MEMS晶圆101的第二表面101B以形成第一突出部件501和第二突出部件503之后的第一接合结构800。在一些实施例中，图8B中示出的第一接合结构800与以上关于图5B所述的第一接合结构500类似，并且类似元件用类似标号来标记，因此本文不再重复描述。如下文更加详细的描述，第一接合连接件805A/805B和第二接合连接件807A/807B(例如，见图8E)将分别形成在第一突出部件501和第二突出部件503上，并且将用于使第一接合结构800接合至CMOS晶圆200。
参考图8C，在MEMS晶圆101的图案化的第二表面101B上共形地形成晶种层801。在示出的实施例中，可以使用溅射等来形成晶种层801。在其他的实施例中，可以使用与以上关于图1B所述的导电层107类似的材料和方法来形成晶种层801，因此本文不再重复描述。在一些实施例中，晶种层801可以具有介于大约和大约之间的厚度T3。在一些实施例中，晶种层801可以包括形成在钛层(具有介于大约和大约之间的厚度)上方的铜层(具有介于大约和大约之间的厚度)。
还是参考图8C，在晶种层801的暴露的表面上形成图案化的掩模803。在一些实施例中，可以使用与以上关于图1C所述的图案化的掩模109类似的材料和方法来形成并且图案化图案化的掩模803，因此本文不再重复描述。在示出的实施例中，图案化的掩模803保护晶种层801的设置在第一突出部件501和第二突出部件503上的部分。
参考图8D，去除晶种层801的暴露部分以在第一突出部件501上形成第一接合连接件805A/805B的第二部分805B并且在第二突出部件503上形成第二接合连接件807A/807B的第二部分807B。在一些实施例中，可以使用与以上关于图1E所述的导电层107类似的方法来图案化晶种层801，因此本文不再重复描述。因此，在示出的实施例中，第二部分805B和807B具有高度H7，该高度等于晶种层801的厚度T3。在一些实施例中，第二部分805B可以具有介于大约30μm和大约50μm之间的宽度W7，并且第二部分807B可以具有介于大约10μm和大约50μm之间的宽度W8。
参考图8E，第一部分805A形成在第二部分805B上以形成第一接合连接件805A/805B，并且第一部分807A形成在第二部分807B上以形成第二接合连接件807A/807B。在示出的实施例中，可以使用无电镀工艺等来形成第一部分805A和807A。因此，第一部分805A具有宽度W7，并且第一部分807A具有宽度W8。在一些实施例中，第一部分805A和807A具有介于大约0.2μm和大约1μm之间的高度H8。
还是参考图8E，第一接合连接件805A/805B和第二接合连接件807A/807B的顶视图形状分别与以上关于图5B所述的第一突出部件501和第二突出部件503的顶视图的形状类似，因此本文不再重复描述。在下文中，第一接合连接件805A/805B也可以称为接合环805A/805B，并且第二接合连接件807A/807B也可以称为接合焊盘807A/807B。如下文更加详细的描述，第一接合连接件805A/805B和第二接合连接件807A/807B将用于使第一接合结构800接合并且电连接至第三晶圆200(例如，见图9A和图9B)。如以上关于图8A至图8E所述，使用溅射形成晶种层801，而使用无电镀工艺来形成第一部分805A和807A，这有利地形成厚度高度一致的接合连接件。
图9A示出了根据一些实施例的第二接合结构901的截面图，该第二接合结构包括接合至图2A所示的CMOS晶圆200的第一接合结构800。在一些实施例中，可以使用与以上关于图6A所述的第二接合结构601类似的方法来形成第二接合结构901，因此本文不再重复描述。
图9B示出了根据一些实施例的第二接合结构903的截面图，该第二接合结构包括接合至图2C所示的CMOS晶圆200的第一接合结构800。在示出的实施例中，在第一开口209和第二开口211中形成UBM 213(见图2B和图2C)之后，将CMOS晶圆200接合至第一接合结构800。在一些实施例中，可以使用与以上关于图6B所述的第二接合结构603类似的方法来形成第二接合结构903，因此本文不再重复描述。
图10是示出了根据一些实施例的形成接合结构(诸如第二接合结构901或903)的方法1000的流程图。方法1000开始于步骤1001，其中如以上关于图8A所述，第一晶圆(诸如MEMS晶圆101)接合至第二晶圆(诸如盖帽晶圆103)以形成第一接合结构(诸如第一接合结构800)。在步骤1003中，如以上关于图8B所述，图案化第一晶圆的暴露的表面以形成第一突出部件和第二突出部件(诸如第一突出部件501和第二突出部件503)。在步骤1005中，如以上关于图8C所述，在第一晶圆的图案化的表面上形成导电层(诸如导电层801)。在步骤1007中，如以上关于图8C和图8D所述，图案化导电层以形成第一接合连接件和第二接合连接件的第二部分(诸如第一接合连接件805A/805B的第二部分805B和第二接合连接件807A/807B的第二部分807B)。在步骤1009中，如以上关于图8E所述，第一接合连接件的第一部分(诸如第一接合连接件805A/805B的第一部分805A)形成在第一接合连接件的相应的第二部分上，并且第二接合连接件的第一部分(诸如第二接合连接件807A/807B的第一部分807A)形成在第二接合连接件的相应的第二部分上。在步骤1011中，如以上关于图9A和图9B所述，使用第一接合连接件和第二接合连接件将第一接合结构接合至第三晶圆(诸如CMOS晶圆200)，以形成第二接合结构(例如，诸如第二接合结构901或903)。
本文中的实施例提供各种益处，诸如接合连接件的厚度高度一致和降低成本。在一些实施例中，在接合连接件的形成期间，避免了晶圆的图案化，这有利地以降低的成本形成厚度高度一致的接合连接件。在一些实施例中，采用两个掩模的方法使得接合环阶段与接合焊盘阶段分离，这有利地形成厚度高度统一的接合连接件。在一些实施例中，在接合连接件的形成期间使用诸如溅射和无电镀的沉积工艺，这有利地形成厚度高度一致的接合连接件。
根据实施例，一种方法包括在接合结构的第一表面上形成导电层，接合结构包括接合至第二衬底的第一衬底，接合结构的第一表面是第一衬底的暴露的表面。在导电层上形成图案化的掩模，图案化的掩模包括第一开口和第二开口，第一开口和第二开口暴露导电层的一部分。在第一开口中形成第一接合连接件的第一部分，并且在第二开口中形成第二接合连接件的第一部分。图案化导电层以形成第一接合连接件的第二部分和第二接合连接件的第二部分，其中第一接合连接件的第一部分和第二接合连接件的第一部分用作掩模。使用第一接合连接件和第二接合连接件将接合结构接合至第三衬底，其中第一接合连接件和第二接合连接件延伸穿过形成在第三衬底的前面上的第三开口并且接触由第三开口暴露的导电部件。
根据另一实施例，一种方法包括在第一衬底的背面上形成第一突出部件和第二突出部件。在第一突出部件和第二突出部件上形成第一导电材料。在第一突出部件上形成第一接合连接件的第一部分。在第二突出部件上形成第二接合连接件的第一部分。图案化第一导电材料以形成第一接合连接件的第二部分和第二接合连接件的第二部分，其中第一接合连接件的第一部分和第二接合连接件的第一部分用作掩模。使用第一接合连接件和第二接合连接件将第二衬底接合至第一衬底。
根据又一实施例，方法包括图案化第一衬底的背面以形成第一突出部件和第二突出部件。在第一突出部件上形成第一接合连接件的第二部分，并且在第二突出部件上形成第二接合连接件的第二部分。在第一接合连接件的第二部分上形成第一接合连接件的第一部分，并且在第二接合连接件的第二部分上形成第二接合连接件的第一部分。使用第一接合连接件和第二接合连接件将第二衬底接合至第一衬底。
上面论述了若干实施例的部件，使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (17)

1.一种形成堆叠半导体器件的方法，包括：
在接合结构的第一表面上形成导电层，所述接合结构包括接合至第二衬底的第一衬底，所述接合结构的第一表面是所述第一衬底的暴露的表面；
在所述导电层上形成图案化的掩模，所述图案化的掩模包括第一开口和第二开口，所述第一开口和所述第二开口暴露所述导电层的一部分；
在所述第一开口中形成第一接合连接件的第一部分，并且在所述第二开口中形成第二接合连接件的第一部分；
图案化所述导电层以形成所述第一接合连接件的第二部分和所述第二接合连接件的第二部分，其中，所述第一接合连接件的第一部分和所述第二接合连接件的第一部分用作掩模；以及
使用所述第一接合连接件和所述第二接合连接件将所述接合结构接合至第三衬底，其中，所述第一接合连接件和所述第二接合连接件延伸穿过形成在所述第三衬底的正面上的第三开口并且接触由所述第三开口而暴露的导电部件，
其中，通过无电镀方法形成所述第一接合连接件的第一部分和所述第二接合连接件的第一部分，
其中，所述第一接合连接件形成接合环以气密密封所述第一衬底中的器件。
2.根据权利要求1所述的方法，其中，所述第一衬底是MEMS晶圆，并且所述第二衬底是盖帽晶圆。
3.根据权利要求2所述的方法，其中，所述第三衬底是CMOS晶圆。
4.根据权利要求1所述的方法，其中，所述第二接合连接件被所述接合环包围。
5.根据权利要求1所述的方法，其中，在将所述接合结构接合至所述第三衬底之后，所述第一接合连接件的第一部分沿着所述第一接合连接件的相应的第二部分的侧壁延伸。
6.根据权利要求1所述的方法，其中，所述第一接合连接件的厚度与所述第二接合连接件的厚度基本相同。
7.一种形成堆叠半导体器件的方法，包括：
在第一衬底的背面上形成第一突出部件和第二突出部件；
在所述第一突出部件和所述第二突出部件上形成第一导电材料；
在所述第一突出部件上通过无电镀方法形成第一接合连接件的第一部分；
在所述第二突出部件上通过所述无电镀方法形成第二接合连接件的第一部分；
图案化所述第一导电材料以形成所述第一接合连接件的第二部分和所述第二接合连接件的第二部分，其中，所述第一接合连接件的第一部分和所述第二接合连接件的第一部分用作掩模；以及
使用所述第一接合连接件和所述第二接合连接件将第二衬底接合至所述第一衬底，
其中，所述第一接合连接件的第一部分和所述第二接合连接件的第一部分分别通过第一图案化的掩模和第二图案化的掩模形成，
其中，所述第一接合连接件形成接合环以气密密封所述第一衬底中的器件。
8.根据权利要求7所述的方法，其中，形成所述第一接合连接件的第一部分包括：
在所述第一导电材料上形成所述第一图案化的掩模，所述第一图案化的掩模中具有第一开口，所述第一开口暴露所述第一导电材料中设置在所述第一突出部件上的部分；
在所述第一开口中形成第二导电材料，所述第二导电材料与所述第一导电材料不同；以及
去除所述第一图案化的掩模。
9.根据权利要求8所述的方法，其中，形成所述第二接合连接件的第一部分包括：
在所述第一导电材料上形成所述第二图案化的掩模，所述第二图案化的掩模中具有第二开口，所述第二开口暴露所述第一导电材料中设置在所述第二突出部件上的部分；
在所述第二开口中形成所述第二导电材料；以及
去除所述第二图案化的掩模。
10.根据权利要求7所述的方法，其中，所述第二接合连接件被所述接合环包围。
11.根据权利要求7所述的方法，还包括：在将所述第二衬底接合至所述第一衬底之前，在所述第二衬底的正面上形成第三开口和第四开口，所述第三开口暴露第一导电部件，并且所述第四开口暴露第二导电部件。
12.根据权利要求11所述的方法，其中，所述第一接合连接件延伸进入所述第三开口并且接触所述第一导电部件，并且所述第二接合连接件延伸进入所述第四开口并且接触所述第二导电部件。
13.一种形成堆叠半导体器件的方法，包括：
图案化第一衬底的背面以形成第一突出部件和第二突出部件；
在所述第一突出部件上形成第一接合连接件的第二部分，并且在所述第二突出部件上形成第二接合连接件的第二部分；
通过无电镀方法，在所述第一接合连接件的第二部分上形成所述第一接合连接件的第一部分，并且在所述第二接合连接件的第二部分上形成所述第二接合连接件的第一部分，其中，所述第一接合连接件的第一部分和所述第二接合连接件的第一部分分别通过不同的图案化的掩模形成；以及使用所述第一接合连接件和所述第二接合连接件将第二衬底接合至所述第一衬底，
其中，所述第一接合连接件形成接合环以气密密封所述第一衬底中的器件。
14.根据权利要求13所述的方法，其中，形成所述第一接合连接件的第二部分和形成所述第二接合连接件的第二部分包括：
在所述第一突出部件和所述第二突出部件上溅射第一导电材料；以及
图案化所述第一导电材料。
15.根据权利要求14所述的方法，其中，形成所述第一接合连接件的第一部分和形成所述第二接合连接件的第一部分包括：通过所述无电镀方法在所述第一导电材料上形成第二导电材料，所述第二导电材料与所述第一导电材料不同。
16.根据权利要求13所述的方法，其中，所述第一接合连接件的厚度与所述第二接合连接件的厚度基本相同。
17.根据权利要求13所述的方法，其中，所述第二接合连接件是接合焊盘，所述接合焊盘被所述接合环包围。
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