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TWI553749B - 封裝結構及其形成方法 - Google Patents

封裝結構及其形成方法 Download PDF

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Publication number
TWI553749B
TWI553749B TW103145535A TW103145535A TWI553749B TW I553749 B TWI553749 B TW I553749B TW 103145535 A TW103145535 A TW 103145535A TW 103145535 A TW103145535 A TW 103145535A TW I553749 B TWI553749 B TW I553749B
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TW
Taiwan
Prior art keywords
layer
opening
wafer
dielectric layer
contact pad
Prior art date
Application number
TW103145535A
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English (en)
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TW201533811A (zh
Inventor
施婉婷
劉乃瑋
林俊成
黃震麟
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台灣積體電路製造股份有限公司
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Publication of TW201533811A publication Critical patent/TW201533811A/zh
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Publication of TWI553749B publication Critical patent/TWI553749B/zh

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Description

封裝結構及其形成方法
本發明係關於一種封裝結構，特別是關於一種扇出封裝結構及其形成方法。
半導體裝置被使用於各種電子應用中，例如個人電腦、手機、數位相機、及其他電子設備。半導體裝置通常經由依次地沉積絕緣或介電層、導電層、及半導體層的材料於半導體基板上，且利用微影製程圖案化上述各種材料層，以在其上形成電路部件及元件。數十或數百個積體電路通常製造於單一半導體晶圓上。沿著切割線切割積體電路，令使個別的晶片被單一化。接著，舉例來說，這些個別的晶片被分別封裝在多晶片模組或其他封裝類型中。
藉由在最小特徵尺寸上的持續減少，半導體工業持續改良各種電子部件的集成度(例如：電晶體、二極體、電阻器、電容器等)，以容許更多部件被整合於一給定區域中。在一些應用中，這些較小的電子部件，例如積體電路晶片，亦可要求較小的封裝結構，以利用於比以往封裝結構更小的區域。
本發明之一態樣在於提供一種封裝結構。此封裝結構包含具有基板及接觸墊位於基板上的晶片及側向包覆晶片的模製化合物。第一介電層形成覆蓋模製化合物及晶片，且具有第一開口暴露接觸墊。第一金屬化層形成覆蓋第一介電層，其中第一金屬化層填充第一開口。第二介電層形成覆蓋第一金屬化層及第一介電層，且具有第二開口位於第一開口之上。第二金屬化層形成覆蓋第二介電層且形成在第二開口之內。
本發明之另一態樣在於提供一種封裝結構。此封裝結構包含具有基板及接觸墊位於基板上的晶片，及側向包覆晶片的模製化合物。第一介電層形成覆蓋模製化合物及晶片，且具有第一開口暴露接觸墊。第一晶種層形成覆蓋第一介電層，且內襯於第一開口的側壁及底部。第一導電層形成覆蓋第一晶種層，且填充第一開口。第二介電層形成覆蓋第一導電層，且具有第二開口直接位於第一開口之上。第二晶種層形成覆蓋第二介電層，且內襯於第二開口的側壁及底部。第二導電層形成覆蓋第二晶種層。
本發明之又一態樣在於提供一種方法。此方法包含：提供晶片，其具有接觸墊；形成模製化合物側向包覆晶片，且接觸墊被模製化合物所暴露；形成第一介電層於模製化合物及晶片之上；形成第一開口於第一介電層中，以暴露接觸墊；形成第一導電層覆蓋第一介電層，且填充第一開 口，其中第一導電層在第一開口中具有平坦表面；形成第二介電層於第一導電層及第一介電層之上；形成第二開口在第二介電層中，以暴露位於第一開口上的第一導電層；以及形成第二導電層覆蓋於第二介電層上，且通過第二開口物理接觸第一導電層。
10‧‧‧晶片
10B‧‧‧後側(第二側)
10F‧‧‧前側(第一側)
12‧‧‧基板
14‧‧‧接觸墊
16‧‧‧鈍化層
16a、30a、40a‧‧‧開口
18‧‧‧模製化合物
200‧‧‧載板
202‧‧‧黏合膜
204‧‧‧膠帶
30‧‧‧第一介電層
32‧‧‧第一金屬化層
32a‧‧‧第一晶種層
32b‧‧‧第一導電層
32s‧‧‧平坦金屬表面
34‧‧‧第一連接通道
40‧‧‧第二介電層
42‧‧‧第二金屬化層
42a‧‧‧第二晶種層
42b‧‧‧第二導電層
44‧‧‧第二連接通道
50‧‧‧凸塊
50a‧‧‧頂部
52‧‧‧保護層
W‧‧‧寬度
H‧‧‧高度
為了更完整了解本發明之實施例及其優點，請參考配合附圖的以下敘述，其中：第1至8圖係根據本發明之一實施例在一製造方法中的各種結構剖面圖。
本實施例的製造和使用方法皆詳細討論如後。然而，可以理解的是，本發明提供了可在各種特定背景下表現的許多可適用的發明概念。所討論的具體實施例僅僅是為製造或使用本發明之主題的具體說明方式，並不限制本發明在不同實施例的範圍。
實施例係描述相對於一個特定情況，即一個扇出封裝結構。然而，其它實施例亦可被應用於其他封裝結構。圖式及以下的討論說明被簡化的結構，以不模糊各種特徵，並省略多餘的特徵。如此，對於所屬技術領域中具有通常知識者而言將是明確的。像圖式中的元件編號指代相同的元件。雖然方法實施例可被描述為以特定順序進行，但是其 他實施例則可以任何合理的順序進行。
第1至8圖係根據本發明之一實施例在一製造方法中的各種結構剖面圖。
第1圖說明二晶片10藉由黏合膜202黏附於載板200上。在一實施例中，諸晶片10係形成於晶圓的一部分，且晶圓接著被切割形成個別的晶片10。舉例來說，諸晶片10可為邏輯積體電路、記憶體晶片、模擬晶片、或其他任意晶片。每一晶片10包含基板12、位於基板12上的接觸墊14、及覆蓋基板12及接觸墊14的鈍化層16。基板12可包含半導體基板，例如體半導體基板(bulk semiconductor substrate)、絕緣體上半導體基板(semiconductor-on-insulator substrate)或其類，其上的電性電路包含主動裝置(例如電晶體)，及/或被動裝置(例如電容器、感應器或其類)，係根據半導體製程所形成。形成在半導體基板內的電性電路可為適合於特定應用之任何類型的電路。舉例來說，電性電路可包含各種N型金屬氧化物半導體(NMOS)及/或P型金屬氧化物半導體(PMOS)裝置，例如電晶體、電容器、電阻器、二極體、光電二極體、保險絲或其類，互聯以進行一或多種功能。這些功能可利用多種結構被執行，而這些結構包含記憶體結構、處理器結構、感測器、放大器、配電器、輸入/輸出電路、或其類。其他電路可適合被用於給定的應用。介電層及金屬線形成於上述電子電路中。舉例來說，介電層可由低介電係數(low-K)之介電材料所形成，例如磷矽玻璃(PSG)、硼磷矽 玻璃(BPSG)、氟矽玻璃(FSG)、SiOxCy、旋塗玻璃(SOG)、旋塗聚合物(SOP)、矽碳材料、上述材料之化合物、上述材料之複合物、上述材料之組合、或其類，且藉由任何適合的方法，例如旋轉法、化學氣相沉積法(CVD)、及/或電漿輔助化學氣相沉積法(PECVD)。由例如銅、鎢、鋁及/或其合金所形成的金屬線係形成於介電層中，且電性耦合於上述電子電路及/或接觸墊14。
接觸墊14形成在基板12中最上層的介電層之上，以電性連接於底層的金屬化層。在一些實施例中，接觸墊14係由鋁、鋁銅、鋁合金、銅、銅合金或其類所形成。鈍化層16形成於基板12之上表面之上，且圖案化形成開口16a以暴露至少一部分的接觸墊14。鈍化層16可為單一層或層疊的多層結構。在一些實施例中，鈍化層16係由介電材料所形成，例如無摻雜矽玻璃(USG)、氮化矽、氧化矽、氮氧化矽、或無孔洞材料。在一些實施例中，鈍化層16係藉由化學氣相沉積法(CVD)、物理氣相沉積法(PVD)、或其他任何適合的製程所形成。
在一實施例中，諸晶片10係利用例如拾取和放置工具放置在載板200上，且諸晶片10係藉由黏合膜202黏合於載板200，例如任何適合的黏著劑，例如紫外光膠(當被紫外光曝照時，此膠會失去其黏合特性)、或線上膜(film on wire,FOW)材料。載板200可為晶圓狀基板或面板狀基板。依據晶片10的尺寸、載板200的尺寸及特定的用途，數十個晶片10或數百個晶片10或更多可黏附於載板200。晶片 10具有第一側10F(在此也稱作前側10F)及第二側10B(在此也稱作後側10B)。在一些實施例中，藉著放置諸晶片10於載板200上的預定位置，晶片10的後側10B係黏附於黏合膜202，令使晶片10係面朝上地安裝在載板200上。
在第2圖中，形成模製化合物18至少側向包覆晶片10。其係指，藉由側向包覆，模製化合物係形成以各方圍繞晶片，但不延伸至晶片之上表面之上。模製化合物18形成以填充諸晶片10之間的間隙。模製化合物18可利用壓縮模塑法、層壓法或其類而形成。模製化合物18可為具有環氧基團的複合物或其類。舉例來說，模製化合物18可利用恆溫或介於120℃至340℃的傾斜升溫熱製程以固化。模製化合物18可先覆蓋所形成的晶片10，例如延伸至晶片10的上表面之上，接著經由磨削製程以暴露犧牲層(未繪示)於晶片10上。犧牲層可利用溶劑、化學品、或其類移除。在一實施例中，濕蝕刻對於犧牲層的選擇性係用以移除犧牲層，例如稀釋的氫氧化鉀溶液，其舉例來說為約3%至約5%的氫氧化鉀。在一些實施例中，諸晶片10的前側10F不為模製化合物18所覆蓋，以暴露接觸墊14及鈍化層16。在一實施例中，鈍化層16的上表面低於模製化合物18的上表面。在一些實施例中，鈍化層16的上表面大致與模製化合物18的上表面齊平。
請參考第3圖，第一介電層30形成於諸晶片10的鈍化層16及接觸墊14之上，且覆蓋模製化合物18。在一些實施例中，第一介電層30包含聚苯噁唑(polybenzoxazole, PBO)層、聚醯亞胺(polyimide)層、苯並環丁烯(benzocyclobutene,BCB)層、環氧化合物層、感光材料層、其他適合的高分子材料、或其組合。第一介電層30可藉由旋轉塗佈製程、層壓製程、其類似製程或其組合沉積而成。接著第一介電層30係藉由微影及/或蝕刻製程而圖案化，以形成開口30a，藉以暴露底層的接觸墊14。在至少一些實施例中，開口30a係設置在鈍化層16的開口16a之上。在已說明的實施例中，開口30a的尺寸(例如直徑)小於開口16a的尺寸。在其他預想的實施例中，開口30a的尺寸可大於或等於開口16a的尺寸。
在第4圖中，第一金屬化層32形成於第一介電層30上作為各種痕跡，且第一金屬化層32填充開口30a以形成複數個第一連接通道34直接位於個別接觸墊14上。在一些實施例中，當自頂巷下來看時，第一連接通道34可為環狀、類環狀、矩形狀、正方形狀、三角形狀、六角形狀、八角形狀、或其類。再者，第一連接通道34可為封閉狀、破碎或斷開狀。在一實施例中，第一金屬化層32包含第一晶種層32a及第一導電層32b。舉例來說，第一晶種層32a沉積於第一介電層30上，且內襯於第一介電層30的開口30a的底部及側壁。第一晶種層32a可為銅、鈦、氮化鈦、銅與鈦的組合、其類似材料、或其組合，且藉由原子層沉積法(ALD)、濺射法、其他物理氣相沉積法(PVD)或其類所沉積而成。第一導電層32b形成於第一晶種層32a上，且填充第一介電層30的開口30a。第一導電層32b可為銅、銅合金、 鋁、鋁合金、鎢、鎢合金、或其組合，且藉由電鍍製程所形成，例如化學鍍法、電鍍法、或其類。在一實施例中，進行銅電鍍製程係修改添加劑的選擇及控制銅溶液濃度，令使在開口30a中第一導電層32b的表面形成平坦金屬表面325。舉例來說，銅電鍍製程係在電鍍速率大於約1微米/分鐘下進行。第一導電層32b形成於開口30a之內，其具有寬度(W)及高度(H)。舉例來說，高度(H)小於10微米。高度(H)可為約3微米。在一實施例中，寬高比(W/H)大於約2。在另一實施例中，寬高比(W/H)小於約20。在又一實施例中，寬高比(W/H)介於2至20之間。其次，進行微影及蝕刻製程以圖案化第一導電層32b及第一晶種層32a，以形成所期望的第一金屬化層32之圖案。第一金屬化層32為後鈍化互聯(PPI)結構，且後鈍化互聯結構可作為互聯層、電源線、重新分佈線(RDL)、感應器、電容器或任何被動元件。
在第5圖中，第二介電層40形成於第一介電層30及第一金屬化層32上。在一些實施例中，第二介電層40包含聚苯噁唑(polybenzoxazole,PBO)層、聚醯亞胺(polyimide)層、苯並環丁烯(benzocyclobutene,BCB)層、環氧化合物層、感光材料層、其他適合的高分子材料、或其組合。第二介電層40可藉由旋轉塗佈製程、層壓製程、其類似製程或其組合沉積而成。接著第二介電層40係藉由微影及/或蝕刻製程而圖案化，以形成開口40a，藉以暴露部分底層的第一金屬化層32。在至少一些實施例中，由於開口40a設置於第一介電層30的開口30a上，因此第一連接通道34 暴露於開口40a。舉例來說，開口40a的尺寸大致等於開口30a的尺寸。開口40a的尺寸可大於或小於開口30a的尺寸。
接下來，如第6圖所示，第二金屬化層42形成於第二介電層40上作為各種痕跡或連接墊，且第二金屬化層42形成在開口40a中，以形成複數個第二連接通道44直接位於個別第一連接通道34上。在一些實施例中，第二連接通道44可為環狀、類環狀、矩形狀、正方形狀、三角形狀、六角形狀、八角形狀、或其類。再者，第二連接通道44可為封閉狀、破碎或斷開狀。在一實施例中，第二金屬化層42包含第二晶種層42a及第二導電層42b。舉例來說，第二晶種層42a沉積於第二介電層40上，且內襯於第二介電層40的開口40a的底部及側壁。第二晶種層42a可為銅、鈦、氮化鈦、銅與鈦的組合、其類似材料、或其組合，且藉由原子層沉積法(ALD)、濺射法、其他物理氣相沉積法(PVD)或其類所沉積而成。第二導電層42b形成於第二晶種層42a上。第二導電層42b亦可形成於第二介電層40的開口40a之內。依據開口尺寸及電鍍製程的控制，第二導電層42b可部分填充於開口40a(如第6圖所示)或完全填充於開口40a(未繪示)。第二導電層42b可為銅、銅合金、鋁、鋁合金、鎢、鎢合金、或其組合，且藉由電鍍製程所形成，例如化學鍍法、電鍍法、或其類。其次，進行微影及蝕刻製程以圖案化第二導電層42b及第二晶種層42a，以暴露所期望的第二金屬化層42之圖案。第二金屬化層42包含第二連接通道44電性耦合於第一連接通道34。第二金屬化層42可作為互聯 層、電源線、重新分佈線(RDL)、感應器、電容器或任何被動元件。當第二連接通道44與第一連接通道34以垂直對齊表示時，例如第二連接通道44偏移於第一連接通道34的其他設置皆在本發明之預想範圍之內。
請參考第7圖，凸塊50形成在第二金屬化層42上。在一實施例中，凸塊50為焊料凸塊，例如包含無鉛焊料、錫銀、或包含錫、鉛、銀、銅、鎳、鉍或其組合之合金的焊料材料。焊料凸塊可藉由放置焊料球或在迴流焊製程中鍍上焊料層而形成。在一些實施例中，凸塊50為銅柱凸塊、包含鎳或金的金屬凸塊、或其組合。在一實施例中，每一凸塊50具有一直徑大於約200微米。然後，保護層52係選擇性地形成於第二金屬化層42及第二介電層40上，且圍繞一部分的凸塊50。舉例來說，凸塊50的頂部暴露且延伸至保護層52上方。在一實施例中，保護層52為一支撐材料，其為模製化合物或其類，以提供結構性支持。
其次，如第8圖所示，載板200係自晶片10及模製化合物18分離，然後最終結構被切割成為複數個個別的封裝結構，亦被稱為扇出封裝結構。在一實施例中，膠帶204被提供於覆蓋晶片10之後側10B及模製化合物18之後側的黏合膜202上。扇出封裝結構包含一或多個晶片10及位於晶片10的前側10F的二金屬化層32及42，其中包含第二連接通道44及第一連接通道34的層疊通道結構54係電性耦接且設置於晶片10的接觸墊14上。如所示，第一連接通道34形成在第一介電層30的開口30a中。第一連接通道34包 含內襯於開口30a的底部及側壁的第一晶種層32a及填充於開口30a的第一導電層32b。根據一實施例，第一連接通道34的頂面包含一平坦金屬表面。第二連接通道44形成在第二介電層40的開口40a中。第二連接通道44包含內襯於開口40a的底部及側壁的第二晶種層42a及位於開口40a內的第二導電層42b。第二連接通道44形成於第一連接通道34之上，因此第二晶種層42a係夾置於第一導電層32b及第二導電層42b之間。藉由修改第一導電層32b的鍍膜速率及形成第一導電層32b的寬高比，平坦金屬表面可形成在第一連接通道34上，且介於模製化合物18及第一介電層30之間具有一厚度的間隙可被最小化，因此放大第二介電層40的微影窗，且得到微間距的扇出封裝結構。此外，在一些實施例中，可減少成本。
在一實施例中，封裝結構包含具有基板及接觸墊位於基板上的晶片及側向包覆晶片的模製化合物。第一介電層形成覆蓋模製化合物及晶片，且具有第一開口暴露接觸墊。第一金屬化層形成覆蓋第一介電層，其中第一金屬化層填充第一開口。第二介電層形成覆蓋第一金屬化層及第一介電層，且具有第二開口位於第一開口之上。第二金屬化層形成覆蓋第二介電層且形成在第二開口之內。
在另一實施例中，封裝結構包含具有基板及接觸墊位於基板上的晶片，及側向包覆晶片的模製化合物。第一介電層形成覆蓋模製化合物及晶片，且具有第一開口暴露接觸墊。第一晶種層形成覆蓋第一介電層，且內襯於第一開 口的側壁及底部。第一導電層形成覆蓋第一晶種層，且填充第一開口。第二介電層形成覆蓋第一導電層，且具有第二開口直接位於第一開口之上。第二晶種層形成覆蓋第二介電層，且內襯於第二開口的側壁及底部。第二導電層形成覆蓋第二晶種層。
在又一實施例中，方法包含：提供晶片，其具有接觸墊；形成模製化合物側向包覆晶片，且接觸墊被模製化合物所暴露；形成第一介電層於模製化合物及晶片之上；形成第一開口於第一介電層中，以暴露接觸墊；形成第一導電層覆蓋第一介電層，且填充第一開口，其中第一導電層在第一開口中具有平坦表面；形成第二介電層於第一導電層及第一介電層之上；形成第二開口在第二介電層中，以暴露位於第一開口上的第一導電層；以及形成第二導電層覆蓋於第二介電層上，且通過第二開口物理接觸第一導電層。
雖然本發明之諸實施例及其優點已詳細敘述，應被了解的是，在不偏離由申請專利範圍所界定的本發明之精神及範圍的前提下，可在此進行各種改變、取代及變動。此外，本申請的範圍並非被限定於敘述在本說明書中的製程、機器、製造方法、成分組成、技術手段、方法及步驟的特定實施例。如所屬技術領域中具有通常知識者將易於從本發明理解的是，當前存在或以後待開發的製程、機器、製造方法、成分組成、技術手段、方法及步驟，可利用如根據本發明在此所述的對應實施例產生大致相同的功能或達到大致相同的結果。據此，所附申請專利範圍旨在其範圍內包含 這些製程、機器、製造方法、成分組成、技術手段、方法或步驟。
14‧‧‧接觸墊
16‧‧‧鈍化層
18‧‧‧模製化合物
200‧‧‧載板
202‧‧‧黏合膜
30‧‧‧第一介電層
34‧‧‧第一連接通道
40‧‧‧第二介電層
42‧‧‧第二金屬化層
42a‧‧‧第二晶種層
42b‧‧‧第二導電層
44‧‧‧第二連接通道

Claims (10)

  1. 一種封裝結構，包含：一第一晶片，其包含一第一基板及一第一接觸墊位於該第一基板上；一第二晶片，其包含一第二基板及一第二接觸墊位於該第二基板上；一模製化合物側向包覆該第一晶片及該第二晶片；一第一介電層覆蓋該模製化合物、該第一晶片及該第二晶片，且該第一介電層具有一第一開口暴露該第一接觸墊及一第三開口暴露該第二接觸墊；一第一金屬化層覆蓋該第一介電層，其中該第一金屬化層填充該第一開口及該第三開口且側向延伸在該模製化合物之上並連接該第一接觸墊及該第二接觸墊；一第二介電層覆蓋該第一金屬化層及該第一介電層，且具有一第二開口位於該第一開口之上；以及一第二金屬化層覆蓋該第二介電層及通過該第二開口電耦合於該第一金屬化層，且側向延伸在該模製化合物之上。
  2. 如請求項1所述之封裝結構，其中該第二金屬化層係形成在該第二開口內，且物理接觸該第一金屬化層。
  3. 如請求項1所述之封裝結構，其中該第二金屬化層內襯於該第二開口的一側壁及一底部。
  4. 如請求項1所述之封裝結構，其中該第一金屬化層包含一第一晶種層及一第一導電層形成於該第一晶種層上。
  5. 如請求項1所述之封裝結構，其中該第二金屬化層包含一第二晶種層及一第二導電層形成於該第二晶種層上。
  6. 如請求項1所述之封裝結構，更包含一凸塊在該第二金屬化層上。
  7. 一種封裝結構，包含：一第一晶片，其包含一第一基板及一第一接觸墊位於該第一基板上；一第二晶片，其包含一第二基板及一第二接觸墊位於該第二基板上；一模製化合物側向包覆該第一晶片及該第二晶片；一第一介電層覆蓋該模製化合物、該第一晶片及該第二晶片，且該第一介電層具有一第一開口暴露該第一接觸墊及一第三開口暴露該第二接觸墊；一第一晶種層覆蓋該第一介電層且內襯於該第一開口及該第三開口的側壁及底部，該第一晶種層側向延伸至該模製化合物之上並連接該第一接觸墊及該第二接觸墊；一第一導電層覆蓋該第一晶種層且填充該第一開口及 該第三開口並側向延伸在該模製化合物之上；一第二介電層覆蓋該第一導電層，且具有一第二開口直接位於該第一開口之上；一第二晶種層覆蓋該第二介電層且內襯於該第二開口的一側壁及一底部；以及一第二導電層覆蓋該第二晶種層。
  8. 如請求項7所述之封裝結構，其中該第二導電層係沿著該第二開口的側壁及底部而形成。
  9. 一種形成封裝結構的方法，包含：提供一晶片，其具有一接觸墊，該晶片具有一主動表面及一底面；將該晶片之該底面黏合於一載板上；形成一模製化合物側向包覆該晶片且不覆蓋該晶片之該主動表面及該底面，且該接觸墊被該模製化合物所暴露；形成一第一介電層於該模製化合物及該晶片之上；形成一第一開口在該第一介電層中，以暴露該接觸墊；形成一第一導電層覆蓋該第一介電層，且填充該第一開口，其中該第一導電層側向延伸至該模製化合物之上且在該第一開口中具有一平坦表面；形成一第二介電層於該第一導電層及該第一介電層之上；形成一第二開口在該第二介電層中，以暴露位於該第一開口上的該第一導電層；以及 形成一第二導電層覆蓋於該第二介電層上，且通過該第二開口物理接觸該第一導電層。
  10. 如請求項9所述之方法，其中該第一導電層係藉由一銅電鍍製程所形成，且該銅電鍍製程之電鍍速率大於1微米/分鐘。
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US11532577B2 (en) 2022-12-20
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US20200373264A1 (en) 2020-11-26
US20160005702A1 (en) 2016-01-07
US10366960B2 (en) 2019-07-30
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US9824989B2 (en) 2017-11-21
TW201533811A (zh) 2015-09-01
KR20150086170A (ko) 2015-07-27
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US10741511B2 (en) 2020-08-11
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