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CN104393845A - Variable gain amplifier in current mode - Google Patents

Variable gain amplifier in current mode Download PDF

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Publication number
CN104393845A
CN104393845A CN201410560866.8A CN201410560866A CN104393845A CN 104393845 A CN104393845 A CN 104393845A CN 201410560866 A CN201410560866 A CN 201410560866A CN 104393845 A CN104393845 A CN 104393845A
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China
Prior art keywords
tube
pmos
drain electrode
current
transistor
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CN201410560866.8A
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Chinese (zh)
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CN104393845B (en
Inventor
徐建
周正
吴毅强
韩婷婷
马力
田密
王志功
陈建平
吉荣新
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Nanjing Ticom Tech Co ltd
Southeast University
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Nanjing Taitong S & T Co Ltd
Southeast University
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Priority to CN201410560866.8A priority Critical patent/CN104393845B/en
Publication of CN104393845A publication Critical patent/CN104393845A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a novel variable gain amplifier circuit in a current mode. The variable gain amplifier circuit comprises a variable gain circuit, a functional digital control logic circuit and a direct current offset calibration circuit, wherein the variable gain circuit comprises four full balanced digital programmable current amplifiers; the functional digital control logic circuit is used for coding a control signal into a binary signal and then controlling gain decibels of the variable gain circuit; and the direct current offset calibration circuit feeds a low-frequency signal output by the variable gain circuit back to an input end of the variable gain circuit to form a negative feedback loop. In the amplifier circuit in the current mode, signal input is low resistance, signal output is high resistance, and a circulating signal is a current signal and is not influenced by the magnitude of voltage. A variable gain amplifier in the current mode is in a Class-AB output structure, so that the power consumption of the circuit is greatly reduced. The current amplifier is free from limitation of a gain bandwidth product, so that the bandwidth is not limited on any gain almost.

Description

Current mode variable gain amplifier
Technical Field
The present invention relates to a gain amplifier, and more particularly, to a current mode variable gain amplifier.
Background
With the improvement of the process, the bearing voltage of the MOS tube is lower and lower, so that the power supply voltage is reduced. For example, the 40nm low-voltage tube voltage is only about 1.0V, and the turn-on voltage Vt is about 0.4V. Thus for a two layer tube amplifier circuit, there is only a 0.2V dynamic range. This presents a significant challenge to the design of the circuit from a voltage signal perspective.
The traditional voltage signal variable gain amplifier is realized by adopting operational amplifier feedback. Are limited by the gain-bandwidth product of the op-amp. At low gain, the bandwidth is wide, and at high gain, the bandwidth becomes narrow, which is not favorable for application in broadband occasions.
Disclosure of Invention
The purpose of the invention is as follows: aiming at the prior art, the variable gain amplifying circuit applied to current input and output is provided, and the problem that under the conditions of low voltage and low power consumption, the bandwidth is narrowed when the gain is high, and the amplification in broadband occasions is not facilitated is solved.
The technical scheme is as follows: a current mode variable gain amplifier comprises a variable gain circuit, a functional digital control logic circuit and a direct current offset calibration circuit; the variable gain circuit comprises four stages of current fully differential programmable amplifiers, wherein the input end of the first stage of current fully differential programmable amplifier is used as the input end of the current mode variable gain amplifier, and the output end of the fourth stage of current fully differential programmable amplifier is used as the output end of the current mode variable gain amplifier; the functional digital control logic circuit is used for controlling the gain decibels of the variable gain circuit; and the direct current offset calibration circuit feeds back a low-frequency signal output by the fourth-stage current fully-differential programmable amplifier to the input end of the first-stage current fully-differential programmable amplifier to form a negative feedback loop.
As the improvement of the invention, the single-stage current fully-differential programmable amplifier is formed by reversely connecting two symmetrical single-ended input and differential output current followers; each current follower comprises M1-M19 MOS transistors and a bias current source IBIASAnd first to sixth CDN units; the MOS transistors M1-M19 are single MOS transistors, M11, M13 and M19 are three groups of MOS transistors each comprising a plurality of PMOS transistors, and M10, M12 and M18 are three groups of MOS transistors each comprising a plurality of NMOS transistors; the source electrodes of the PMOS tube M1, the PMOS tube M2, the PMOS tube M9, the PMOS tube M11, the PMOS tube M13, the PMOS tube M15, the PMOS tube M17 and the PMOS tube M19 are all grounded, and the source electrodes of the NMOS tube M5, the NMOS tube M6, the NMOS tube M7, the NMOS tube M10, the NMOS tube M12, the NMOS tube M14, the NMOS tube M16, the NMOS tube M18 and the drain electrode of the PMOS tube M8 are all connected with an external high-level VDD; the grid electrode of the PMOS tube M1 is connected with the drain electrode thereof, and the bias current source IBIASIs connected between the drain of the PMOS transistor M1 and the drain of the NMOS transistor M5. A bias voltage source is connected between the drain electrode of the NMOS transistor M5 and the drain electrode of the PMOS transistor M1, the drain electrode of the NMOS transistor M6 is connected with the drain electrode of the PMOS transistor M3, and the source electrode of the PMOS transistor M3 is connected with a direct current level VCM(ii) a The drain electrode of the NMOS tube M7 is connected with the drain electrode of the PMOS tube M4, and the source electrode of the PMOS tube M4 is connected with the drain electrode of the PMOS tube M2; the gates of the PMOS transistor M3 and the PMOS transistor M4 are connected and connected to the drain of the NMOS transistor M6; the gates of the NMOS transistor M5, the NMOS transistor M6 and the NMOS transistor M7 are all connected to the drain of the NMOS transistor M5; the source electrode of the PMOS tube M8 is connected with the drain electrode of the PMOS tube M9, and the gate electrode of the PMOS tube M9 is connected with an external bias voltage source VBIAS(ii) a The drain electrode of the NMOS tube M10 is connected with the first end of the first CDN unit, the input end of the second end of the first CDN unit is connected with the first end of the second CDN unit, and the second end of the second CDN unit is connected with the drain electrode of the PMOS tube M11; the drain electrode of the NMOS tube M12 is connected with the first end of the third CDN unit, the input end of the second end of the third CDN unit is connected with the first end of the fourth CDN unit, and the second end of the fourth CDN unit is connected with the drain electrode of the PMOS tube M13; the drain of the NMOS transistor M14 is connected to the drain of the PMOS transistor M17, the drain of the NMOS transistor M16 is connected to the drain of the PMOS transistor M175, the drain of the NMOS transistor M18 is connected to the first end of the fifth CDN unit,the second end of the fifth CDN unit is connected to the first end of the sixth CDN unit, and the second end of the sixth CDN unit is connected to the drain of the PMOS transistor M19; the gates of the PMOS transistor M8, the NMOS transistor M10, the NMOS transistor M12 and the NMOS transistor M14 are all connected to the drain of the NMOS transistor M7, the gates of the MOS transistor M16 and the NMOS transistor M18 are all connected to the drain of the MOS transistor M16, the gates of the PMOS transistor M1 and the PMOS transistor M2 are all connected to the drain of the PMOS transistor M1, the gates of the PMOS transistor M11, the PMOS transistor M13 and the PMOS transistor M15 are all connected to the drain of the PMOS transistor M9, the gates of the PMOS transistor M17 and the PMOS transistor M19 are all connected to the drain of the PMOS transistor M17, the source of the PMOS transistor M4 is connected to the first end of the first CDN unit and serves as the input end of the current follower, the connection point of the third CDN unit and the fourth CDN unit serves as the in-phase output end of the current follower, and the connection point of the fifth unit and the sixth CDN unit serves as the reverse.
As an improvement of the invention, the direct current offset calibration circuit and the variable gain circuit form a first-order low-pass feedback network; the direct current offset calibration circuit comprises a fully differential current connector, two active resistors and a resistor R2; the differential input ends of the fully differential current splicer are respectively connected with the output end of the variable gain circuit after being connected with an active resistor in series; the resistor R2 is connected with a fully differential current connector to form a fully differential linear transconductance, the magnitude of a signal fed back to the input end of the variable gain circuit by the direct current offset calibration circuit is adjusted by adjusting the magnitude of the resistor R2, and the magnitude of the transconductance is(ii) a The transfer function of the feedback network is:
wherein,for variable gain amplificationA pole frequency;is composed ofA value at 0 frequency.
As an improvement of the invention, the fully differential current connector comprises twenty-six MOS transistors from M1 to M26, and a resistor R3 and a resistor R4; the sources of the NMOS transistors M13, M11, M9, M7, M8, M10, M12, M14, M25 and M26 are all connected with an external high-level VDD, the sources of the PMOS transistors M15, M16, M17, M18, M19, M20, M21 and M22 are all grounded, the gates of the PMOS transistors M15-M22 are all connected with an external bias voltage source VBIAS(ii) a The drain electrode of the NMOS tube M13 is connected with the drain electrode of the PMOS tube M15, and the connection point of the NMOS tube M13 and the PMOS tube M15 is used as the current signal inverting output end Z of the fully differential current connectorN(ii) a The drain electrode of the NMOS tube M11 is connected with the drain electrode of the PMOS tube M16, the drain electrode of the NMOS tube M9 is connected with the drain electrode of the PMOS tube M3, the grid electrode of the PMOS tube M3 is connected with the drain electrode of the PMOS tube M16 and is used as the inverting input end X of the current signal of the fully differential current connectorNThe drain of NMOS transistor M7 is connected to the drains of PMOS transistors M4 and M1, and the gate of PMOS transistor M4 is connected to DC level VCMThe source electrodes of the PMOS tube M3 and the PMOS tube M4 are both connected with the drain electrode of the PMOS tube M17, and the grid electrodes of the NMOS tube M13 and the NMOS tube M11 are both connected with the drain electrode of the PMOS tube M4; the drain electrode of the NMOS tube M8 is simultaneously connected with the drain electrodes of the PMOS tubes M2 and M5, and the grid electrode of the PMOS tube M1 is used as the voltage signal inverting input end Y of the fully differential current connectorINThe grid of the PMOS tube M2 is used as the voltage signal non-inverting input end Y of the fully differential current connectorPNThe sources of the PMOS tubes M1 and M2 are both connected with the drain of the PMOS tube M18, and the gate of the PMOS tube M5 is connected with the DC level VCM(ii) a The drain electrode of the NMOS tube M10 is connected with the drain electrode of the PMOS tube M6, the source electrodes of the PMOS tubes M5 and M6 are connected with the drain electrode of the PMOS tube M19, the gate electrodes of the NMOS tube M7 and the NMOS tube M8 are connected, the drain electrode of the NMOS tube M9 is connected with the gate electrode of the NMOS tube M10, the drain electrode of the NMOS tube M12 is connected with the drain electrode of the PMOS tube M21, and the drain electrode of the PMOS tube M6 is connected with the drain electrode of the PMOS tube M6A non-inverting input terminal X connected with the drain electrode of the NMOS tube M12 and used as a current signal of the fully differential current connectorP(ii) a The drain electrode of the NMOS tube M14 is connected with the drain electrode of the PMOS tube M21 and is used as the current signal positive phase output end Z of the fully differential current connectorPThe gates of the NMOS transistors M12 and M14 are both connected with the drain of the NMOS transistor M8; the drain electrode of the NMOS tube M25 is connected with the grid electrode thereof and the drain electrode of the PMOS tube M23, the drain electrode of the NMOS tube M26 is connected with the grid electrode thereof and the drain electrode of the PMOS tube M24, the grid electrode of the PMOS tube M23 is simultaneously connected with one ends of a resistor R3 and a resistor R4, and the other end of the resistor R3 is used as a positive phase input end X of a current signal of the fully differential current connectorPThe other end of the resistor R4 is used as the inverting input end X of the current signal of the fully differential current connectorNThe sources of the PMOS tubes M24 and M23 are both connected with the drain of the PMOS tube M22, and the gate of the PMOS tube M24 is connected with the DC level VCM。
As an improvement of the invention, the active resistor comprises four MOS tubes; the source electrode of the first MOS tube is respectively connected with the drain electrode of the second MOS tube and the drain electrode of the third MOS tube, the drain electrode of the first MOS tube is respectively connected with the grid electrode of the first MOS tube and the source electrode of the second MOS tube, the grid electrode of the second MOS tube is connected with the drain electrode of the second MOS tube, the drain electrode of the third MOS tube is respectively connected with the grid electrode of the third MOS tube and the source electrode of the fourth MOS tube, and the source electrode of the third MOS tube is respectively connected with the drain electrode of the fourth MOS tube and the grid electrode of the fourth MOS tube.
Has the advantages that: in the current mode amplifying circuit, the signal input is low resistance, the signal output is high resistance, and the circulating signal is a current signal and is not influenced by the voltage. The current mode variable gain amplifier adopts a Class-AB output structure, and the power consumption of the circuit is greatly reduced. The current amplifier is not limited by the product of gain and bandwidth, so that the bandwidth can be almost unlimited at any gain. The current mode variable gain amplifier provided by the invention greatly reduces the influence of power supply voltage on the circuit, greatly improves the input and output dynamic range of the circuit, and simultaneously only needs extremely small current.
Drawings
FIG. 1 is a block diagram of a current-mode variable gain amplifier architecture;
fig. 2 is a block diagram of a single stage fully differential current-mode variable gain amplifier FBDPCA;
FIG. 3 is a circuit diagram of a current follower;
FIG. 4 is a functional digital control logic circuit schematic;
fig. 5 is a circuit diagram of a fully differential current connector applied to a dc offset calibration circuit;
fig. 6 shows an active resistor structure applied to a dc offset calibration circuit.
Detailed Description
The invention is further explained below with reference to the drawings.
As shown in fig. 1, a current-mode variable gain amplifier includes a variable gain circuit, a functional digital control logic circuit, and a dc offset calibration circuit. It is difficult to achieve high gain with a single-stage current amplifier, and the output linearity varies with the gain. The single-stage amplifier is used for realizing high gain, the stability is inevitably reduced, the linearity is also limited, and the multistage amplifier cascade structure is required. The more the number of stages is, the working current of the whole circuit is increased, and the power consumption of the circuit is increased. Weighing three aspects of stability, linearity and power consumption, wherein the variable gain circuit is formed by a four-stage Current fully differential Programmable Amplifier (FBDPCA); each stage has a gain of AiThen the overall current gain of the system is A = A1A2A3A4. The first-stage current gain and the second-stage current gain are designed to be 0/6/12/18dB adjustable, the third-stage current gain is designed to be 0/6/12dB adjustable, and the fourth-stage current gain is designed to be 5/6/7/8/9/10dB adjustable; the current gain of the whole current variable gain amplifier is adjustable within 5-58dB, and the step length is 1 dB.
The amplifier has a high gain of 58dB or so, which is about 794 times. A small mismatch at the input will cause a severe shift in the operating point of the subsequent stage, and therefore the current mode variable gain amplifier requires a DC offset calibration (DCOC) circuit. The basic principle of the DCOC circuit is that a low-frequency signal is taken out from the output end of the variable gain circuit, and then the signal is fed back to the input end of the variable gain circuit through a loop to form a complete negative feedback loop, so that the function of eliminating direct current offset is realized. The function of the decoder is mainly realized by a digital control logic (digital control word) circuit, and the digital control logic (digital control word) circuit is used for decoding the control signal into a binary signal of 5-58 and then controlling the gain decibel number of the variable gain circuit.
As shown in fig. 2, the single-stage current fully differential programmable amplifier (FBDPCA) is formed by connecting two symmetrical single-ended input and differential output current follower inverters (DPCA), and is mainly implemented by subtracting two single-ended current signals; the single-ended input differential output current follower adopts a Class-AB output structure. Positive output end signal of single-stage current fully-differential programmable amplifierAnd negative output end signalThe sizes are respectively as follows:
wherein,is a multiple of the gain of the signal,is a single-stage current fully differential programmable amplifier for positive input of a current signal,is a negative input current signal of the single-stage current fully differential programmable amplifier.
As shown in fig. 3, the single-stage current fully-differential programmable amplifier is formed by reversely connecting two symmetrical single-ended input and differential output current followers; each current follower comprises M1-M19 MOS transistors and a bias current source IBIASAnd first to sixth CDN units; the MOS transistors M1-M19 are single MOS transistors, M11, M13 and M19 are three groups of MOS transistors each comprising a plurality of PMOS transistors, and M10, M12 and M18 are three groups of MOS transistors each comprising a plurality of NMOS transistors. The source electrodes of the PMOS tube M1, the PMOS tube M2, the PMOS tube M9, the PMOS tube M11, the PMOS tube M13, the PMOS tube M15, the PMOS tube M17 and the PMOS tube M19 are all grounded, and the source electrodes of the NMOS tube M5, the NMOS tube M6, the NMOS tube M7, the NMOS tube M10, the NMOS tube M12, the NMOS tube M14, the NMOS tube M16, the NMOS tube M18 and the drain electrode of the PMOS tube M8 are all connected with an external high-level VDD; the grid electrode of the PMOS tube M1 is connected with the drain electrode thereof, and the bias current source IBIASIs connected between the drain of the PMOS transistor M1 and the drain of the NMOS transistor M5. A bias voltage source is connected between the drain electrode of the NMOS transistor M5 and the drain electrode of the PMOS transistor M1, the drain electrode of the NMOS transistor M6 is connected with the drain electrode of the PMOS transistor M3, and the source electrode of the PMOS transistor M3 is connected with a direct current level VCM(ii) a The drain electrode of the NMOS tube M7 is connected with the drain electrode of the PMOS tube M4, and the source electrode of the PMOS tube M4 is connected with the drain electrode of the PMOS tube M2; the gates of the PMOS transistor M3 and the PMOS transistor M4 are connected and connected to the drain of the NMOS transistor M6; the gates of the NMOS transistor M5, the NMOS transistor M6 and the NMOS transistor M7 are all connected to the drain of the NMOS transistor M5; the source electrode of the PMOS tube M8 is connected with the drain electrode of the PMOS tube M9, and the gate electrode of the PMOS tube M9 is connected with an external bias voltage source VBIAS(ii) a The drain electrode of the NMOS tube M10 is connected with the first end of the first CDN unit, the input end of the second end of the first CDN unit is connected with the first end of the second CDN unit, and the second end of the second CDN unit is connected with the drain electrode of the PMOS tube M11; the drain electrode of the NMOS tube M12 is connected with the first end of the third CDN unit, the input end of the second end of the third CDN unit is connected with the first end of the fourth CDN unit, and the second end of the fourth CDN unit is connected with the drain electrode of the PMOS tube M13; the drain electrode of the NMOS transistor M14 is connected with the drain electrode of the PMOS transistor M17, the drain electrode of the NMOS transistor M16 is connected with the drain electrode of the PMOS transistor M175, the drain electrode of the NMOS transistor M18 is connected with the first end of the fifth CDN unit, and the fifth CDN unit is connected with the drain electrode of the NMOS transistor M18The second end of the CDN unit is connected to the first end of the sixth CDN unit, and the second end of the sixth CDN unit is connected to the drain of the PMOS transistor M19; the gates of the PMOS transistor M8, the NMOS transistor M10, the NMOS transistor M12 and the NMOS transistor M14 are all connected to the drain of the NMOS transistor M7, the gates of the MOS transistor M16 and the NMOS transistor M18 are all connected to the drain of the MOS transistor M16, the gates of the PMOS transistor M1 and the PMOS transistor M2 are all connected to the drain of the PMOS transistor M1, the gates of the PMOS transistor M11, the PMOS transistor M13 and the PMOS transistor M15 are all connected to the drain of the PMOS transistor M9, the gates of the PMOS transistor M17 and the PMOS transistor M19 are all connected to the drain of the PMOS transistor M17, the source of the PMOS transistor M4 is connected to the first end of the first CDN unit and serves as the input end of the current follower, the connection point of the third CDN unit and the fourth CDN unit serves as the in-phase output end of the current follower, and the connection point of the fifth unit and the sixth CDN unit serves as the reverse. The MOS transistors M11, M13, M19, M10, M12 and M18 are all connected with a plurality of NMOS or PMOS transistors in each group.
The amplifier comprises a first N-tube current mirror consisting of an MOS tube M1 and an MOS tube M2, a second N-tube current mirror consisting of an MOS tube M3 and an MOS tube M4, a first P-tube current mirror consisting of an MOS tube M5, an MOS tube M6 and an MOS tube M7, a second P-tube current mirror consisting of an MOS tube M16 and an MOS tube M18, a third P-tube current mirror consisting of an MOS tube M17 and an MOS tube M19, eight MOS tubes of M8-M15, a bias voltage source and first-sixth CDN units, and a two-stage common-gate-common-source amplifier consisting of MOS tubes M4-M10. In the current follower inverter (DPCA) with single-ended input and differential output, the current of the MOS transistor M6 and the current of the MOS transistor M7 are both mirrored from the MOS transistor M5, and the MOS transistor M4 and the MOS transistor M3 are also a pair of current mirrors. The source of the MOS transistor M3 is directly connected with the DC level, which is equivalent to the AC ground. Therefore, the source of the MOS transistor M4, i.e., the input terminal of the current signal, is designed as a low impedance point, which is favorable for the input of the current signal. The input signal is amplified by a MOS transistor M4-MOS transistor M10 two-stage common-gate common-source amplifier and fed back to the input terminal, so that the input terminal X can be calculatedINResistance R ofIN. Wherein M10, M11, M12, M13, M18 and M19 are all a group of tubes with various sizes, the output currents of MOS tube M12 and MOS tube M13 follow MOS tube M10 and MOS tube M11, and MOS tube M12, MOS tube M13, MOS tube M10 and MOS tube M11 are controlled11, the in-phase output Z can be obtainedPAnd input terminal XINThe in-phase current ratio; the tubes of M18 and M19 have the same sizes as those of M12 and M13, and the current direction is reversed through M14, M15, M16 and M17, so that an inverted output end Z can be obtainedNAnd input terminal XINThe reverse phase current ratio. Therefore, the single-stage current variable gain amplifier with single input end and differential output is realized. The output stage Rout is formed by connecting the output resistors of the MOS transistor M12 and the MOS transistor M13 in parallel, and has a high resistance. And designing a current amplifier meeting the input and output impedance according to the impedance of the front and rear stages.
Taking a PMOS branch as an example, the CDN unit of the current distribution network may be implemented as shown in fig. 4, where the CDN unit includes n PMOS transistors, drains of the n PMOS transistors are connected to each other and serve as a second end of the CDN unit (i.e., serve as a current output point), sources of the n PMOS transistors serve as first ends of the CDN unit, a source of each PMOS transistor is correspondingly connected to a drain of an MOS transistor in the M10 group, and gates of the n PMOS transistors are independent and are controlled by a control word.ToFor controlling the signal, the source current of each PMOS tube is controlledToMake and break of (2).When the voltage is high level, the switching tube is disconnected, and the current of the path is not conducted;when the voltage is low level, the switch tube is disconnected, and the current flows through the switch tube, so that the current programming is realized. Wherein, the value of n is consistent with the number of PMOS tubes in the M10 group. The NMOS branch structure is the same as that of PMOS, but N tubes are neededAs a switch.
In fig. 1, the dc offset calibration circuit and the variable gain circuit form a first-order low-pass feedback network, and the dc offset calibration circuit includes a fully differential current transformer (FBCCII), two active resistors, and a resistor R2. The differential input ends of the fully differential current splicer are respectively connected with the output end of the variable gain circuit after being connected with an active resistor in series. The transfer function of the feedback network is:
wherein,is composed ofAt the value of the frequency of 0, the frequency of,the variable gain amplifier pole frequency. Considering the DCOC feedback network, the gain of the whole system is:
due to pole frequency of DCOCVery low, at 0 frequency (around dc), the gain of the whole system is approximately:
as long asFar greaterIn 1, the dc error cancellation can be achieved. When the intermediate frequency signal passes through, the signal frequency is far more thanThe feedback network isIs 0 and does not affect the application of the working frequency.
Since the input and output signals of the variable gain circuit are current signals, in order to not reduce the magnitude of the current, a voltage signal is taken at the output end of the variable gain circuit, and the current is fed back to the input end of the variable gain circuit, so that a fully differential linear transconductance is required. The fully differential linear transconductance of the invention is formed by a fully differential FBCCII and a resistor R2, and the transconductanceThe size is as follows:
the magnitude of the signal fed back to the input end of the variable gain circuit by the direct current offset calibration circuit is adjusted by adjusting the magnitude of the resistor R2, namely, the DCOC feedback depth and the loop gain are controlled by changing the magnitude of the R2.
The fully differential current connector (fbcci) is shown in fig. 5, and includes twenty-six MOS transistors M1-M26, and a resistor R3 and a resistor R4; the sources of the NMOS transistors M13, M11, M9, M7, M8, M10, M12, M14, M25 and M26 are all connected with an external high-level VDD, the sources of the PMOS transistors M15, M16, M17, M18, M19, M20, M21 and M22 are all grounded, the gates of the PMOS transistors M15-M22 are all connected with an external bias voltage source VBIAS(ii) a The drain electrode of the NMOS tube M13 is connected with the drain electrode of the PMOS tube M15, and the connection point of the NMOS tube M13 and the PMOS tube M15 is used as the current signal inverting output end Z of the fully differential current connectorN(ii) a Drain of NMOS transistor M11The drain electrode of the PMOS tube M16 is connected, the drain electrode of the NMOS tube M9 is connected with the drain electrode of the PMOS tube M3, the grid electrode of the PMOS tube M3 is connected with the drain electrode of the PMOS tube M16 and is used as the inverting input end X of the current signal of the fully differential current connectorNThe drain of NMOS transistor M7 is connected to the drains of PMOS transistors M4 and M1, and the gate of PMOS transistor M4 is connected to DC level VCMThe source electrodes of the PMOS tube M3 and the PMOS tube M4 are both connected with the drain electrode of the PMOS tube M17, and the grid electrodes of the NMOS tube M13 and the NMOS tube M11 are both connected with the drain electrode of the PMOS tube M4; the drain electrode of the NMOS tube M8 is simultaneously connected with the drain electrodes of the PMOS tubes M2 and M5, and the grid electrode of the PMOS tube M1 is used as the voltage signal inverting input end Y of the fully differential current connectorINThe grid of the PMOS tube M2 is used as the voltage signal non-inverting input end Y of the fully differential current connectorPNThe sources of the PMOS tubes M1 and M2 are both connected with the drain of the PMOS tube M18, and the gate of the PMOS tube M5 is connected with the DC level VCM(ii) a The drain of the NMOS transistor M10 is connected with the drain of the PMOS transistor M6, the sources of the PMOS transistors M5 and M6 are both connected with the drain of the PMOS transistor M19, the gate of the NMOS transistor M7 is connected with the gate of the NMOS transistor M8, the drain of the NMOS transistor M9 is connected with the gate of the NMOS transistor M10, the drain of the NMOS transistor M12 is connected with the drain of the PMOS transistor M21, the drain of the PMOS transistor M6 is connected with the drain of the NMOS transistor M12 and serves as the positive phase input end X of the current signal of the fully differential current connectorP(ii) a The drain electrode of the NMOS tube M14 is connected with the drain electrode of the PMOS tube M21 and is used as the current signal positive phase output end Z of the fully differential current connectorPThe gates of the NMOS transistors M12 and M14 are both connected with the drain of the NMOS transistor M8; the drain electrode of the NMOS tube M25 is connected with the grid electrode thereof and the drain electrode of the PMOS tube M23, the drain electrode of the NMOS tube M26 is connected with the grid electrode thereof and the drain electrode of the PMOS tube M24, the grid electrode of the PMOS tube M23 is simultaneously connected with one ends of a resistor R3 and a resistor R4, and the other end of the resistor R3 is used as a positive phase input end X of a current signal of the fully differential current connectorPThe other end of the resistor R4 is used as the inverting input end X of the current signal of the fully differential current connectorNThe sources of the PMOS tubes M24 and M23 are both connected with the drain of the PMOS tube M22, and the gate of the PMOS tube M24 is connected with the DC level VCM。
The MOS transistor M15, M16, M7, M18, M19, M20, M21 and M22 form a first P transistor current mirror; a first differential input pair transistor is formed by MOS transistors M1 and M2; byThe MOS transistors M3 and M4 form a second differential input pair transistor; a third differential input pair transistor is formed by MOS transistors M5 and M6; the MOS transistor M23, M24, M25, M26, R3, R4, M7 and M8 form a common mode negative feedback circuit; the MOS transistors M9 and M10 constitute diode-connected active resistors. The voltage signal input end and the current signal input end are low-impedance nodes, and the current signal output end is a high-impedance node. MOS transistor M1 and MOS transistor M2 are differential signal inputs, MOS transistor M11 and MOS transistor M12 are output stages of two-stage operational amplifier, and X is realized by feedbackP、XNLow impedance current input terminal, output terminal ZNPThe parallel connection of the channel modulation resistors of the MOS transistor M14 and the MOS transistor M21 is high impedance, ZNThe same is true. MOS tubes M23, M24, M25 and M26, R3 and R4 form a common mode negative feedback circuit, and the direct current working point of the circuit is stabilized.
The active resistor R1 in DCOC in fig. 1 may be designed using the active resistor shown in fig. 6. The active resistor comprises four MOS tubes; the source electrode of the first MOS tube is respectively connected with the drain electrode of the second MOS tube and the drain electrode of the third MOS tube, the drain electrode of the first MOS tube is respectively connected with the grid electrode of the first MOS tube and the source electrode of the second MOS tube, the grid electrode of the second MOS tube is connected with the drain electrode of the second MOS tube, the drain electrode of the third MOS tube is respectively connected with the grid electrode of the third MOS tube and the source electrode of the fourth MOS tube, and the source electrode of the third MOS tube is respectively connected with the drain electrode of the fourth MOS tube and the grid electrode of the fourth MOS tube. In use, 4 MOS tubes are all in non-conducting state, and the direct current resistance is very large, which can be realized generallyAnd on the left and right, the lower DCOC pole frequency is easier to realize.
In the current mode variable gain amplifier circuit, the signal input is low resistance, the signal output is high resistance, and the circulating signal is a current signal and is not influenced by the voltage. The single-ended input differential output current mode variable gain amplifier shown in fig. 3 adopts a Class-AB output structure, so that the power consumption of the circuit is greatly reduced. The current amplifier is not limited by the product of gain and bandwidth, so that the bandwidth can be almost unlimited at any gain.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (5)

1. A current-mode variable gain amplifier, characterized by: the digital control circuit comprises a variable gain circuit, a functional digital control logic circuit and a direct current offset calibration circuit; the variable gain circuit comprises four stages of current fully differential programmable amplifiers, wherein the input end of the first stage of current fully differential programmable amplifier is used as the input end of the current mode variable gain amplifier, and the output end of the fourth stage of current fully differential programmable amplifier is used as the output end of the current mode variable gain amplifier; the functional digital control logic circuit is used for controlling the gain decibels of the variable gain circuit; and the direct current offset calibration circuit feeds back a low-frequency signal output by the fourth-stage current fully-differential programmable amplifier to the input end of the first-stage current fully-differential programmable amplifier to form a negative feedback loop.
2. A current-mode variable gain amplifier according to claim 1, wherein: the single-stage current fully-differential programmable amplifier is formed by reversely connecting two symmetrical single-ended input and differential output current followers; each current follower comprises M1-M19 MOS transistors and a bias current source IBIASAnd first to sixth CDN units; the MOS transistors M1-M19 are single MOS transistors, M11, M13 and M19 are three groups of MOS transistors each comprising a plurality of PMOS transistors, and M10, M12 and M18 are three groups of MOS transistors each comprising a plurality of NMOS transistors; the source electrodes of the PMOS tube M1, the PMOS tube M2, the PMOS tube M9, the PMOS tube M11, the PMOS tube M13, the PMOS tube M15, the PMOS tube M17 and the PMOS tube M19 are all grounded, and the source electrodes of the NMOS tube M5, the NMOS tube M6, the NMOS tube M7, the NMOS tube M10, the NMOS tube M12, the NMOS tube M14, the NMOS tube M16, the NMOS tube M18 and the drain electrode of the PMOS tube M8 are all connected with an external high-level VDD; the grid electrode of the PMOS tube M1 is connected with the drain electrode thereof, and the bias current source IBIASThe transistor is connected between the drain electrode of the PMOS transistor M1 and the drain electrode of the NMOS transistor M5; a bias voltage source is connected between the drain electrode of the NMOS transistor M5 and the drain electrode of the PMOS transistor M1, the drain electrode of the NMOS transistor M6 is connected with the drain electrode of the PMOS transistor M3, and the source electrode of the PMOS transistor M3 is connected with a direct current level VCM(ii) a The drain electrode of the NMOS tube M7 is connected with the drain electrode of the PMOS tube M4, and the source electrode of the PMOS tube M4 is connected with the drain electrode of the PMOS tube M2; the gates of the PMOS transistor M3 and the PMOS transistor M4 are connected and connected to the drain of the NMOS transistor M6; the gates of the NMOS transistor M5, the NMOS transistor M6 and the NMOS transistor M7 are all connected to the drain of the NMOS transistor M5; the source electrode of the PMOS tube M8 is connected with the drain electrode of the PMOS tube M9, and the gate electrode of the PMOS tube M9 is connected with an external bias voltage source VBIAS(ii) a The drain electrode of the NMOS tube M10 is connected with the first end of the first CDN unit, the input end of the second end of the first CDN unit is connected with the first end of the second CDN unit, and the second end of the second CDN unit is connected with the drain electrode of the PMOS tube M11; the drain electrode of the NMOS tube M12 is connected with the first end of the third CDN unit, the input end of the second end of the third CDN unit is connected with the first end of the fourth CDN unit, and the second end of the fourth CDN unit is connected with the first end of the fourth CDN unitThe drain electrode of the PMOS pipe M13; the drain electrode of the NMOS transistor M14 is connected to the drain electrode of the PMOS transistor M17, the drain electrode of the NMOS transistor M16 is connected to the drain electrode of the PMOS transistor M175, the drain electrode of the NMOS transistor M18 is connected to the first end of the fifth CDN unit, the second end of the fifth CDN unit is connected to the first end of the sixth CDN unit, and the second end of the sixth CDN unit is connected to the drain electrode of the PMOS transistor M19; the gates of the PMOS transistor M8, the NMOS transistor M10, the NMOS transistor M12 and the NMOS transistor M14 are all connected to the drain of the NMOS transistor M7, the gates of the MOS transistor M16 and the NMOS transistor M18 are all connected to the drain of the MOS transistor M16, the gates of the PMOS transistor M1 and the PMOS transistor M2 are all connected to the drain of the PMOS transistor M1, the gates of the PMOS transistor M11, the PMOS transistor M13 and the PMOS transistor M15 are all connected to the drain of the PMOS transistor M9, the gates of the PMOS transistor M17 and the PMOS transistor M19 are all connected to the drain of the PMOS transistor M17, the source of the PMOS transistor M4 is connected to the first end of the first CDN unit and serves as the input end of the current follower, the connection point of the third CDN unit and the fourth CDN unit serves as the in-phase output end of the current follower, and the connection point of the fifth unit and the sixth CDN unit serves as the reverse.
3. A current-mode variable gain amplifier according to claim 1, wherein: the direct current offset calibration circuit and the variable gain circuit form a first-order low-pass feedback network; the direct current offset calibration circuit comprises a fully differential current connector, two active resistors and a resistor R2; the differential input ends of the fully differential current splicer are respectively connected with the output end of the variable gain circuit after being connected with an active resistor in series; the resistor R2 is connected with a fully differential current connector to form a fully differential linear transconductance, the magnitude of a signal fed back to the input end of the variable gain circuit by the direct current offset calibration circuit is adjusted by adjusting the magnitude of the resistor R2, and the magnitude of the transconductance is(ii) a The transfer function of the feedback network is:
wherein,is the variable gain amplifier pole frequency;is composed ofA value at 0 frequency.
4. A current-mode variable gain amplifier according to claim 3, wherein: the fully differential current connector comprises twenty-six MOS transistors from M1 to M26, a resistor R3 and a resistor R4; the sources of the NMOS transistors M13, M11, M9, M7, M8, M10, M12, M14, M25 and M26 are all connected with an external high-level VDD, the sources of the PMOS transistors M15, M16, M17, M18, M19, M20, M21 and M22 are all grounded, the gates of the PMOS transistors M15-M22 are all connected with an external bias voltage source VBIAS(ii) a The drain electrode of the NMOS tube M13 is connected with the drain electrode of the PMOS tube M15, and the connection point of the NMOS tube M13 and the PMOS tube M15 is used as the current signal inverting output end Z of the fully differential current connectorN(ii) a The drain electrode of the NMOS tube M11 is connected with the drain electrode of the PMOS tube M16, the drain electrode of the NMOS tube M9 is connected with the drain electrode of the PMOS tube M3, the grid electrode of the PMOS tube M3 is connected with the drain electrode of the PMOS tube M16 and is used as the inverting input end X of the current signal of the fully differential current connectorNThe drain of NMOS transistor M7 is connected to the drains of PMOS transistors M4 and M1, and the gate of PMOS transistor M4 is connected to DC level VCMThe source electrodes of the PMOS tube M3 and the PMOS tube M4 are both connected with the drain electrode of the PMOS tube M17, and the grid electrodes of the NMOS tube M13 and the NMOS tube M11 are both connected with the drain electrode of the PMOS tube M4; the drain electrode of the NMOS tube M8 is simultaneously connected with the drain electrodes of the PMOS tubes M2 and M5, and the grid electrode of the PMOS tube M1 is used as the voltage signal inverting input end Y of the fully differential current connectorINThe grid of the PMOS tube M2 is used as the voltage signal non-inverting input end Y of the fully differential current connectorPNThe sources of the PMOS tubes M1 and M2 are both connected with the drain of the PMOS tube M18, and the gate of the PMOS tube M5 is connected with the DC level VCM(ii) a The drain of the NMOS transistor M10 is connected with the drain of the PMOS transistor M6, the sources of the PMOS transistors M5 and M6 are both connected with the drain of the PMOS transistor M19, the gate of the NMOS transistor M7 is connected with the gate of the NMOS transistor M8, the drain of the NMOS transistor M9 is connected with the gate of the NMOS transistor M10, the drain of the NMOS transistor M12 is connected with the drain of the PMOS transistor M21, the drain of the PMOS transistor M6 is connected with the drain of the NMOS transistor M12 and serves as the positive phase input end X of the current signal of the fully differential current connectorP(ii) a The drain electrode of the NMOS tube M14 is connected with the drain electrode of the PMOS tube M21 and is used as the current signal positive phase output end Z of the fully differential current connectorPThe gates of the NMOS transistors M12 and M14 are both connected with the drain of the NMOS transistor M8; the drain electrode of the NMOS tube M25 is connected with the grid electrode thereof and the drain electrode of the PMOS tube M23, the drain electrode of the NMOS tube M26 is connected with the grid electrode thereof and the drain electrode of the PMOS tube M24, the grid electrode of the PMOS tube M23 is simultaneously connected with one ends of a resistor R3 and a resistor R4, and the other end of the resistor R3 is used as a positive phase input end X of a current signal of the fully differential current connectorPThe other end of the resistor R4 is used as the inverting input end X of the current signal of the fully differential current connectorNThe sources of the PMOS tubes M24 and M23 are both connected with the drain of the PMOS tube M22, and the gate of the PMOS tube M24 is connected with the DC level VCM。
5. A current-mode variable gain amplifier according to claim 3, wherein: the active resistor comprises four MOS tubes; the source electrode of the first MOS tube is respectively connected with the drain electrode of the second MOS tube and the drain electrode of the third MOS tube, the drain electrode of the first MOS tube is respectively connected with the grid electrode of the first MOS tube and the source electrode of the second MOS tube, the grid electrode of the second MOS tube is connected with the drain electrode of the second MOS tube, the drain electrode of the third MOS tube is respectively connected with the grid electrode of the third MOS tube and the source electrode of the fourth MOS tube, and the source electrode of the third MOS tube is respectively connected with the drain electrode of the fourth MOS tube and the grid electrode of the fourth MOS tube.
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CN116032283B (en) * 2023-01-09 2023-09-22 合肥工业大学 Programmable gain amplifying circuit with DCOC calibration and implementation method
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