CN104393845A - Variable gain amplifier in current mode - Google Patents

Abstract

The invention discloses a novel variable gain amplifier circuit under current mode, which includes a variable gain circuit, a functional digital control logic circuit and a DC offset calibration circuit; the variable gain circuit includes a four-stage current fully differential programmable amplifier; Function The digital control logic circuit is used to control the gain decibels of the variable gain circuit after decoding the control signal into a binary signal; the DC offset calibration circuit feeds back the output low frequency signal of the variable gain circuit to the input terminal of the variable gain circuit , forming a negative feedback loop. In the current mode amplifier circuit of this design, the signal input is low impedance, the output is high impedance, and the circulating signal is a current signal, which is not affected by the voltage. The current mode variable gain amplifier adopts the output structure of Class-AB, which greatly reduces the power consumption of the circuit. The current amplifier is not limited by the gain-bandwidth product, so it can be used at almost any gain without limiting the bandwidth.

Description

A Current Mode Variable Gain Amplifier

technical field

The invention relates to a gain amplifier, in particular to a current mode variable gain amplifier.

Background technique

With the improvement of the technology, the withstand voltage of the MOS tube is getting lower and lower, resulting in a reduction of the power supply voltage. For example, the voltage of the popular 40nm low-voltage tube is only about 1.0V, and the turn-on voltage Vt is about 0.4V. In this way, for the amplifier circuit with two layers of tubes, there is only a dynamic range of 0.2V. From the voltage signal point of view, this brings great challenges to the circuit design.

Traditional voltage signal variable gain amplifiers are all realized by op amp feedback. are limited by the gain-bandwidth product of the op amp. When the gain is low, the bandwidth is relatively wide, and when the gain is high, the bandwidth becomes narrow, which is not conducive to the application of broadband applications.

Contents of the invention

Purpose of the invention: Aiming at the above prior art, a variable gain amplifier circuit that can be applied to current input and output is proposed to solve the problem of narrowing bandwidth at high gain under low voltage and low power consumption conditions, which is not conducive to the amplification problem of broadband applications .

Technical solution: A current mode variable gain amplifier, including a variable gain circuit, a functional digital control logic circuit, and a DC offset calibration circuit; the variable gain circuit includes a four-stage current fully differential programmable amplifier, and the first stage current is fully differential The input terminal of the differential programmable amplifier is used as the input terminal of the current mode variable gain amplifier, and the output terminal of the fourth-stage current fully differential programmable amplifier is used as the output terminal of the current mode variable gain amplifier; the functional digital control logic circuit is used for controlling the gain in decibels of the variable gain circuit; the DC offset calibration circuit feeds back the low-frequency signal output by the fourth-stage current full-differential programmable amplifier to the input end of the first-stage current full-differential programmable amplifier, forming negative feedback loop.

As an improvement of the present invention, the single-stage current fully differential programmable amplifier is composed of two symmetrical current followers with single-ended input and differential output connected in reverse; each current follower includes MOS transistors M1 to M19, bias Current source I _BIAS and the first to the sixth CDN unit; Wherein, M1 to M19 are single MOS transistors, M11, M13, M19 are three groups of MOS transistors that each group includes several PMOS transistors, M10, M12, M18, all Each group includes three groups of MOS transistors including several NMOS transistors; the sources of PMOS transistor M1, PMOS transistor M2, PMOS transistor M9, PMOS transistor M11, PMOS transistor M13, PMOS transistor M15, PMOS transistor M17 and PMOS transistor M19 are all grounded , the sources of NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M10, NMOS tube M12, NMOS tube M14, NMOS tube M16, NMOS tube M18 and the drain of PMOS tube M8 are all connected to external high level VDD; The gate of the PMOS transistor M1 is connected to its drain, and the bias current source I _BIAS is connected between the drain of the PMOS transistor M1 and the drain of the NMOS transistor M5 . The bias voltage source is connected between the drain of the NMOS transistor M5 and the drain of the PMOS transistor M1, the drain of the NMOS transistor M6 is connected to the drain of the PMOS transistor M3, and the source of the PMOS transistor M3 is connected to the DC level _VCM ; The drain of M7 is connected to the drain of the PMOS transistor M4, the source of the PMOS transistor M4 is connected to the drain of the PMOS transistor M2; the gates of the PMOS transistor M3 and the PMOS transistor M4 are connected and connected to the drain of the NMOS transistor M6; the NMOS transistor M5 The gates of the NMOS transistor M6 and the NMOS transistor M7 are all connected to the drain of the NMOS transistor M5; the source of the PMOS transistor M8 is connected to the drain of the PMOS transistor M9, and the gate of the PMOS transistor M9 is connected to the external bias voltage source V _BIAS ; The drain of the NMOS transistor M10 is connected to the first terminal of the first CDN unit, the input terminal of the second terminal of the first CDN unit is connected to the first terminal of the second CDN unit, and the second terminal of the second CDN unit is connected to the drain of the PMOS transistor M11 pole; the drain of the NMOS transistor M12 is connected to the first end of the third CDN unit, the input end of the second end of the third CDN unit is connected to the first end of the fourth CDN unit, and the second end of the fourth CDN unit is connected to the PMOS transistor M13 The drain of the NMOS transistor M14 is connected to the drain of the PMOS transistor M17, the drain of the NMOS transistor M16 is connected to the drain of the PMOS transistor M175, the drain of the NMOS transistor M18 is connected to the first end of the fifth CDN unit, and the fifth The second end of the CDN unit is connected to the first end of the sixth CDN unit, and the second end of the sixth CDN unit is connected to the drain of the PMOS transistor M19; the gates of the PMOS transistor M8, the NMOS transistor M10, the NMOS transistor M12, and the NMOS transistor M14 Both are connected to the drain of the NMOS transistor M7, the gates of the MOS transistor M16 and the NMOS transistor M18 are connected to the drain of the MOS transistor M16, the gates of the PMOS transistor M1 and the PMOS transistor M2 are connected to the drain of the PMOS transistor M1, and the gates of the PMOS transistor M11 The gates of the PMOS transistor M13 and the PMOS transistor M15 are connected to the drain of the PMOS transistor M9, the gates of the PMOS transistor M17 and the PMOS transistor M19 are connected to the drain of the PMOS transistor M17, and the source of the PMOS transistor M4 is connected to the first CDN unit The first terminal of the current follower is used as the input terminal of the current follower, the connection point of the third CDN unit and the fourth CDN unit is used as the non-inverting output terminal of the current follower, and the connection point of the fifth CDN unit and the sixth CDN unit is used as the current follower of the inverting output.

As an improvement of the present invention, the DC offset calibration circuit and the variable gain circuit constitute a first-order low-pass feedback network; the DC offset calibration circuit includes a fully differential current connector, two active resistors and a resistor R2; the The differential input terminals of the fully differential current connector are respectively connected in series with an active resistor and then connected to the output terminal of the variable gain circuit; the resistor R2 is connected to the fully differential current connector to form a fully differential linear transconductance. By adjusting the resistance R2 size to adjust the size of the signal fed back to the input terminal of the variable gain circuit by the DC offset calibration circuit, and the size of the transconductance is ; The transfer function of the feedback network is:

in, is the pole frequency of the variable gain amplifier; for The value at 0 frequency.

As an improvement of the present invention, the full differential current connector includes twenty-six MOS transistors from M1 to M26, resistors R3 and R4; NMOS transistor M13, NMOS transistor M11, NMOS transistor M9, NMOS transistor M7, NMOS transistor M8 , NMOS tube M10, NMOS tube M12, NMOS tube M14, NMOS tube M25, NMOS tube M26 are all connected to external high level VDD, PMOS tube M15, PMOS tube M16, PMOS tube M17, PMOS tube M18, PMOS tube M19 , the sources of the PMOS transistor M20, the PMOS transistor M21, and the PMOS transistor M22 are all grounded, the gates of the PMOS transistors M15-M22 are connected to the external bias voltage source V _BIAS ; the drain of the NMOS transistor M13 is connected to the drain of the PMOS transistor M15, Its connection point is used as the current signal inverting output terminal Z _N of the fully differential current connector; the drain of the NMOS transistor M11 is connected to the drain of the PMOS transistor M16, the drain of the NMOS transistor M9 is connected to the drain of the PMOS transistor M3, and the drain of the PMOS transistor M3 The gate of the NMOS transistor M16 is connected to the drain of the PMOS transistor M16 and used as the inverting input terminal X _N of the current signal of the fully differential current connector. The drain of the NMOS transistor M7 is connected to the drains of the PMOS transistors M4 and M1 at the same time, and the gate of the PMOS transistor M4 The poles are connected to the DC level V _CM , the sources of the PMOS transistor M3 and the PMOS transistor M4 are connected to the drain of the PMOS transistor M17, the gates of the NMOS transistor M13 and the NMOS transistor M11 are connected to the drain of the PMOS transistor M4; the drain of the NMOS transistor M8 The poles are connected to the drains of PMOS transistors M2 and M5 at the same time, the gate of PMOS transistor M1 is used as the inverting input terminal Y _IN of the voltage signal of the fully differential current connector, and the gate of PMOS transistor M2 is used as the inphase voltage signal of the fully differential current connector Input terminal Y _PN , the sources of the PMOS transistors M1 and M2 are connected to the drain of the PMOS transistor M18, the gate of the PMOS transistor M5 is connected to the DC level V _CM ; the drain of the NMOS transistor M10 is connected to the drain of the PMOS transistor M6, and the PMOS transistor M10 is connected to the drain of the PMOS transistor M6. The sources of M5 and M6 are connected to the drain of PMOS transistor M19, the gates of NMOS transistor M7 and NMOS transistor M8 are connected, the drain and gate of NMOS transistor M9 and the drain and gate of NMOS transistor M10 are connected. , the drain of the NMOS transistor M12 is connected to the drain of the PMOS transistor M21, the drain of the PMOS transistor M6 is connected to the drain of the NMOS transistor M12 and used as the positive phase input terminal X _P of the current signal of the fully differential current connector; the drain of the NMOS transistor M14 The drain is connected to the drain of the PMOS transistor M21 and used as the current signal positive phase output terminal Z _P of the fully differential current connector, the gates of the NMOS transistors M12 and M14 are connected to the drain of the NMOS transistor M8; the drain of the NMOS transistor M25 is connected to Its gate is connected to the drain of PMOS transistor M23, and the drain of NMOS transistor M26 is connected to its gate and connected to the drain of PMOS transistor M24. The drain, the gate of the PMOS transistor M23 are connected to one end of the resistor R3 and the resistor R4 at the same time, the other end of the resistor R3 is used as the positive phase input terminal X _P of the current signal of the full differential current connector, and the other end of the resistor R4 is used as the full differential current The inverting input terminal X _N of the current signal of the connector, the sources of the PMOS transistors M24 and M23 are both connected to the drain of the PMOS transistor M22, and the gate of the PMOS transistor M24 is connected to the DC level V _CM .

As an improvement of the present invention, the active resistance includes four MOS transistors; the source of the first MOS transistor is respectively connected to the drain of the second MOS transistor and the drain of the third MOS transistor, and the drains of the first MOS transistor are respectively The gate of the first MOS transistor is connected to the source of the second MOS transistor, the gate of the second MOS transistor is connected to the drain of the second MOS transistor, and the drain of the third MOS transistor is respectively connected to the gate of the third MOS transistor and the gate of the second MOS transistor. The source of the fourth MOS transistor and the source of the third MOS transistor are respectively connected to the drain of the fourth MOS transistor and the gate of the fourth MOS transistor.

Beneficial effects: in the current mode amplifier circuit of the present invention, the signal input is low impedance, the output is high impedance, and the circulating signal is a current signal, which is not affected by the magnitude of the voltage. The current mode variable gain amplifier adopts the output structure of Class-AB, which greatly reduces the power consumption of the circuit. The current amplifier is not limited by the gain-bandwidth product, so it can be used at almost any gain without limiting the bandwidth. The current mode variable gain amplifier proposed by the invention greatly reduces the influence of the power supply voltage on the circuit, greatly improves the input and output dynamic range of the circuit, and at the same time, the circuit only needs very little current.

Description of drawings

Figure 1 is a block diagram of a current mode variable gain amplifier;

Figure 2 is a block diagram of a single-stage fully differential current-mode variable gain amplifier FBDPCA;

Fig. 3 is the circuit diagram of current follower;

Fig. 4 is a schematic diagram of a functional digital control logic circuit;

Fig. 5 is a circuit diagram of a fully differential current connector applied to a DC offset calibration circuit;

Figure 6 is an active resistor structure applied to a DC offset calibration circuit.

Detailed ways

The present invention will be further explained below in conjunction with the accompanying drawings.

As shown in Figure 1, a current mode variable gain amplifier includes a variable gain circuit, a functional digital control logic circuit and a DC offset calibration circuit. It is difficult to achieve very high gain for a single-stage current amplifier, and the output linearity will vary with the gain. To achieve high gain with a single-stage amplifier, the stability will inevitably decrease, and the linearity will be limited, so it is necessary to use a multi-stage amplifier cascaded to form. The more stages, the working current of the whole circuit will increase, increasing the power consumption of the circuit. To balance stability, linearity and power consumption, the variable gain circuit is composed of a four-stage current full differential programmable amplifier (FBDPCA, Full Balanced Digital Programmable Current Amplifier); each stage gain is A _i , and the overall current gain of the system is It is A=A ₁ A ₂ A ₃ A ₄ . The first and second stage current gains are designed to be 0/6/12/18dB adjustable, the third stage current gain is designed to be 0/6/12dB adjustable, and the fourth stage current gain is designed to be 5/6/7/8/9 /10dB adjustable; the current gain of the entire current variable gain amplifier is adjustable from 5-58dB with a step size of 1dB.

Due to the large gain of the amplifier, the maximum reaches 58dB, which is about 794 times. A small mismatch at the input will cause a sharp shift in the operating point of the subsequent stage, so the current mode variable gain amplifier requires a DC offset calibration (DCOC, DC offset canceller) circuit. The basic principle of the DCOC circuit is to take out the low-frequency signal at the output end of the variable gain circuit, and then feed the signal back to the input end of the variable gain circuit through a loop to form a complete negative feedback loop to realize the function of DC offset elimination. Function The digital control logic (digital control word generator) circuit mainly realizes the function of the decoder, which is used to control the decibel gain of the variable gain circuit after decoding the control signal into a binary signal of 5-58.

As shown in Figure 2, the single-stage current fully differential programmable amplifier (FBDPCA) is composed of two symmetrical single-ended input differential output current follower inverters (DPCA) connected, mainly by subtracting two single-ended current signals Realization; the current follower with single-ended input and differential output adopts the Class-AB output structure. Positive output signal of single-stage current fully differential programmable amplifier and negative output signal The sizes are:

in, is the gain multiple, The positive input current signal is a single-stage current fully differential programmable amplifier, Negative input current signal for single-stage current fully differential programmable amplifier.

As shown in Figure 3, the single-stage current fully differential programmable amplifier is composed of two symmetrical current followers with single-ended input and differential output connected in reverse; each current follower includes MOS transistors from M1 to M19, a bias current source I _BIAS and the first to sixth CDN units; wherein, M1 to M19 are single MOS transistors, M11, M13, and M19 are three groups of MOS transistors that each group includes several PMOS transistors, and M10, M12, M18, are each The group includes three groups of MOS transistors including several NMOS transistors. The sources of PMOS tube M1, PMOS tube M2, PMOS tube M9, PMOS tube M11, PMOS tube M13, PMOS tube M15, PMOS tube M17, and PMOS tube M19 are all grounded, and the sources of NMOS tube M5, NMOS tube M6, NMOS tube M7, and NMOS tube The sources of tube M10, NMOS tube M12, NMOS tube M14, NMOS tube M16, NMOS tube M18 and the drain of PMOS tube M8 are all connected to external high level VDD; the gate of PMOS tube M1 is connected to its drain, and the bias current The source I _BIAS is connected between the drain of the PMOS transistor M1 and the drain of the NMOS transistor M5. The bias voltage source is connected between the drain of the NMOS transistor M5 and the drain of the PMOS transistor M1, the drain of the NMOS transistor M6 is connected to the drain of the PMOS transistor M3, and the source of the PMOS transistor M3 is connected to the DC level _VCM ; The drain of M7 is connected to the drain of the PMOS transistor M4, the source of the PMOS transistor M4 is connected to the drain of the PMOS transistor M2; the gates of the PMOS transistor M3 and the PMOS transistor M4 are connected and connected to the drain of the NMOS transistor M6; the NMOS transistor M5 The gates of the NMOS transistor M6 and the NMOS transistor M7 are all connected to the drain of the NMOS transistor M5; the source of the PMOS transistor M8 is connected to the drain of the PMOS transistor M9, and the gate of the PMOS transistor M9 is connected to the external bias voltage source V _BIAS ; The drain of the NMOS transistor M10 is connected to the first terminal of the first CDN unit, the input terminal of the second terminal of the first CDN unit is connected to the first terminal of the second CDN unit, and the second terminal of the second CDN unit is connected to the drain of the PMOS transistor M11 pole; the drain of the NMOS transistor M12 is connected to the first end of the third CDN unit, the input end of the second end of the third CDN unit is connected to the first end of the fourth CDN unit, and the second end of the fourth CDN unit is connected to the PMOS transistor M13 The drain of the NMOS transistor M14 is connected to the drain of the PMOS transistor M17, the drain of the NMOS transistor M16 is connected to the drain of the PMOS transistor M175, the drain of the NMOS transistor M18 is connected to the first end of the fifth CDN unit, and the fifth The second end of the CDN unit is connected to the first end of the sixth CDN unit, and the second end of the sixth CDN unit is connected to the drain of the PMOS transistor M19; the gates of the PMOS transistor M8, the NMOS transistor M10, the NMOS transistor M12, and the NMOS transistor M14 Both are connected to the drain of the NMOS transistor M7, the gates of the MOS transistor M16 and the NMOS transistor M18 are connected to the drain of the MOS transistor M16, the gates of the PMOS transistor M1 and the PMOS transistor M2 are connected to the drain of the PMOS transistor M1, and the gates of the PMOS transistor M11 The gates of the PMOS transistor M13 and the PMOS transistor M15 are connected to the drain of the PMOS transistor M9, the gates of the PMOS transistor M17 and the PMOS transistor M19 are connected to the drain of the PMOS transistor M17, and the source of the PMOS transistor M4 is connected to the first CDN unit The first terminal of the current follower is used as the input terminal of the current follower, the connection point of the third CDN unit and the fourth CDN unit is used as the non-inverting output terminal of the current follower, and the connection point of the fifth CDN unit and the sixth CDN unit is used as the current follower of the inverting output. Wherein, the connection relationship of the involved MOS transistors M11, M13, M19, M10, M12 and M18 is the connection relationship of several NMOS or PMOS transistors in each group.

Among them, the first N-tube current mirror is composed of MOS transistor M1 and MOS transistor M2, the second N-tube current mirror is composed of MOS transistor M3 and MOS transistor M4, and the second N-tube current mirror is composed of MOS transistor M5, MOS transistor M6 and MOS transistor M7. A P tube current mirror, a second P tube current mirror composed of MOS tube M16 and MOS tube M18, a third P tube current mirror composed of MOS tube M17 and MOS tube M19, and eight MOS tubes from M8 to M15 , a bias voltage source and the first to sixth CDN units are composed of MOS transistors M4-M10 to form a two-stage common-gate-common-source amplifier. In the current follower inverter (DPCA) with single-ended input and differential output, the currents of MOS transistor M6 and MOS transistor M7 are mirrored from MOS transistor M5, and MOS transistor M4 and MOS transistor M3 are also a pair of current mirrors. Since the source of the MOS transistor M3 is directly connected to the DC level, it is equivalent to the AC ground. Therefore, the source stage of the MOS transistor M4, that is, the input terminal of the current signal is designed as a low impedance point, which is beneficial to the input of the current signal. The input signal is amplified by the MOS transistor M4-MOS transistor M10 two-stage common-gate-common source amplifier, and fed back to the input terminal, and the impedance R _IN of the input terminal X _IN can be calculated. Among them, M10, M11, M12, M13, M18, and M19 are a group of tubes of various sizes. The output current of MOS tube M12 and MOS tube M13 follows the MOS tube M10 and MOS tube M11, and controls the MOS tube M12 and MOS tube M13. Compared with the size ratio of MOS tube M10 and MOS tube M11, the in-phase current ratio of the in-phase output terminal Z _P and the input terminal X _IN can be obtained; the size of M18 and M19 tubes is the same as that of M12 and M13, because the current direction passes through M14, M15, M16 and M17 Inverting, the ratio of the inverting output terminal Z _N to the input terminal X _IN inverting current can be obtained. Therefore, a single-stage current variable gain amplifier with single-ended input and differential output is realized. The output stage Rout is a parallel connection of the output resistors of the MOS transistor M12 and the MOS transistor M13, which is high impedance. According to the impedance of the front and rear stages, design a current amplifier that meets the input and output impedances.

Among them, taking a PMOS branch as an example, the CDN unit of the current distribution network can be realized as shown in Figure 4. The CDN unit includes n PMOS transistors, and the drains of the n PMOS transistors are connected and used as the second end of the CDN unit (that is, as the current output point), the sources of n PMOS transistors are used as the first end of the CDN unit, and the source of each PMOS transistor is correspondingly connected to the drain of a MOS transistor in the M10 group. The gates of n PMOS transistors are independent and controlled by the control word control switch. arrive For the control signal, control the source current of each PMOS tube arrive on and off. When the level is high, the switch tube is disconnected, and the current in this circuit is blocked; When it is low level, the switch tube is turned off, and the current flows through this channel, thus realizing the programmable current. Wherein, the value of n is consistent with the number of PMOS transistors in the M10 group. The structure of the NMOS branch is the same as that of the PMOS, except that an N tube is required as a switch.

In Figure 1, the DC offset calibration circuit and the variable gain circuit form a first-order low-pass feedback network. The DC offset calibration circuit includes a fully differential current connector (FBCCII), two active resistors, and resistor R2. The differential input ends of the fully differential current connector are respectively connected in series with an active resistor and then connected to the output end of the variable gain circuit. The transfer function of the feedback network is:

in, for The value at 0 frequency, is the pole frequency of the variable gain amplifier. Considering the DCOC feedback network, the gain of the whole system is:

Since the DCOC pole frequency Very low, at 0 frequency (near DC), the gain of the whole system is approximately:

if only Much larger than 1 is sufficient, and the DC error can be eliminated. When the intermediate frequency signal passes through, the signal frequency is much higher than , the feedback network is It is 0, which does not affect the application of the working frequency.

Since the input and output signals of the variable gain circuit are current signals, in order not to reduce the current, the voltage signal is taken at the output of the variable gain circuit, and the current is fed back to the input of the variable gain circuit, so a fully differential linear transconductance. In the present invention, the fully differential linear transconductance is composed of fully differential FBCCII and resistor R2, and the transconductance The size is:

Adjust the magnitude of the signal fed back from the DC offset calibration circuit to the input terminal of the variable gain circuit by adjusting the size of the resistor R2, that is, control the DCOC feedback depth and loop gain by changing the size of R2.

The fully differential current connector (FBCCII) is shown in Figure 5, including twenty-six MOS tubes from M1 to M26, resistors R3 and R4; NMOS tube M13, NMOS tube M11, NMOS tube M9, NMOS tube M7, NMOS tube The sources of M8, NMOS tube M10, NMOS tube M12, NMOS tube M14, NMOS tube M25, and NMOS tube M26 are all connected to external high level VDD, PMOS tube M15, PMOS tube M16, PMOS tube M17, PMOS tube M18, PMOS tube The sources of M19, PMOS transistor M20, PMOS transistor M21, and PMOS transistor M22 are all grounded, and the gates of PMOS transistors M15-M22 are connected to an external bias voltage source V _BIAS ; the drain of NMOS transistor M13 is connected to the drain of PMOS transistor M15 , and its connection point is used as the inverting output terminal Z _N of the current signal of the fully differential current connector; the drain of the NMOS transistor M11 is connected to the drain of the PMOS transistor M16, the drain of the NMOS transistor M9 is connected to the drain of the PMOS transistor M3, and the drain of the PMOS transistor M11 is connected to the drain of the PMOS transistor M3. The gate of M3 is connected to the drain of PMOS transistor M16 and used as the inverting input terminal X _N of the current signal of the fully differential current connector, the drain of NMOS transistor M7 is connected to the drains of PMOS transistors M4 and M1 at the same time, and the drain of PMOS transistor M4 The gate is connected to the DC level V _CM , the sources of the PMOS transistor M3 and the PMOS transistor M4 are connected to the drain of the PMOS transistor M17, the gates of the NMOS transistor M13 and the NMOS transistor M11 are connected to the drain of the PMOS transistor M4; The drains are connected to the drains of the PMOS transistors M2 and M5 at the same time, the gate of the PMOS transistor M1 is used as the voltage signal inverting input terminal Y _IN of the fully differential current connector, and the gate of the PMOS transistor M2 is used as the voltage signal of the fully differential current connector The non-inverting input terminal Y _PN , the sources of the PMOS transistors M1 and M2 are connected to the drain of the PMOS transistor M18, the gate of the PMOS transistor M5 is connected to the DC level V _CM ; the drain of the NMOS transistor M10 is connected to the drain of the PMOS transistor M6, and the PMOS transistor M10 is connected to the drain of the PMOS transistor M6. The sources of the transistors M5 and M6 are connected to the drain of the PMOS transistor M19, the gates of the NMOS transistor M7 and the NMOS transistor M8 are connected, the drain and the gate of the NMOS transistor M9 and the drain and the gate of the NMOS transistor M10 are in phase Connection, the drain of the NMOS transistor M12 is connected to the drain of the PMOS transistor M21, the drain of the PMOS transistor M6 is connected to the drain of the NMOS transistor M12 and used as the positive phase input terminal X _P of the current signal of the fully differential current connector; the NMOS transistor M14 The drain of the PMOS transistor M21 is connected to the drain of the PMOS transistor M21 and used as the current signal positive phase output terminal Z _P of the fully differential current connector, the gates of the NMOS transistors M12 and M14 are connected to the drain of the NMOS transistor M8; the drain of the NMOS transistor M25 Connect its gate to the drain of the PMOS transistor M23, and the drain of the NMOS transistor M26 to its gate and connect to the PMOS transistor M The drain of 24 and the gate of PMOS transistor M23 are connected to one end of resistor R3 and resistor R4 at the same time, the other end of resistor R3 is used as the positive phase input terminal X _P of the current signal of the fully differential current connector, and the other end of resistor R4 is used as the full differential current connector. The inverting input terminal X _N of the current signal of the differential current connector, the sources of the PMOS transistors M24 and M23 are connected to the drain of the PMOS transistor M22, and the gate of the PMOS transistor M24 is connected to the DC level V _CM .

Among them, the first P tube current mirror is composed of MOS transistors M15, M16, M7, M18, M19, M20, M21, and M22; the first differential input pair is composed of MOS transistors M1 and M2; the second differential input pair is composed of MOS transistors M3 and M4. Two differential input pairs; the third differential input pair consists of MOS transistors M5 and M6; a common-mode negative feedback circuit is composed of MOS transistors M23, M24, M25, M26, R3, R4, M7, and M8; MOS transistors M9 and M10 An active resistance forming a diode connection. The voltage signal input terminal and the current signal input terminal are low-impedance nodes, and the current signal output terminal is a high-impedance node. MOS tube M1 and MOS tube M2 are differential signal input, MOS tube M11 and MOS tube M12 are the output stages of the two-stage op amp, the low-impedance current input terminals of X _P and X _N are realized through feedback, and the output terminal Z _NP is a MOS tube The parallel connection of M14 and the channel modulating resistor of MOS transistor M21 is high impedance, and Z _N is also the same. MOS tubes M23, M24, M25, M26 and R3, R4 constitute a common-mode negative feedback circuit to stabilize the DC operating point of the circuit.

The active resistor R1 in DCOC in Figure 1 can adopt the active resistor design shown in Figure 6 . The active resistance includes four MOS transistors; the source of the first MOS transistor is respectively connected to the drain of the second MOS transistor and the drain of the third MOS transistor, and the drain of the first MOS transistor is respectively connected to the gate of the first MOS transistor electrode and the source of the second MOS transistor, the gate of the second MOS transistor is connected to the drain of the second MOS transistor, and the drain of the third MOS transistor is respectively connected to the gate of the third MOS transistor and the source of the fourth MOS transistor , the source of the third MOS transistor is respectively connected to the drain of the fourth MOS transistor and the gate of the fourth MOS transistor. In use, the four MOS tubes are all in a non-conducting state, and their DC resistance is very large, which can generally be realized or so, it is easier to achieve a lower DCOC pole frequency.

In the current mode variable gain amplifier circuit of the present invention, the signal input is low impedance, the output is high impedance, and the circulating signal is a current signal, which is not affected by the magnitude of the voltage. The single-ended input differential output current mode variable gain amplifier shown in Figure 3 adopts a Class-AB output structure, which greatly reduces the power consumption of the circuit. The current amplifier is not limited by the gain-bandwidth product, so it can be used at almost any gain without limiting the bandwidth.

The above is only a preferred embodiment of the present invention, and it should be pointed out that for those of ordinary skill in the art, some improvements and modifications can also be made without departing from the principles of the present invention. It should be regarded as the protection scope of the present invention.

Claims (5)

1. A current-mode variable gain amplifier, characterized by: the digital control circuit comprises a variable gain circuit, a functional digital control logic circuit and a direct current offset calibration circuit; the variable gain circuit comprises four stages of current fully differential programmable amplifiers, wherein the input end of the first stage of current fully differential programmable amplifier is used as the input end of the current mode variable gain amplifier, and the output end of the fourth stage of current fully differential programmable amplifier is used as the output end of the current mode variable gain amplifier; the functional digital control logic circuit is used for controlling the gain decibels of the variable gain circuit; and the direct current offset calibration circuit feeds back a low-frequency signal output by the fourth-stage current fully-differential programmable amplifier to the input end of the first-stage current fully-differential programmable amplifier to form a negative feedback loop.

2. A current-mode variable gain amplifier according to claim 1, wherein: the single-stage current fully-differential programmable amplifier is formed by reversely connecting two symmetrical single-ended input and differential output current followers; each current follower comprises M1-M19 MOS transistors and a bias current source I_BIASAnd first to sixth CDN units; the MOS transistors M1-M19 are single MOS transistors, M11, M13 and M19 are three groups of MOS transistors each comprising a plurality of PMOS transistors, and M10, M12 and M18 are three groups of MOS transistors each comprising a plurality of NMOS transistors; the source electrodes of the PMOS tube M1, the PMOS tube M2, the PMOS tube M9, the PMOS tube M11, the PMOS tube M13, the PMOS tube M15, the PMOS tube M17 and the PMOS tube M19 are all grounded, and the source electrodes of the NMOS tube M5, the NMOS tube M6, the NMOS tube M7, the NMOS tube M10, the NMOS tube M12, the NMOS tube M14, the NMOS tube M16, the NMOS tube M18 and the drain electrode of the PMOS tube M8 are all connected with an external high-level VDD; the grid electrode of the PMOS tube M1 is connected with the drain electrode thereof, and the bias current source I_BIASThe transistor is connected between the drain electrode of the PMOS transistor M1 and the drain electrode of the NMOS transistor M5; a bias voltage source is connected between the drain electrode of the NMOS transistor M5 and the drain electrode of the PMOS transistor M1, the drain electrode of the NMOS transistor M6 is connected with the drain electrode of the PMOS transistor M3, and the source electrode of the PMOS transistor M3 is connected with a direct current level V_CM(ii) a The drain electrode of the NMOS tube M7 is connected with the drain electrode of the PMOS tube M4, and the source electrode of the PMOS tube M4 is connected with the drain electrode of the PMOS tube M2; the gates of the PMOS transistor M3 and the PMOS transistor M4 are connected and connected to the drain of the NMOS transistor M6; the gates of the NMOS transistor M5, the NMOS transistor M6 and the NMOS transistor M7 are all connected to the drain of the NMOS transistor M5; the source electrode of the PMOS tube M8 is connected with the drain electrode of the PMOS tube M9, and the gate electrode of the PMOS tube M9 is connected with an external bias voltage source V_BIAS(ii) a The drain electrode of the NMOS tube M10 is connected with the first end of the first CDN unit, the input end of the second end of the first CDN unit is connected with the first end of the second CDN unit, and the second end of the second CDN unit is connected with the drain electrode of the PMOS tube M11; the drain electrode of the NMOS tube M12 is connected with the first end of the third CDN unit, the input end of the second end of the third CDN unit is connected with the first end of the fourth CDN unit, and the second end of the fourth CDN unit is connected with the first end of the fourth CDN unitThe drain electrode of the PMOS pipe M13; the drain electrode of the NMOS transistor M14 is connected to the drain electrode of the PMOS transistor M17, the drain electrode of the NMOS transistor M16 is connected to the drain electrode of the PMOS transistor M175, the drain electrode of the NMOS transistor M18 is connected to the first end of the fifth CDN unit, the second end of the fifth CDN unit is connected to the first end of the sixth CDN unit, and the second end of the sixth CDN unit is connected to the drain electrode of the PMOS transistor M19; the gates of the PMOS transistor M8, the NMOS transistor M10, the NMOS transistor M12 and the NMOS transistor M14 are all connected to the drain of the NMOS transistor M7, the gates of the MOS transistor M16 and the NMOS transistor M18 are all connected to the drain of the MOS transistor M16, the gates of the PMOS transistor M1 and the PMOS transistor M2 are all connected to the drain of the PMOS transistor M1, the gates of the PMOS transistor M11, the PMOS transistor M13 and the PMOS transistor M15 are all connected to the drain of the PMOS transistor M9, the gates of the PMOS transistor M17 and the PMOS transistor M19 are all connected to the drain of the PMOS transistor M17, the source of the PMOS transistor M4 is connected to the first end of the first CDN unit and serves as the input end of the current follower, the connection point of the third CDN unit and the fourth CDN unit serves as the in-phase output end of the current follower, and the connection point of the fifth unit and the sixth CDN unit serves as the reverse.

3. A current-mode variable gain amplifier according to claim 1, wherein: the direct current offset calibration circuit and the variable gain circuit form a first-order low-pass feedback network; the direct current offset calibration circuit comprises a fully differential current connector, two active resistors and a resistor R2; the differential input ends of the fully differential current splicer are respectively connected with the output end of the variable gain circuit after being connected with an active resistor in series; the resistor R2 is connected with a fully differential current connector to form a fully differential linear transconductance, the magnitude of a signal fed back to the input end of the variable gain circuit by the direct current offset calibration circuit is adjusted by adjusting the magnitude of the resistor R2, and the magnitude of the transconductance is(ii) a The transfer function of the feedback network is:

wherein,is the variable gain amplifier pole frequency;is composed ofA value at 0 frequency.

4. A current-mode variable gain amplifier according to claim 3, wherein: the fully differential current connector comprises twenty-six MOS transistors from M1 to M26, a resistor R3 and a resistor R4; the sources of the NMOS transistors M13, M11, M9, M7, M8, M10, M12, M14, M25 and M26 are all connected with an external high-level VDD, the sources of the PMOS transistors M15, M16, M17, M18, M19, M20, M21 and M22 are all grounded, the gates of the PMOS transistors M15-M22 are all connected with an external bias voltage source V_BIAS(ii) a The drain electrode of the NMOS tube M13 is connected with the drain electrode of the PMOS tube M15, and the connection point of the NMOS tube M13 and the PMOS tube M15 is used as the current signal inverting output end Z of the fully differential current connector_N(ii) a The drain electrode of the NMOS tube M11 is connected with the drain electrode of the PMOS tube M16, the drain electrode of the NMOS tube M9 is connected with the drain electrode of the PMOS tube M3, the grid electrode of the PMOS tube M3 is connected with the drain electrode of the PMOS tube M16 and is used as the inverting input end X of the current signal of the fully differential current connector_NThe drain of NMOS transistor M7 is connected to the drains of PMOS transistors M4 and M1, and the gate of PMOS transistor M4 is connected to DC level V_CMThe source electrodes of the PMOS tube M3 and the PMOS tube M4 are both connected with the drain electrode of the PMOS tube M17, and the grid electrodes of the NMOS tube M13 and the NMOS tube M11 are both connected with the drain electrode of the PMOS tube M4; the drain electrode of the NMOS tube M8 is simultaneously connected with the drain electrodes of the PMOS tubes M2 and M5, and the grid electrode of the PMOS tube M1 is used as the voltage signal inverting input end Y of the fully differential current connector_INThe grid of the PMOS tube M2 is used as the voltage signal non-inverting input end Y of the fully differential current connector_PNThe sources of the PMOS tubes M1 and M2 are both connected with the drain of the PMOS tube M18, and the gate of the PMOS tube M5 is connected with the DC level V_CM(ii) a The drain of the NMOS transistor M10 is connected with the drain of the PMOS transistor M6, the sources of the PMOS transistors M5 and M6 are both connected with the drain of the PMOS transistor M19, the gate of the NMOS transistor M7 is connected with the gate of the NMOS transistor M8, the drain of the NMOS transistor M9 is connected with the gate of the NMOS transistor M10, the drain of the NMOS transistor M12 is connected with the drain of the PMOS transistor M21, the drain of the PMOS transistor M6 is connected with the drain of the NMOS transistor M12 and serves as the positive phase input end X of the current signal of the fully differential current connector_P(ii) a The drain electrode of the NMOS tube M14 is connected with the drain electrode of the PMOS tube M21 and is used as the current signal positive phase output end Z of the fully differential current connector_PThe gates of the NMOS transistors M12 and M14 are both connected with the drain of the NMOS transistor M8; the drain electrode of the NMOS tube M25 is connected with the grid electrode thereof and the drain electrode of the PMOS tube M23, the drain electrode of the NMOS tube M26 is connected with the grid electrode thereof and the drain electrode of the PMOS tube M24, the grid electrode of the PMOS tube M23 is simultaneously connected with one ends of a resistor R3 and a resistor R4, and the other end of the resistor R3 is used as a positive phase input end X of a current signal of the fully differential current connector_PThe other end of the resistor R4 is used as the inverting input end X of the current signal of the fully differential current connector_NThe sources of the PMOS tubes M24 and M23 are both connected with the drain of the PMOS tube M22, and the gate of the PMOS tube M24 is connected with the DC level V_CM。

5. A current-mode variable gain amplifier according to claim 3, wherein: the active resistor comprises four MOS tubes; the source electrode of the first MOS tube is respectively connected with the drain electrode of the second MOS tube and the drain electrode of the third MOS tube, the drain electrode of the first MOS tube is respectively connected with the grid electrode of the first MOS tube and the source electrode of the second MOS tube, the grid electrode of the second MOS tube is connected with the drain electrode of the second MOS tube, the drain electrode of the third MOS tube is respectively connected with the grid electrode of the third MOS tube and the source electrode of the fourth MOS tube, and the source electrode of the third MOS tube is respectively connected with the drain electrode of the fourth MOS tube and the grid electrode of the fourth MOS tube.