CN113328711B - Constant cross-rail-to-rail input differential output high-speed programmable gain amplifier - Google Patents

Abstract

The invention discloses a constant cross-guide rail to rail input differential output high-speed programmable gain amplifier which is mainly used for meeting the amplification requirement of a signal chain system on high-frequency signals, reducing harmonic distortion of the high-frequency signals and transmitting the harmonic distortion to a rear-end high-speed analog-to-digital converter. The gain amplifier structure is formed by cascade connection of two constant gm single-ended output operational amplifiers serving as a first stage and a constant gm differential output operational amplifier serving as a second stage, and input signals adjust the proportion of feedback resistors according to external gain selection signals, so that the signals are amplified to target gain. Therefore, the invention has the advantages of good linearity, high speed, constant gm and real-time amplification.

Description

High Speed Programmable Gain Amplifier with Constant Across Rail-to-Rail Input Differential Output

technical field

The invention belongs to the technical field of integrated circuits, and in particular relates to a high-speed programmable gain amplifier with constant cross-rail-to-rail input differential output.

Background technique

The analog front end is the core module for processing analog signals in the signal system. It is widely used in data acquisition systems, sensors, radar communications, etc. It is a bridge connecting analog circuits and digital circuits. The analog front-end signal detects and amplifies the analog signal in nature, and then passes through the analog-to-digital converter, converts it into a digital signal that is easy to process, and sends it to the digital system for processing; while the Programmable Gain Amplifier (PGA) is an analog front-end module. One of the core components, it can amplify the signal to different times according to the size of the input signal to improve the dynamic range of the system.

Today, an important feature of the development of integrated circuits is integration and miniaturization. A highly integrated system chip can reduce the overall cost and make it easier to apply to the mobile portable market. As an important module of the signal system, the performance of the programmable gain amplifier has a crucial impact on the entire signal system, and it is the mainstream development trend to integrate it into the system chip; therefore, the high bandwidth, high linearity and gain range adjustment are relatively large A programmable gain amplifier is integral.

The traditional programmable gain amplifier generally adopts the instrumentation amplifier structure. As shown in Figure 1, the instrumentation amplifier adopts a two-stage amplifier, the first stage adopts the same-direction parallel differential amplifier, and the second stage adopts a basic differential amplifier, which has a high input impedance. , the common mode rejection ability is strong, the gain adjustment is convenient and so on. However, this structure can only be single-ended output, and is mostly used to amplify low-frequency signals. If high-frequency signals are amplified, there will be large gain errors and obvious harmonic distortion.

On the other hand, the traditional programmable gain amplifier has a certain range limit on the common-mode voltage of the input signal, so when the input common-mode voltage is close to the power supply voltage or ground, the programmable gain amplifier cannot work normally, and when the input signal is When the common-mode voltage deviation is large, the gain of the amplifier will fluctuate accordingly; for analog signals in nature, because the common-mode voltage is not constant, the performance of the programmable gain amplifier will be unstable, which is not conducive to application in integrated systems.

SUMMARY OF THE INVENTION

In view of the above, the present invention provides a high-speed programmable gain amplifier with constant input and differential output across rail-to-rail, which can be applied to amplify high-frequency signals to provide stable gain and low harmonic distortion.

A high-speed programmable gain amplifier with constant input and differential output across rail-to-rail, including 7 adjustable resistor arrays R ₁ to R ₇ , 2 first-stage operational amplifiers A1 and A2, and a second-stage operational amplifier A3 with differential output, wherein The non-inverting input end of A1 is connected to the non-inverting input signal V _IP , the output end of A1 is connected to one end of R ₁ and one end of R ₂ , the inverting input end of A1 is connected to the other end of R ₁ and one end of R ₇ , the output end of R ₂ is connected to the other end of R 1 and one end of R 7 . The other end is connected to the inverting input of A3 and one end of _R3 , the other end of _R3 is connected to the non-inverting output of A3 to generate the amplified non-inverting output signal V _OUTP , and the non-inverting input of A2 is connected to the inverting input signal V _IN , the output end of A2 is connected to one end of _R4 and one end of R5, the _inverting input end of A2 is connected to the other end of _R4 and the other end of _R7 , the other end of R5 is connected to the _noninverting input end of A3 and One end of R ₆ is connected, and the other end of R ₆ is connected to the inverting output terminal of A3 to generate an amplified inverting output signal V _OUTN .

Further, the adjustable resistor arrays R ₁ to R ₇ are formed by connecting a plurality of switch resistors in series, and the switch resistors are formed by a high linearity switch SW and a resistor in parallel; R ₁ and R ₄ , R ₂ and R _5. R ₃ and R ₆ , the serial number of switch resistors between them and the switch timing sequence are completely consistent.

Further, the high linearity switch SW includes five switch tubes M1-M5, wherein the source of M1 is connected to the working voltage VDD, the drain of M1 is connected to the source of M2, the drain of M4 and the substrate of M3, The gate of M1 is connected to the gate of M4 and the gate of M5 and is connected to the inverted clock signal CLKN, the gate of M2 is connected to the gate of M3 and is connected to the in-phase clock signal CLKP, the substrate of M2 is connected to the power supply voltage V _DD , The drain of M2 is connected to the source of M3, the source of M4 and the drain of M5 and serves as one end of SW, the drain of M3 is connected to the source of M5 and serves as the other end of SW, the substrate of M4 and the The substrate is connected to the power supply ground V _SS , M1 to M3 are PMOS tubes, and M4 to M5 are NMOS tubes.

Further, the high linearity switch SW includes 8 switch tubes M1-M8, wherein the source of M1 is connected to the working voltage VDD, the drain of M1 is connected to the source of M2, the drain of M8 and the substrate of M3, The gate of M1 is connected to the gate of M8, the gate of M7 and the gate of M6 in parallel with the inverted clock signal CLKN, the gate of M2 is connected to the gate of M3, the gate of M4 and the gate of M5 in parallel In-phase clock signal CLKP, the substrate of M2 and the substrate of M4 are connected to the power supply voltage V _DD , the drain of M2 is connected to the source of M3, the source of M8 and the drain of M7 as one end of SW, and the drain of M3 It is connected to the source of M4, the source of M7 and the drain of M6 and serves as the other end of SW, the drain of M4 is connected to the drain of M5, the source of M6 and the substrate of M7, the substrate of M8, the substrate of M6 The substrate and the source of M5 are connected to the power supply ground V _SS , M1 to M4 are PMOS tubes, and M5 to M8 are NMOS tubes.

Further, the first-level operational amplifiers A1 and A2 and the second-level operational amplifier A3 include:

Constant transconductance input stage for constant transconductance over rail-to-rail input range;

The gain amplifier stage provides gain amplification to the input signal through the folded cascode structure;

The cross-coupled output stage provides high linearity rail-to-rail output through a dual Double-Push cross-coupling structure.

Further, the two-stage operational amplifier A3 further includes a common-mode feedback module, which is used for clamping the output voltage of the cross-coupling output stage to a preset value.

Further, the constant transconductance input stage includes 21 switch tubes MA ₁ ～MA ₅ , MC ₁ , MC ₂ , MBA, MBAS, MA ₁ S, MA ₂ S, M ₁ N, M ₂ N, MS ₁ ～ MS ₄ , M ₁ NS, M ₂ NS, MBN, MBNS, wherein the source of MA ₃ is connected to the source of MA ₄ , the source of MC ₂ , the source of MS ₂ and the source of MS ₄ and is connected to the power supply voltage V _DD , the gate of MA ₄ is connected to the drain of MA ₂ , the drain of MA ₁ , the drain of MC ₁ and the gate and drain of MA ₃ , the gate of MA ₂ is connected to the gate of M ₂ N and The gate of MS ₃ is connected to the inverting input of the op amp, the gate of MA ₁ is connected to the gate of M ₁ N and the gate of MS ₁ as the non-inverting input of the op amp, the gate of MC ₁ is connected to the gate of MBA The gate, the gate of MBN and the gate of MBNS are connected to the reverse bias voltage VBN ₁ , the source of MA ₁ is connected to the source of MA ₂ and the drain of MBA, and the source of MBA is connected to the source of MC ₁ electrode, the source of MA ₅ , the source of MBAS, the drain of MS ₁ , the source of MBNS, the source of MBN and the drain of MS ₃ are connected to the power ground V _SS , the drain of MA ₄ is connected to the source of MBAS The gate and the gate and drain of MA ₅ are connected, the gate of MC ₂ is connected to the gate of MS ₂ and the gate of MS ₄ and is connected to the in-phase bias voltage VBP ₁ , the drain of MC ₂ is connected to the gate of MA ₁ S The source, the source of MA ₂ S and the drain of MBAS are connected, the drain of MS ₂ is connected to the gate of M ₁ NS, the gate of MA ₂ S and the source of MS ₁ , the drain of MS ₄ is connected to M The gate of ₂ NS, the gate of MA ₁ S and the source of MS ₃ are connected, the drain of MA ₁ S is connected with the drain of M ₁ NS and the drain of M ₁ N as the inverting output of the input stage, The drain of MA ₂ S is connected to the drain of M ₂ NS and the drain of M ₂ N as the non-inverting output of the input stage, the source of M ₁ NS is connected to the source of M ₂ NS and the drain of MBNS, M The source of ₁ N is connected to the source of M ₂ N and the drain of MBN, MA ₃ , MA ₄ , MC ₂ and MS ₁ to MS ₄ are PMOS transistors, MA ₁ , MA ₂ , MA ₅ , MC ₁ , MA ₁ S, MA ₂ S, MBA, MBAS, M ₁ NS, M ₂ NS, MBN, MBNS, M ₁ N, and M ₂ N are NMOS transistors.

Further, the gain amplifier stages in the first-stage operational amplifiers A1 and A2 include 10 switch tubes N1-N10, wherein the source of N7 is connected to the source of N8 and is connected to the power supply voltage V _DD , and the gate of N7 is connected to N8 The gate of N7 is connected to the non-inverting bias voltage VBP ₁ , the drain of N7 is connected to the source of N5 and is connected to the inverting output of the input stage, the drain of N8 is connected to the source of N6 and is connected to the non-inverting output of the input stage terminal, the gate of N5 is connected to the gate of N6 and connected to the same-phase bias voltage VBP ₂ , the drain of N5 is connected to the drain of N3, the gate of N1 and the gate of N2, the drain of N6 is connected to the drain of N9 The pole and gate are connected to the output port Z1 of the amplifier stage, the source of N9 is connected to the source of N10 as the output port Z2 of the amplifier stage, the drain of N4 is connected to the drain and gate of N10 as the output port of the amplifier stage Z3, the gate of N3 is connected to the gate of N4 and connected to the reverse bias voltage VBN ₂ , the source of N3 is connected to the drain of N1, the source of N4 is connected to the drain of N2, and the source of N1 is connected to N2 The source is connected to the power supply ground V _SS in parallel, N1-N4 and N9 are NMOS transistors, and N5-N8 and N10 are PMOS transistors.

Further, the gain amplifier stage in the two-stage operational amplifier A3 includes 14 switching transistors P1-P14, wherein the source of P7 is connected to the source of P8 and is connected to the power supply voltage V _DD , and the gate of P7 is connected to the gate of P8 The pole is connected to the non-inverting bias voltage VBP ₁ , the drain of P7 is connected to the source of P5 and is connected to the inverting output terminal of the input stage, the drain of P8 is connected to the source of P6 and is connected to the non-inverting output terminal of the input stage, The gate of P5 is connected to the gate of P6 and connected to the in-phase bias voltage VBP ₂ , the drain of P5 is connected to the drain and gate of P9 as the in-phase output port ZP1 of the amplifier stage, the source of P9 and the source of P10 It is connected to the non-inverting output port ZP2 as the amplifier stage, the drain of P13 is connected to the drain and gate of P10 as the non-inverting output port ZP3 of the amplifier stage, and the drain of P6 is connected to the drain and gate of P11 as the inverse of the amplifier stage. Phase output port ZN1, the source of P11 is connected to the source of P12 as the inverting output port ZN2 of the amplifier stage, the drain of P14 is connected to the drain and gate of P12 as the inverting output port ZN3 of the amplifier stage, and the The gate is connected to the gate of P14 and the reverse bias voltage VBN ₂ , the source of P13 is connected to the drain of P1 and the drain of P3, the source of P14 is connected to the drain of P2 and the drain of P4, The gate of P3 is connected to the gate of P4 and is connected to the common mode feedback voltage V _CFB , the gate of P1 is connected to the gate of P1 and is connected to the reverse bias voltage VBN ₁ , the source of P1 is connected to the source of P2, P3 The source of P4 and the source of P4 are connected in parallel with the power supply ground V _SS , P1-P4, P9, P11, P13 and P14 are NMOS tubes, P5-P8, P10 and P12 are PMOS tubes.

Further, the cross-coupling output stage in the first-stage operational amplifiers A1 and A2 includes a Double-Push circuit module, and the cross-coupling output stage in the second-stage operational amplifier A3 includes two Double-Push circuit modules in differential form. , the Double-Push circuit module includes a resistor R, a capacitor C and 18 switch tubes M11-M28, wherein the source of M12 and the source of M14, the source of M15, the source of M20, the source of M22 and the source of M28 The source of M12 is connected to the power supply voltage V _DD , the gate of M12 is connected to the gate of M11 and one end of the resistor R is connected to the output port Z2, ZN2 or ZP2 of the amplifier stage, the drain of M12 is connected to the drain of M11, M13 The drain and gate of M14, the drain and gate of M14, the source of M25 and the source of M26 are connected, the source of M11 is connected to the source of M13, the source of M16, the source of M19, the source of M21 And the source of M27 is connected to the power supply ground V _SS , the gate of M15 is connected to the output port Z1, ZN1 or ZP1 of the amplifier stage, the gate of M16 is connected to the output port Z3, ZN3 or ZP3 of the amplifier stage, and the source of M15 is connected to the output port Z1, ZN1 or ZP1 of the amplifier stage. The source of M18 is connected to the source of M17, the source of M17 is connected to the source of M16, the drain of M17 is connected to the gate of M28 and the gate and drain of M20, the gate of M22 is connected to the in-phase bias voltage VBP ₁ , and the The gate is connected to the in-phase bias voltage VBP ₂ , the gate of M23 is connected to the reverse-phase bias voltage VBN ₂ , the gate of M21 is connected to the reverse-phase bias voltage VBN ₁ , the drain of M22 is connected to the source of M24, and the drain of M24 The pole is connected to the gate of M17 and the gate and drain of M25, the drain of M18 is connected to the gate of M27 and the gate and drain of M19, the drain of M23 is connected to the gate of M18 and the gate and drain of M26. The drain is connected to the drain, the drain of M21 is connected to the source of M23, the other end of the resistor R is connected to one end of the capacitor C, the other end of the capacitor C is connected to the drain of M28 and the drain of M27 as the output end of the output stage, M11, M13, M15, M17, M19, M21, M23, M25 and M27 are NMOS transistors, and M12, M14, M16, M18, M20, M22, M24, M26 and M28 are PMOS transistors.

Further, the common mode feedback module includes five switch tubes M49-M53, two resistors R3-R4 and C3-C4, wherein the source of M49 is connected to the power supply voltage V _DD , the drain of M49 and the source of M50 and The source of M51 is connected to the source, the gate of M50 is connected to the input common mode voltage V _CM , the gate of M51 is connected to one end of the resistor R3, one end of the resistor R4, one end of the capacitor C3 and one end of the capacitor C4, and the other end of the resistor R3 is connected to The other end of the capacitor C3 is connected to the non-inverting output terminal of the output stage in parallel, the other end of the resistor R4 is connected to the other end of the capacitor C4 and connected to the inverting output terminal of the output stage, and the drain of M50 is connected to the drain and gate of M52. And generate a common mode feedback voltage V _CFB , the drain of M51 is connected to the drain and gate of M53, the source of M52 is connected to the source of M53 and connected to the power ground V _SS , M49~M51 are PMOS tubes, M52 and M53 For the NMOS tube.

Based on the above technical solutions, the present invention has the following beneficial technical effects:

1. The present invention can realize the input and output rail-to-rail, and improve the input swing of the programmable gain amplifier.

2. The present invention can provide constant transconductance, so that under different common mode input voltages, the gain is stable and the performance of the programmable gain amplifier is stable.

3. The present invention can provide a certain output driving capability, and the output signal can be directly provided to the analog-to-digital converter at the back end without additional driving modules.

4. The present invention can be applied to the amplification of high frequency signals, provides low gain error and low harmonic distortion, and can also maintain the performance of low frequency signals.

Description of drawings

FIG. 1 is a schematic diagram of the structure of a conventional instrumentation amplifier.

FIG. 2 is a schematic structural diagram of a high-speed programmable gain amplifier of the present invention.

FIG. 3 is a schematic structural diagram of an adjustable resistor array.

FIG. 4 is a schematic structural diagram of a high linearity switch.

FIG. 5 is a schematic diagram of a high linearity switch structure using a deep hydrazine process.

FIG. 6 is a schematic structural diagram of a constant transconductance input stage.

FIG. 7 is a schematic diagram of a simulation waveform of the transconductance of the input stage.

FIG. 8 is a schematic structural diagram of the first-stage operational amplifier.

FIG. 9 is a schematic diagram of the structure of the second-stage operational amplifier.

Detailed ways

In order to describe the present invention more specifically, the technical solutions of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

The present invention has a constant cross-rail-to-rail input differential output high-speed programmable gain amplifier, adopts an instrument-like amplifier structure, and realizes gain adjustment through a resistor array network; The first-stage op amp with high gain and wide bandwidth reduces the design difficulty of a single-stage op amp, and replaces the original single-ended output op amp with a differential output op amp for the second stage. The amplifier reduces one operational amplifier, and at the same time can make the output common mode voltage adjustable, and the application occasions are more extensive, and the application occasions are more extensive. The two-stage op amps use all-N input differential pairs to replace the original P-N input differential pairs, which avoids the influence of P-N input pair tube mismatch on constant gm, and the addition of a feedforward path elimination module further reduces the gm deviation, making the gm deviation The minimum can reach within 5%; and the two-stage op amp adopts a constant gm design, which can make the performance of the second-stage op amp not affected by the output swing of the first-stage op amp, and improve the stability of the overall performance. The output stage of the first-stage op amp adopts a Double-Push cross-coupling structure to enhance the driving capability and reduce the impact of resistance switching on the performance of the op-amp; the second-stage op amp adopts a double-Push cross-coupling structure and adopts a common mode feedback design. The output voltage is common-mode clamped to a specified voltage, resulting in a differential rail-to-rail output with high linearity and high drive capability.

The structure of the gain amplifier of the present invention is shown in Figure 2, which includes a co-directional parallel differential amplifier (A1, A2 as the first stage operational amplifier), a differential input differential output operational amplifier (A3 as the second stage operational amplifier) and an adjustable resistor array , the same-direction parallel differential amplifier (A1, A2) can provide rail-to-rail input and output, maintain a constant gm, and can maintain the advantages of high input impedance and strong common mode rejection of the instrumentation amplifier, and can be used as a separate op amp to adjust gain, reducing the difficulty of op amp bandwidth design. The design of rail-to-rail input and constant gm can increase the input signal amplitude, and can provide relatively stable gain, improve the performance of the entire programmable gain amplifier, and because the input signals V _IP and V _IN are both positive from the op amp terminal input, so it can offset a certain input offset effect. The gain provided by the first stage op amp is:

The second-stage differential input differential output op amp still adopts the rail-to-rail input and output, constant gm design, so that it matches the output of the first stage, and at the same time reduces the situation of "top clipping" of the output signal; on the other hand, Because programmable gain amplifiers are usually connected to analog-to-digital converters, a "negative resistance" is used as the drive output design to avoid distortion when the output signal enters the analog-to-digital converter. The gain provided by the second stage op amp is:

The adjustable resistance array is used to adjust the gain of the programmable gain amplifier. It is mainly realized by the external coding control switch. The unit resistance of the adjustable resistance array needs to be based on the actual gain requirements. Too large or too small resistance will easily cause phase On the other hand, the high linearity control switch can reduce the influence of harmonics and improve the overall amplifier performance. Therefore, the gain of the overall programmable gain amplifier is:

Among them: resistors R1, R2, R3, and R _gain are composed of adjustable resistor arrays. As shown in Figure 3, the adjustable resistor array is composed of resistors and switches. The resistors R1, R2, R3, and R _gain are regulated by external coding control switches. The resistance value is used to adjust the gain of the programmable gain amplifier. The control switch is implemented by a switch with high linearity. As shown in Figure 4, when the transmission gate is turned off, the tail current source is turned on, and the body of M3 is connected to VDD. When the transmission gate is turned on, the tail current source is turned off, and the body of M3 is turned off. Connected to the S terminal, this connection method can keep the on-resistance of the transmission gate constant, thereby reducing the nonlinearity introduced by the switch and improving the linearity. If the deep hydrazine process is used, the switch shown in Figure 5 can be used. Compared with Figure 4, a pair of transmission gates are added, and M7 also adopts the same connection method as M3 to keep the on-resistance constant and further reduce the switch Introduced nonlinearity.

The traditional rail-to-rail constant gm differential input stage is implemented with N-P complementary input pair tubes, and the constant gm over the full range of the common mode input is achieved by compensating 3 times the input pair tube tail current, but due to the compensation 3 Double the tail current, resulting in the change of the slew rate SR in the common mode input range. At the same time, under the influence of process and temperature, the gm deviation of about 12% can be caused due to the mismatch of carrier mobility between the N tube and the P tube. The constant gm in the present invention is realized by the full N-type input pair tube, which avoids the inherent deviation of the N-P MOS tube, does not need to compensate the input pair tube tail current, and can realize constant gm and SR, gm deviation control in the full range of the common mode input Within 5%, and there are no frequency response and CMRR attenuation issues. As shown in FIG. 6 , in this embodiment, the rail-to-rail common mode input full-range constant gm is specifically implemented as follows:

When the common-mode input is near the ground stage, the input pair of transistors M ₁ N and M ₂ N are turned off, the source follower input transistors MS1 and MS2 are turned on, and the other pair of N-type input transistors M ₁ NS and M ₂ NS are raised. The input voltages V _i ⁺ sh, V _i ^- sh, M ₁ NS, M ₂ NS are in a conducting state. Correspondingly, MA ₁ and MA ₂ in the feedforward path elimination module are in the off state, so the input pair tubes MA ₁ S and MA ₂ S corresponding to M ₁ NS and M ₂ NS are in the off state because there is no tail current. In this interval, only the input pair tubes M ₁ NS and M ₂ NS are in a conducting state, providing gm ₀ .

When the common mode input is in the middle stage, the input pair transistors M ₁ N and M ₂ N are turned on, and at the same time, M ₁ NS and M ₂ NS are also in a conducting state. Correspondingly, MA ₁ and MA ₂ in the feed-forward path elimination module are turned on, and the input pair tubes MA ₁ S and MA ₂ S are turned on. Since the polarity of the input voltage of the pair tubes in the feed-forward path elimination module is opposite to that of the main module, the output pair is opposite to that of the main module. The contribution of -gm ₀ is used to offset the gm ₀ contributed by M ₁ NS and M ₂ NS to the output. In this interval, the input pair of tubes M ₁ N, M ₂ N, M ₁ NS, and M ₂ NS are all in the conduction state At the same time, the pair tubes MA ₁ , MA ₂ , MA ₁ S and MA ₂ S in the feedforward path elimination module are also turned on, and the final transconductance contributed to the output is gm ₀ .

When the common mode input is close to the power supply voltage stage, since MS1 and MS2 are turned off, M ₁ NS and M ₂ NS are in a conducting state, but they do not contribute to the output transconductance. Correspondingly, MA ₁ and MA ₂ in the feedforward path elimination module are turned _on , and the input to the tubes MA ₁ S and MA ₂ S is turned _on but has no gain contribution to the output. ₁ NS and M ₂ NS are in the conducting state, and at the same time, the paired tubes MA ₁ , MA ₂ , MA ₁ S, and MA ₂ S in the feedforward path elimination module are also turned on. Since the source follower stage is turned off, it finally contributes to the output. The transconductance is gm ₀ .

Therefore, over the full range of the common-mode input voltage, the rail-to-rail input stage contribution is constant across gm ₀ and the slew rate SR remains constant. As shown in Figure 7, the simulation result is that under the full range of the common mode input, the maximum deviation of the transconductance gm of the input stage is 5.38%.

As shown in FIG. 8 , the output stage of this embodiment adopts a Double-Push cross-coupling output stage, which provides a rail-to-rail output swing and has a large driving capability at the same time. Compared with the general class-AB output, the use of cross-coupling can provide higher linearity, and the Double-Push is used to obtain the differentially driven output, thereby obtaining a larger output current. As shown in Figure 9, the second-stage op amp adopts a double-Push cross-coupling structure and adds common-mode feedback, so that the output common-mode voltage can be clamped to the pointing voltage, resulting in a differential rail-to-rail with high linearity and large driving capability. output. The specific implementation of the Double-Push cross-coupling output stage is as follows:

First, MOS tubes M9, M10 copy the cascode input stage current to M15, M16; MOS tubes M21, M22, M23, M24 copy one of the cascode branch currents, and then copy to M17, M18 through M25, M26; M19, M20 will The crossover current is proportionally copied to the output tubes M27 and M28 to obtain the output current; the MOS tubes M11, M12, M13 and M14 form an inverter to obtain the node voltage B that is inverse to the voltage at the input end A of the output stage, and the output stage is obtained Finally, the differential input terminals A and B of the output stage amplify the AC-changing signal and output it to obtain a larger dynamic output current.

The above description of the embodiments is for the convenience of those of ordinary skill in the art to understand and apply the present invention. It will be apparent to those skilled in the art that various modifications to the above-described embodiments can be readily made, and the general principles described herein can be applied to other embodiments without inventive effort. Therefore, the present invention is not limited to the above-mentioned embodiments, and improvements and modifications made by those skilled in the art according to the disclosure of the present invention should all fall within the protection scope of the present invention.

Claims (8)

1. A high-speed programmable gain amplifier with constant input and differential output across rail-to-rail, including 7 adjustable resistor arrays R ₁ to R ₇ , 2 first-stage operational amplifiers A1 and A2, and a second-stage operational amplifier A3 with differential output , which is characterized in that the non-inverting input terminal of A1 is connected to the non-inverting input signal V _IP , the output terminal of A1 is connected to one end of R ₁ and one end of R ₂ , and the inverting input terminal of A1 is connected to the other end of R ₁ and one end of R ₇ connected, the other end of R ₂ is connected to the inverting input end of A3 and one end of R ₃ , the other end of R ₃ is connected to the non-inverting output end of A3 to generate the amplified non-inverting output signal V _OUTP , and the non-inverting input end of A2 is connected Inverting the input signal V _IN , the output end of A2 is connected to one end of R ₄ and one end of R ₅ , the inverting input end of A2 is connected to the other end of R ₄ and the other end of R ₇ , and the other end of R ₅ is connected to A3 The non _- inverting input end of R6 is connected with one end of R6, and the other end of _{R6 is connected with the inverting output end of A3 to generate the amplified inverting output signal VOUTN ;} The first-level operational amplifiers A1 and A2 and the second-level operational amplifier A3 include: Constant transconductance input stage for constant transconductance over rail-to-rail input range; The gain amplifier stage provides gain amplification to the input signal through the folded cascode structure; Cross-coupling output stage, providing high linearity rail-to-rail output through dual Double-Push cross-coupling structure; The two-stage operational amplifier A3 further includes a common-mode feedback module, which is used for clamping the output voltage of the cross-coupling output stage at a preset value; The cross-coupling output stage in the first-stage operational amplifiers A1 and A2 includes a Double-Push circuit module, and the cross-coupling output stage in the second-stage operational amplifier A3 includes two Double-Push circuit modules in differential form. The Double-Push circuit module includes a resistor R, a capacitor C and 18 switches M11-M28, wherein the source of M12 and the source of M14, the source of M15, the source of M20, the source of M22 and the source of M28 Connected and connected to the power supply voltage V _DD , the gate of M12 is connected to the gate of M11 and one end of the resistor R is connected to the output port Z2, ZN2 or ZP2 of the amplifier stage, the drain of M12 is connected to the drain of M11 and the drain of M13 It is connected to the gate, the drain and gate of M14, the source of M25 and the source of M26, the source of M11 is connected to the source of M13, the source of M16, the source of M19, the source of M21 and the source of M27 The source is connected to the power supply ground V _SS , the gate of M15 is connected to the output port Z1, ZN1 or ZP1 of the amplifier stage, the gate of M16 is connected to the output port Z3, ZN3 or ZP3 of the amplifier stage, the source of M15 and the source of M18 The source of M17 is connected to the source of M16, the drain of M17 is connected to the gate of M28 and the gate and drain of M20, the gate of M22 is connected to the same-phase bias voltage VBP ₁ , and the gate of M24 is connected to In-phase bias voltage VBP ₂ , the gate of M23 is connected to the reverse-phase bias voltage VBN ₂ , the gate of M21 is connected to the reverse-phase bias voltage VBN ₁ , the drain of M22 is connected to the source of M24, and the drain of M24 is connected to M17 The gate of M25 is connected to the gate and drain of M25, the drain of M18 is connected to the gate of M27 and the gate and drain of M19, the drain of M23 is connected to the gate of M18 and the gate and drain of M26 , the drain of M21 is connected to the source of M23, the other end of the resistor R is connected to one end of the capacitor C, the other end of the capacitor C is connected to the drain of M28 and the drain of M27 as the output end of the output stage, M11, M13 , M15, M17, M19, M21, M23, M25 and M27 are NMOS transistors, M12, M14, M16, M18, M20, M22, M24, M26 and M28 are PMOS transistors. 2 . The high-speed programmable gain amplifier according to claim 1 , wherein the adjustable resistor arrays R ₁ to R ₇ are formed by connecting a plurality of switch resistors in series, and the switch resistors are composed of high linearity switches SW and SW. 3 . A resistor is formed in parallel; R ₁ and R ₄ , R ₂ and R ₅ , R ₃ and R ₆ , the serial number of switch resistors and the switch timing between them are completely consistent. 3 . The high-speed programmable gain amplifier according to claim 2 , wherein the high-linearity switch SW comprises five switch tubes M1 to M5 , wherein the source of M1 is connected to the working voltage VDD, and the drain of M1 is connected to the working voltage VDD. 4 . The source of M2, the drain of M4 and the substrate of M3 are connected, the gate of M1 is connected to the gate of M4 and the gate of M5 and connected to the inverted clock signal CLKN, the gate of M2 is connected to the gate of M3 and connected The in-phase clock signal CLKP is connected, the substrate of M2 is connected to the power supply voltage V _DD , the drain of M2 is connected to the source of M3, the source of M4 and the drain of M5 as one end of SW, the drain of M3 is connected to the source of M5 The electrodes are connected to each other and serve as the other end of the SW. The substrate of M4 and the substrate of M5 are connected to the power ground V _SS , M1 to M3 are PMOS transistors, and M4 to M5 are NMOS transistors. 4 . The high-speed programmable gain amplifier according to claim 2 , wherein the high-linearity switch SW comprises 8 switch tubes M1 to M8 , wherein the source of M1 is connected to the working voltage VDD, and the drain of M1 is connected to the operating voltage VDD. 5 . The source of M2, the drain of M8 and the substrate of M3 are connected, the gate of M1 is connected to the gate of M8, the gate of M7 and the gate of M6 and connected to the inverted clock signal CLKN, the gate of M2 is connected to the gate of M3 The gate of M2, the gate of M4 and the gate of M5 are connected and connected to the same-phase clock signal CLKP, the substrate of M2 and the substrate of M4 are connected to the power supply voltage V _DD , the drain of M2 is connected to the source of M3 and the source of M8 And the drain of M7 is connected to one end of SW, the drain of M3 is connected to the source of M4, the source of M7 and the drain of M6 and is connected to the other end of SW, the drain of M4 is connected to the drain of M5, the drain of M6 The source of M7 is connected to the substrate of M7, the substrate of M8, the substrate of M6 and the source of M5 are connected to the power supply ground V _SS , M1-M4 are PMOS tubes, and M5-M8 are NMOS tubes. 5 . The high-speed programmable gain amplifier according to claim 1 , wherein the constant transconductance input stage comprises 21 switch tubes MA ₁ ˜MA ₅ , MC ₁ , MC ₂ , MBA, MBAS, and MA ₁ S . , MA ₂ S, M ₁ N, M ₂ N, MS ₁ to MS ₄ , M ₁ NS, M ₂ NS, MBN, MBNS, where the source of MA ₃ is the same as the source of MA ₄ , the source of MC ₂ , The source of MS ₂ and the source of MS ₄ are connected to the power supply voltage V _DD , the gate of MA ₄ is connected to the drain of MA ₂ , the drain of MA ₁ , the drain of MC ₁ and the gate and drain of MA ₃ The gate of MA ₂ is connected to the gate of M ₂ N and the gate of MS ₃ as the inverting input of the op amp, the gate of MA ₁ is connected to the gate of M ₁ N and the gate of MS ₁ As the non-inverting input terminal of the operational amplifier, the gate of MC ₁ is connected to the gate of MBA, the gate of MBN and the gate of MBNS and is connected to the reverse bias voltage VBN ₁ , the source of MA ₁ and the source of MA ₂ and the drain of MBA, which is connected to the source of MC ₁ , the source of MA ₅ , the source of MBAS, the drain of MS ₁ , the source of MBNS, the source of MBN and the drain of MS ₃ Connected and connected to the power supply ground V _SS , the drain of MA ₄ is connected to the gate of MBAS and the gate and drain of MA ₅ , the gate of MC ₂ is connected to the gate of MS ₂ and the gate of MS ₄ and connected in phase Bias voltage VBP ₁ , the drain of MC ₂ is connected to the source of MA ₁ S, the source of MA ₂ S and the drain of MBAS, the drain of MS ₂ is connected to the gate of M ₁ NS and the gate of MA ₂ S The electrode of MS ₁ is connected to the source electrode of MS 1, the drain electrode of MS ₄ is connected to the gate electrode of M ₂ NS, the gate electrode of MA ₁ S and the source electrode of MS ₃ , the drain electrode of MA ₁ S is connected to the drain electrode of M ₁ NS and The drain of M ₁ N is connected to the inverting output of the input stage, the drain of MA ₂ S is connected to the drain of M ₂ NS and the drain of M ₂ N as the non-inverting output of the input stage, and the source of M ₁ NS The electrode is connected to the source electrode of M ₂ NS and the drain electrode of MBNS, the source electrode of M ₁ N is connected to the source electrode of M ₂ N and the drain electrode of MBN, and MA ₃ , MA ₄ , MC ₂ and MS ₁ to MS ₄ are PMOS transistors, MA ₁ , MA ₂ , MA ₅ , MC ₁ , MA ₁ S, MA ₂ S, MBA, MBAS, M ₁ NS, M ₂ NS, MBN, MBNS, M ₁ N and M ₂ N are NMOS transistors. 6 . The high-speed programmable gain amplifier according to claim 1 , wherein the gain amplifier stages in the first-stage operational amplifiers A1 and A2 include 10 switch tubes N1 to N10 , wherein the source of N7 is the same as the source of N8 . The source is connected to the power supply voltage V _DD , the gate of N7 is connected to the gate of N8 and is connected to the in-phase bias voltage VBP ₁ , the drain of N7 is connected to the source of N5 and is connected to the inverting output of the input stage, N8 The drain of N6 is connected to the source of N6 and is connected to the non-inverting output terminal of the input stage, the gate of N5 is connected to the gate of N6 and is connected to the in-phase bias voltage VBP ₂ , the drain of N5 is connected to the drain of N3 and the gate of N1 The pole and the gate of N2 are connected, the drain of N6 is connected to the drain and gate of N9 as the output port Z1 of the amplifier stage, the source of N9 is connected to the source of N10 as the output port Z2 of the amplifier stage, and the drain of N4 The pole is connected to the drain and gate of N10 as the output port Z3 of the amplifier stage, the gate of N3 is connected to the gate of N4 and is connected to the reverse bias voltage VBN ₂ , the source of N3 is connected to the drain of N1, the N4 The source of N2 is connected to the drain of N2, the source of N1 is connected to the source of N2 and connected to the power supply ground V _SS , N1-N4 and N9 are NMOS tubes, and N5-N8 and N10 are PMOS tubes. 7 . The high-speed programmable gain amplifier according to claim 1 , wherein the gain amplifier stage in the two-stage operational amplifier A3 comprises 14 switching transistors P1 to P14 , wherein the source of P7 and the source of P8 Connected and connected to the power supply voltage V _DD , the gate of P7 is connected to the gate of P8 and connected to the in-phase bias voltage VBP ₁ , the drain of P7 is connected to the source of P5 and is connected to the inverting output of the input stage, and the drain of P8 The pole is connected to the source of P6 and is connected to the non-inverting output terminal of the input stage, the gate of P5 is connected to the gate of P6 and is connected to the in-phase bias voltage VBP ₂ , the drain of P5 is connected to the drain and gate of P9 as amplifying The non-inverting output port ZP1 of the stage, the source of P9 is connected to the source of P10 as the non-inverting output port ZP2 of the amplifier stage, the drain of P13 is connected to the drain and gate of P10 as the non-inverting output port ZP3 of the amplifier stage, and the The drain is connected to the drain and gate of P11 as the inverting output port ZN1 of the amplifier stage, the source of P11 is connected to the source of P12 as the inverting output port ZN2 of the amplifier stage, the drain of P14 and the drain of P12 And the gate is connected to the inverting output port ZN3 as the amplifier stage, the gate of P13 is connected to the gate of P14 and is connected to the reverse bias voltage VBN ₂ , the source of P13 is connected to the drain of P1 and the drain of P3, The source of P14 is connected to the drain of P2 and the drain of P4, the gate of P3 is connected to the gate of P4 and connected to the common-mode feedback voltage V _CFB , the gate of P1 is connected to the gate of P1 and connected to the reverse bias Set the voltage VBN ₁ , the source of P1 is connected to the source of P2, the source of P3 and the source of P4 and connected to the power supply ground V _SS , P1-P4, P9, P11, P13 and P14 are NMOS transistors, P5-P8 , P10 and P12 are PMOS tubes. 8 . The high-speed programmable gain amplifier according to claim 1 , wherein the common mode feedback module comprises five switch tubes M49 to M53 , two resistors R3 to R4 and C3 to C4 , wherein the source of M49 Connected to the power supply voltage V _DD , the drain of M49 is connected to the source of M50 and the source of M51, the gate of M50 is connected to the input common mode voltage V _CM , the gate of M51 is connected to one end of the resistor R3, one end of the resistor R4, the capacitor One end of C3 is connected to one end of capacitor C4, the other end of resistor R3 is connected to the other end of capacitor C3 and is connected to the non-inverting output end of the output stage, and the other end of resistor R4 is connected to the other end of capacitor C4 and is connected to the inverting phase of the output stage At the output end, the drain of M50 is connected to the drain and gate of M52 to generate a common mode feedback voltage V _CFB , the drain of M51 is connected to the drain and gate of M53, the source of M52 is connected to the source of M53 and Connect to the power ground V _SS , M49-M51 are PMOS tubes, M52 and M53 are NMOS tubes.

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