Nothing Special   »   [go: up one dir, main page]

Kasapaki et al., 2013 - Google Patents

Router designs for an asynchronous time-division-multiplexed network-on-chip

Kasapaki et al., 2013

View PDF
Document ID
7541051299048534917
Author
Kasapaki E
Sparsø J
Sørensen R
Goossens K
Publication year
Publication venue
2013 Euromicro Conference on Digital System Design

External Links

Snippet

In this paper we explore the design of an asynchronous router for a time-division- multiplexed (TDM) network-on-chip (NOC) that is being developed for a multi-processor platform for hard real-time systems. TDM inherently requires a common time reference, and …
Continue reading at www.es.ele.tue.nl (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234—Action, measure or step performed to reduce power consumption
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—INDEXING SCHEME RELATING TO CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. INCLUDING HOUSING AND APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B60/00—Information and communication technologies [ICT] aiming at the reduction of own energy use
    • Y02B60/10—Energy efficient computing
    • Y02B60/12—Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply
    • Y02B60/1207—Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply acting upon the main processing unit
    • Y02B60/1217—Frequency modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Switching fabric construction
    • H04L49/109—Switching fabric construction integrated on microchip, e.g. switch-on-chip

Similar Documents

Publication Publication Date Title
Kasapaki et al. Argo: A real-time network-on-chip architecture with an efficient GALS implementation
Bjerregaard et al. Implementation of guaranteed services in the MANGO clockless network-on-chip
Benini et al. Network-on-chip architectures and design methods
Panades et al. A low cost network-on-chip with guaranteed service well suited to the GALS approach
Horak et al. A low-overhead asynchronous interconnection network for GALS chip multiprocessors
Kasapaki et al. Argo: A time-elastic time-division-multiplexed noc using asynchronous routers
Kasapaki et al. Router designs for an asynchronous time-division-multiplexed network-on-chip
Gebhardt et al. Design of an energy-efficient asynchronous NoC and its optimization tools for heterogeneous SoCs
Sparsø Design of networks-on-chip for real-time multi-processor systems-on-chip
Psarras et al. Networks-on-chip with double-data-rate links
Ax et al. Comparing synchronous, mesochronous and asynchronous NoCs for GALS based MPSoCs
Gebhardt et al. Comparing energy and latency of asynchronous and synchronous NoCs for embedded SoCs
Jain et al. Asynchronous bypass channels: Improving performance for multi-synchronous nocs
Nasirian et al. Low-latency power-efficient adaptive router design for network-on-chip
Gilabert et al. Exploring high-dimensional topologies for NoC design through an integrated analysis and synthesis framework
Song et al. Asynchronous spatial division multiplexing router
Ludovicix et al. Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs
Pham et al. A 64-PE folded-torus intra-chip communication fabric for guaranteed throughput in network-on-chip based applications
Yang et al. WaveSync: Low-latency source-synchronous bypass network-on-chip architecture
Gibiluka et al. BAT-Hermes: a transition-signaling bundled-data NoC router
You et al. Performance evaluation of elastic GALS interfaces and network fabric
Gill et al. A low-latency adaptive asynchronous interconnection network using bi-modal router nodes
Fischer et al. FlooNoC: A Multi-Tbps Wide NoC for Heterogeneous AXI4 Traffic
Zhu et al. BiLink: A high performance NoC router architecture using bi-directional link with double data rate
Peh et al. On-chip networks for multicore systems