Nothing Special   »   [go: up one dir, main page]

Horak et al., 2011 - Google Patents

A low-overhead asynchronous interconnection network for GALS chip multiprocessors

Horak et al., 2011

View PDF
Document ID
14792524704060212438
Author
Horak M
Nowick S
Carlberg M
Vishkin U
Publication year
Publication venue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

External Links

Snippet

A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS) chip multiprocessors. The network eliminates the need for global clock distribution, and can interface multiple synchronous timing domains operating …
Continue reading at www.umiacs.umd.edu (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Similar Documents

Publication Publication Date Title
Horak et al. A low-overhead asynchronous interconnection network for GALS chip multiprocessors
Monemi et al. ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform
Kwon et al. OpenSMART: Single-cycle multi-hop NoC generator in BSV and Chisel
Tran et al. Achieving high-performance on-chip networks with shared-buffer routers
US8362802B2 (en) Asynchronous digital circuits including arbitration and routing primitives for asynchronous and mixed-timing networks
Coates et al. The Post Office experience: Designing a large asynchronous chip
Dimitrakopoulos et al. Fast arbiters for on-chip network switches
Ma et al. Networks-on-chip: from implementations to programming paradigms
Rao et al. Vix: Virtual input crossbar for efficient switch allocation
Lin et al. Communication-driven task binding for multiprocessor with latency insensitive network-on-chip
Jiang et al. A lightweight early arbitration method for low-latency asynchronous 2D-mesh NoC's
Fattah et al. A high throughput low power FIFO used for GALS NoC buffers
Qian et al. Fsnoc: A flit-level speedup scheme for network on-chips using self-reconfigurable bidirectional channels
Liu et al. A dynamic adaptive arbiter for Network-on-Chip
Balakrishnan et al. Design and implementation of congestion aware router for network-on-chip
Yan et al. A high throughput router with a novel switch allocator for network on chip
Gill et al. A low-latency adaptive asynchronous interconnection network using bi-modal router nodes
Daneshtalab et al. A systematic reordering mechanism for on-chip networks using efficient congestion-aware method
Zhu et al. BiLink: A high performance NoC router architecture using bi-directional link with double data rate
Bahn et al. On design and application mapping of a Network-on-Chip (NoC) architecture
Sadrosadati et al. An efficient DVS scheme for on-chip networks
Pande et al. Performance optimization for system-on-chip using network-on-chip and data compression
Effiong et al. Exploration of a scalable and power-efficient asynchronous Network-on-Chip with dynamic resource allocation
Krishna et al. Interconnect Modeling for Homogeneous and Heterogeneous Multiprocessors
Principal Power & Area Efficient Router in 2-D Mesh Network-on-Chip Using Low Power Methodology-Clock Gating Techniques