Freedom U Software Development Kit (FUSDK)

MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn't define TrustZone-like primitives to provide hardware separation. To shield critical functionality from untrusted third-party components, MultiZone provides hardware-enforced, software-defined separation of multi

SiFive OpenEmbedded / Yocto BSP Layer

This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkeley.

RISC-V Debugger

RISCV port of the Slackware distribution

SiFive: development platform for PlatformIO

Reverse engineer of the hifive1 rev b bootloader since the source has not been released

Archived, please use official SiFive dev/platform

Play and learn with the SiFive HiFive1 board featuring a FE310-G000 SoC integrating SiFive's E31 RISC-V core.

SiFive's Freedom e300 for the DECA Max10 FPGA

OSdev exploration

Read and write a memory-mapped SiFive system-on-chip UART

Bare metal programming on the RED-V Thing Plus board (SiFive RISC-V FE310 SoC)

Bare Bones OSDev template for the HiFive-1 RISC-V board from SiFive!

A custom development board for the SiFive FE310, a RISC-V microcontroller.

RISC-V Engine Emulator

Stuff related to RISC-V

Development of some Risc-V drivers for the FE310-G002 (SoC)

Board files for the sifive/freedom git to support other fpga plattforms