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Simple RISC CPU. 根据夏宇闻《Verilog数字系统设计教程》第2版17.1节简化RISC_CPU设计修改

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Name		Name	Last commit message	Last commit date
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src		src
test		test
.gitignore		.gitignore
LICENSE		LICENSE
README.md		README.md

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Simple RISC CPU

代码格式优化、一键编译仿真

⛓ Prerequisites

编译工具：iverilog
可选择使用：gtkwave，查看波形

🛠️ 运行

bash ./test/test.sh

将生成 risc_cpu_test.vvp 文件在 ./test 下，并通过 vvp 运行仿真，波形文件将保存在 ./test/wave.fst ，可通过gtkwave等程序查看。

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Simple RISC CPU. 根据夏宇闻《Verilog数字系统设计教程》第2版17.1节简化RISC_CPU设计修改

cpu verilog iverilog risc-cpu

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